CN101154031A - Method of forming hardmask pattern of semiconductor device - Google Patents
Method of forming hardmask pattern of semiconductor device Download PDFInfo
- Publication number
- CN101154031A CN101154031A CNA2007100006027A CN200710000602A CN101154031A CN 101154031 A CN101154031 A CN 101154031A CN A2007100006027 A CNA2007100006027 A CN A2007100006027A CN 200710000602 A CN200710000602 A CN 200710000602A CN 101154031 A CN101154031 A CN 101154031A
- Authority
- CN
- China
- Prior art keywords
- hard mask
- pattern
- layer
- overlayers
- mask layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 238000012797 qualification Methods 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 68
- 238000005516 engineering process Methods 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 238000000059 patterning Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 229920002313 fluoropolymer Polymers 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
A method for forming the hard mask pattern on the semiconductor device comprises: forming a first hard mask layer on the semiconductor substrate; forming a first and second structure on the first hard mask layer, wherein the first and second structures are produced by the same material and the first and second structures define a first space; respectively forming a first and second covering layers on the first and second structures, wherein, the first and second covering layers conform with the first and second structures and the first and second covering layers define the space therebetween and arranging to expose the lower layer; forming a filling layer to fill the defined space between the first and second covering layers; removing the first and second covering layers to provide a first and second structure and a third structure therebetween; etching the first hard mask layer to obtain a first second and third hard mask patterns by using the first second and third structures.
Description
The cross reference of related application
The application requires the right of priority of Korean Patent Application No. 10-2006-95993 that submitted on September 29th, 2006 and the Korean Patent Application No. 10-2006-128767 that submitted on Dec 15th, 2006, and it incorporates this paper in full by reference into.
Technical field
The present invention relates to a kind of method of making semiconductor devices, and more specifically, relate to a kind of method that forms hard mask pattern, wherein the spacing of pattern is less than the resolution of use exposure sources.
Background technology
The minimum spacing of the pattern that forms in the photoetching process changes according to the exposure light wavelength of using in the exposure sources.Along with the quick raising of semiconductor devices degree of integration, must use wavelength to be shorter than the spacing that the present light that uses wavelength reduces pattern.For this purpose, can use X ray or electron beam, but they are owing to technical matters, throughput rate etc. still are in experimental stage.Therefore double exposure and etch process (DEET) have been advised using.
Figure 1A is the figure that describes traditional double exposure etch process to 1C.
With reference to Figure 1A, the first photoresist PR1 is coated on etching target layer 11 and the Semiconductor substrate 10.By exposure and developing process with the first photoresist PR1 patterning after, use the first photoresist PR1 behind this patterning as this etching target layer 11 of mask etching.This moment, the live width of etched etching target layer 11 was that 150nm and interval width are 50nm.
Remove the first photoresist PR1.The second photoresist PR2 is coated on the whole surface.As shown in Figure 1B, by exposure and developing process with the second photoresist PR2 patterning, so that partially-etched destination layer 11 exposures.
As mask, this etching target layer 11 of etching forms the pattern that live width and interval width are 50nm, thus as shown in Fig. 1 C once more by the second photoresist PR2 behind the use patterning.Remove the second photoresist PR2 subsequently.
In DEET, the aerial image alignment precision during the exposure-processed of the second photoresist PR2 (overlay accuracy) changes directly related with the critical dimension (CD) of final pattern.The aerial image alignment precision of exposure sources is difficult to be controlled at below the 10nm in the reality, the feasible thus CD variation that is difficult to reduce final pattern.In addition, be difficult to also control that (optical proximity correction, the circuit that OPC) carries out separates by optical near-correction during the re-expose.
Summary of the invention
One embodiment of the invention relate to a kind of method that forms the hard mask pattern of semiconductor devices, and the spacing of wherein said pattern is less than the resolution of use exposure sources.
In one embodiment, the method that forms the hard mask pattern of semiconductor devices comprises the steps: to form therein on the Semiconductor substrate of etching target layer and forms first hard mask layer and second hard mask layer; On described second hard mask layer, form first pattern; On the surface of described first pattern, form spacer; Form therein and form second pattern between first pattern of spacer; Remove described spacer; Pass through described second hard mask layer of etch process etching and first hard mask layer with use first pattern and second pattern as etching mask, thereby form hard mask pattern.
In one embodiment, comprise in the method that forms hard mask pattern on the semiconductor devices: on Semiconductor substrate, form first hard mask layer and second hard mask layer; On second hard mask layer, form first and second patterns of the first kind; On first and second patterns of the described first kind, form first and second overlayers respectively, described first and second overlayers are conformal with the pattern of the corresponding first kind, described first and second overlayers limit they each other the interval and be set to expose following layer; Form packed layer to fill the interval that limits between first and second overlayers; Remove first and second overlayers with second pattern of first pattern that the first kind is provided, the first kind be arranged on additional pattern between first and second patterns of the first kind; Use first pattern of the first kind, second pattern and described second hard mask layer of additional pattern etching and first hard mask layer of the first kind, to obtain hard mask pattern.
In another embodiment, comprise in the method that forms hard mask pattern on the semiconductor devices: on Semiconductor substrate, form first hard mask layer.Form first and second structures on first hard mask layer, described first and second structures are made by identical materials, first and second structure qualifications, first spacing.On described first and second structures, form first and second overlayers respectively, described first and second overlayers are conformal with first and second structures respectively, first and second overlayers limit their intervals each other, and be set to expose following layer, form packed layer to fill the interval that limits between first and second overlayers.Remove first and second overlayers described first structure, second structure to be provided and to be arranged on the 3rd structure between first and second structures, the first and the 3rd structure qualification second spacing, the second and the 3rd structure qualification the 3rd spacing.Use described first, second and the 3rd etch structures first hard mask layer respectively, to obtain first, second and the 3rd hard mask pattern.
In another embodiment, this method further is included in second hard mask layer is provided under first hard mask layer, wherein etching step comprises described first and second hard mask layers of etching to obtain first, second and the 3rd hard mask pattern, and each hard mask pattern comprises described first and second hard mask layers.
In another embodiment, described substrate defines dense area and isolated area, and the dense area per unit area has than the more transistor of isolated area.This method further is included in pattern is provided on the fill area, and wherein said pattern covers dense area and exposure isolated area expose so that be provided at the partially filled layer of isolated area; And remove the packed layer that exposes in the isolated area, the packed layer in the dense area is kept perfectly.Described packed layer is included in spin-on-glass layer (spin on glass).Described pattern is the photoresist pattern.Adopt identical technology to remove the described pattern and first and second overlayer.
In another embodiment, described first spacing is greater than second spacing or the 3rd spacing, and the second and the 3rd spacing is basic identical.The size of the second or the 3rd spacing is less than the ultimate resolution of the exposure sources that is used to form first and second structures.
Description of drawings
Figure 1A is the synoptic diagram of describing traditional secondary exposure etching technique to 1C.
Fig. 2 to 9 is sectional views of describing the method for the hard mask pattern that forms semiconductor devices according to an embodiment of the invention.
Embodiment
Be described with reference to the accompanying drawings according to a specific embodiments of the present invention.
With reference to Fig. 2, Semiconductor substrate 10 comprises memory cell region C ell, selects transistor area ST and outer peripheral areas Peri.Memory cell region C ell is the zone that forms cell transistor.Select transistor area ST to comprise drain electrode selection wire (DSL) and drain selection line (SSL).Outer peripheral areas Peri comprises peripheral circuit.
On Semiconductor substrate 100, form etching target layer 101.Etching target layer 101 comprises tunnel layer 101a, be used for the conductive layer 101b of floating grid, dielectric layer 101c, be used to control the conductive layer 101d and the insulation course 101e of grid.This embodiment is by describing in order to following method: wherein hard mask pattern is used to form storage unit and transistorized gate pattern.The first hard mask layer 102A is formed on the etching target layer 101.The first hard mask layer 102A comprises agraphitic carbon.
The second hard mask layer 102B is formed on the first hard mask layer 102A.The second hard mask layer 102B comprises SiON or nitride.Subsequently polysilicon layer 103 is formed on the second hard mask 102B.
With reference to Fig. 3, bottom anti-reflective coating (BARC) layer 104 is formed on the polysilicon layer 103.After photoresist being applied on the BARC layer 104, expose and development treatment to form the first photoresist pattern 105.
With reference to Fig. 4, etch process adopts the first photoresist pattern 105 to carry out as mask, with etching BARC layer 104 and polysilicon layer 103, the second hard mask layer 102B is exposed.Form poly-silicon pattern 103P by polysilicon layer 103 like this.The first photoresist pattern 105 and BARC layer 104 are removed by peeling off (strip) processing.
With reference to Fig. 5, overlayer 106 is formed on sidewall and the top of poly-silicon pattern 103P.This overlayer 106 is formed by agraphitic carbon.Overlayer 106 can be by carrying out 30 to 70 seconds preprocessing process, carrying out 5 to 15 seconds adhesive layer deposition processes and the fluorocarbon polymer that carried out 2 to 10 seconds is handled and at least once to be formed.In the case, carrying out the used time of this technology can be according to the thickness decision of overlayer 106.After pre-service, carry out adhesive layer deposition processes and fluorocarbon polymer and handle, can further carry out polymkeric substance and puncture (break-through) processing.This polymkeric substance punctures to be handled and can carry out or carry out when adjacent cover layer 106 connects when the profile that is necessary to make overlayer 106 be better.If overlayer 106 forms by said method, then this overlayer forms with poly-silicon pattern 103P conformally, and has substantially invariable thickness.Therefore, the sidewall of overlayer 106 is vertical substantially.
With reference to Fig. 6, spin-on-glass (SOG) layer 107 is formed on the surface that comprises overlayer 106.SOG layer 107 is filled around the interval between the overlayer 106 of poly-silicon pattern 103P.
With reference to Fig. 7, the second photoresist pattern 108 is formed on the SOG layer 107, to keep SOG layer 107 at memory cell region C ell, in memory cell region C ell, will form gate pattern densely, and remove the SOG layer 107 (for example ST and Peri) in other zones that wherein can not form gate pattern densely.
Being formed on the SOG layer 107 selected on transistor area ST and the outer peripheral areas Peri is removed by etch process by adopting the second photoresist pattern 108.Before forming the second photoresist pattern 108, can form the BARC layer with the diffuse reflection in the exposure process that prevents to be used to form the second photoresist pattern 108.Preferred SOG layer 107 is removed by wet etching process.If SOG layer 107 is removed by dry method etch technology, then the second hard mask layer 102B can use nitride (SiN) to replace nitride (SiON) deposition of doped with oxygen, to improve the etching selectivity with the second hard mask layer 102B.
With reference to Fig. 8, remove the second photoresist pattern 108.SOG pattern 107P is formed on memory cell region C ell, will form gate pattern densely in memory cell region C ell.Can adopt oxygen gas plasma to remove the second photoresist pattern 108.Also remove overlayer 106 in this embodiment simultaneously.Therefore, owing to do not need to remove the additional process of overlayer 106, the processing time can shorten and can save cost.
With reference to Fig. 9, by adopting poly-silicon pattern 103P and SOG pattern 107P the etch process order etching second hard mask layer 102B and the first hard mask layer 102A as etching mask.Remove poly-silicon pattern 103P and SOG pattern 107P.Formation comprises the hard mask pattern 102P of the first and second hard masks.Etching target layer 101 is etched with at memory cell region C ell, selects transistor area ST and outer peripheral areas Peri to form gate pattern by adopting hard mask pattern 102P.
In the content that gate etch handles the present invention has been described as above-mentioned in relevant flash memory, carrying out.But the present invention can be applied in the etch process of other types, for example isolated groove etch process and contact etch technology.The present invention can also be applied to various semiconductor devices, for example DRAM, SRAM, NAND flash memory or NOR flash memory.
As mentioned above, according to the present invention, make with photoresist that pattern forms first pattern by exposure technology, adopt agraphitic carbon that overlayer (or spacer) is formed on the sidewall of first pattern, fill the interval between first pattern, form second hard mask pattern thus.Therefore can form the mask of spacing less than the resolution of exposure sources.
In addition, can be by the single exposure method but not the re-expose method forms the unit pattern with fine and close pattern and sensitive aerial image alignment precision.Therefore can prevent that the pattern dimension that is caused by the medium and small aerial image alignment tolerance limit of re-expose method from changing.
In addition,, therefore can reduce the number of treatment step, can shorten the processing time and can save cost because spacer uses agraphitic carbon to form.
Above-mentioned embodiment of the present invention is descriptive, and non-limiting.Various variations and equivalent can be arranged, and in view of of the present invention open, other conspicuous interpolations, minimizing or improvement are considered as falling in the scope of claims.
Claims (18)
1. method that on semiconductor devices, forms hard mask pattern, described method comprises:
On Semiconductor substrate, form first hard mask layer and second hard mask layer;
On described second hard mask layer, form first and second patterns of the first kind;
On first and second patterns of the described first kind, form first and second overlayers respectively, described first and second overlayers are conformal with corresponding first kind pattern, first and second overlayers limit their intervals each other, and are set to expose following layer;
Form packed layer to fill the interval that limits between first and second overlayers;
Remove described first and second overlayers with second pattern of first pattern that the first kind is provided, the first kind be arranged on additional pattern between first and second patterns of the first kind; With
Use second pattern of first pattern, the first kind of the described first kind and described second hard mask layer of additional pattern etching and first hard mask layer to obtain hard mask pattern.
2. the process of claim 1 wherein that described substrate defines dense area and isolated area, described dense area per unit area has than the more transistor of isolated area, and described method further comprises:
The pattern of second type is provided on the fill area, and the pattern covers of wherein said second type is in the dense area and expose isolated area, exposes so that be provided at the partially filled layer of isolated area; With
Remove the packed layer that exposes in the isolated area, the packed layer in the dense area is kept perfectly.
3. the method for claim 2 further comprises:
Remove the pattern of described second type, wherein said first and second overlayers adopt identical method to remove to remove the pattern of second type.
4. the process of claim 1 wherein that described first and second overlayers adopt agraphitic carbon to form.
5. the process of claim 1 wherein that described first and second overlayers are set to have essentially identical thickness.
6. the process of claim 1 wherein that described first hard mask layer is formed by agraphitic carbon.
7. the process of claim 1 wherein that described second hard mask layer is formed by SiON.
8. the process of claim 1 wherein that described second hard mask layer is formed by nitride.
9. the process of claim 1 wherein that first and second patterns of the described first kind are formed by polysilicon, wherein said following layer is second hard mask layer.
10. the process of claim 1 wherein that described packed layer forms (SOG) by spin-on-glass.
11. a method that forms hard mask pattern on semiconductor devices, described method comprises:
On Semiconductor substrate, form first hard mask layer;
Form first and second structures on described first hard mask layer, described first and second structures form with identical materials, first and second structure qualifications, first spacing;
Form first and second overlayers respectively on described first and second structures, described first and second overlayers are conformal with first and second structures respectively, and first and second overlayers limit their intervals each other, and are set to expose following layer;
Form packed layer to fill the interval that limits between described first and second overlayers;
Remove first and second overlayers first structure, second structure to be provided and to be arranged on the 3rd structure between first and second structures, the described first and the 3rd structure qualification second spacing, the second and the 3rd structure qualification the 3rd spacing; With
Use first, second and described first hard mask layer of the 3rd etch structures to obtain first, second and the 3rd hard mask pattern respectively.
12. the method for claim 11 further comprises:
Second hard mask layer is provided under first hard mask layer, and wherein said etching step comprises etching first and second hard mask layers to obtain first, second and the 3rd hard mask pattern, and each hard mask pattern all comprises first and second hard mask layers.
13. the method for claim 11, wherein said substrate defines dense area and isolated area, and described dense area per unit area has than the more transistor of isolated area, and described method further comprises:
Pattern is provided on the fill area, and wherein said pattern covers is in the dense area and expose isolated area, exposes so that be provided at the partially filled layer of isolated area; With
Remove the packed layer that exposes in the isolated area, the packed layer in the dense area is kept perfectly.
14. the method for claim 13, wherein said packed layer comprises the spin-on-glass layer.
15. the method for claim 14, wherein said pattern are the photoresist patterns.
16. the method for claim 15, the wherein said pattern and first and second overlayers use identical method to remove.
17. the method for claim 11, wherein said first spacing are greater than second spacing or the 3rd spacing, the second and the 3rd spacing is basic identical.
18. the method for claim 17, wherein said second or the size of the 3rd spacing less than the ultimate resolution of the exposure sources that is used to form described first and second structures.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR200695993 | 2006-09-29 | ||
| KR20060095993 | 2006-09-29 | ||
| KR2006-95993 | 2006-09-29 | ||
| KR2006-128767 | 2006-12-15 | ||
| KR2006128767 | 2006-12-15 | ||
| KR1020060128767A KR100905827B1 (en) | 2006-09-29 | 2006-12-15 | Method for forming hard mask pattern in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101154031A true CN101154031A (en) | 2008-04-02 |
| CN101154031B CN101154031B (en) | 2010-12-01 |
Family
ID=39255759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007100006027A Expired - Fee Related CN101154031B (en) | 2006-09-29 | 2007-01-09 | Method of forming hardmask pattern of semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR100905827B1 (en) |
| CN (1) | CN101154031B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102478763A (en) * | 2010-11-30 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Photoetching method |
| CN103367258A (en) * | 2012-04-06 | 2013-10-23 | 力晶科技股份有限公司 | Semiconductor circuit structure and manufacturing process thereof |
| CN109390285A (en) * | 2017-08-08 | 2019-02-26 | 联华电子股份有限公司 | Contact structures and preparation method thereof |
| CN110391134A (en) * | 2018-04-17 | 2019-10-29 | 三星电子株式会社 | Semiconductor devices and its manufacturing method |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100924611B1 (en) | 2007-05-11 | 2009-11-02 | 주식회사 하이닉스반도체 | Method of forming a micro pattern in a semiconductor device |
| KR100929302B1 (en) | 2007-12-26 | 2009-11-27 | 주식회사 하이닉스반도체 | Pattern formation method of semiconductor device |
| KR100946026B1 (en) * | 2008-05-14 | 2010-03-09 | 주식회사 하이닉스반도체 | Method of forming pattern for semiconductor |
| KR100953036B1 (en) * | 2008-05-26 | 2010-04-14 | 주식회사 하이닉스반도체 | Method for forming fine patterns of a semiconductor device |
| KR20100104861A (en) | 2009-03-19 | 2010-09-29 | 삼성전자주식회사 | Method of forming patterns for semiconductor device |
| KR101616744B1 (en) * | 2009-08-25 | 2016-04-29 | 삼성전자주식회사 | Photomask, method of exposing a substrate to light, method of forming a pattern, and method of manufacturing a semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020024415A (en) * | 2000-09-25 | 2002-03-30 | 윤종용 | Method of forming pattern of semiconductor device |
| KR100574999B1 (en) | 2004-12-06 | 2006-04-28 | 삼성전자주식회사 | Method of forming pattern of semiconductor device |
| KR100642886B1 (en) | 2005-06-27 | 2006-11-03 | 주식회사 하이닉스반도체 | Method of forming a micro pattern in a semiconductor device |
-
2006
- 2006-12-15 KR KR1020060128767A patent/KR100905827B1/en active IP Right Grant
-
2007
- 2007-01-09 CN CN2007100006027A patent/CN101154031B/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102478763A (en) * | 2010-11-30 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Photoetching method |
| CN103367258A (en) * | 2012-04-06 | 2013-10-23 | 力晶科技股份有限公司 | Semiconductor circuit structure and manufacturing process thereof |
| US9196623B2 (en) | 2012-04-06 | 2015-11-24 | Powerchip Technology Corporation | Semiconductor circuit structure and process of making the same |
| CN103367258B (en) * | 2012-04-06 | 2016-05-25 | 力晶科技股份有限公司 | Semiconductor circuit structure and manufacturing process thereof |
| CN109390285A (en) * | 2017-08-08 | 2019-02-26 | 联华电子股份有限公司 | Contact structures and preparation method thereof |
| CN109390285B (en) * | 2017-08-08 | 2021-02-12 | 联华电子股份有限公司 | Contact structure and manufacturing method thereof |
| US11018141B2 (en) | 2017-08-08 | 2021-05-25 | United Microelectronics Corp. | Contacts and method of manufacturing the same |
| US11653491B2 (en) | 2017-08-08 | 2023-05-16 | United Microelectronics Corp. | Contacts and method of manufacturing the same |
| CN110391134A (en) * | 2018-04-17 | 2019-10-29 | 三星电子株式会社 | Semiconductor devices and its manufacturing method |
| CN110391134B (en) * | 2018-04-17 | 2024-04-30 | 三星电子株式会社 | Semiconductor device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20080029719A (en) | 2008-04-03 |
| CN101154031B (en) | 2010-12-01 |
| KR100905827B1 (en) | 2009-07-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101154031B (en) | Method of forming hardmask pattern of semiconductor device | |
| US7384874B2 (en) | Method of forming hardmask pattern of semiconductor device | |
| CN101290867B (en) | Method of forming micro pattern of semiconductor device | |
| TWI471903B (en) | Frequency doubling using spacer mask | |
| US10475648B1 (en) | Method for patterning a semiconductor structure | |
| JP2008066689A (en) | Manufacturing method of semiconductor device | |
| US20170338116A1 (en) | Method for Patterning a Substrate Using a Layer with Multiple Materials | |
| JP2011176150A (en) | Method of manufacturing semiconductor device | |
| KR100965011B1 (en) | Method of forming a micro pattern in a semiconductor device | |
| US10734284B2 (en) | Method of self-aligned double patterning | |
| US10410863B2 (en) | Methods for integrated circuit design and fabrication | |
| US9911604B1 (en) | Sidewall spacer pattern formation method | |
| US7955985B2 (en) | Method of forming micro pattern of semiconductor device | |
| US8110507B2 (en) | Method for patterning an active region in a semiconductor device using a space patterning process | |
| KR20090049379A (en) | Method for manufacturing flash memory device | |
| KR100940275B1 (en) | Method for forming gate pattern in semiconductor device | |
| US7381652B2 (en) | Method of manufacturing flash memory device | |
| US8057987B2 (en) | Patterning method of semiconductor device | |
| CN111403269B (en) | Method for manufacturing patterned structure | |
| KR101095041B1 (en) | Method for forming the fine pattern of semiconductor devices | |
| KR20100081019A (en) | Method for manufacuring semiconductor device | |
| KR20080090849A (en) | Method for forming overlay vernier in semiconductor device | |
| KR19980045163A (en) | Manufacturing Method of Semiconductor Device | |
| KR20100129544A (en) | Method for forming pattern using negative spacer patterning technology | |
| KR20050059926A (en) | Method of forming a contact plug in a flash memory devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101201 Termination date: 20170109 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |