KR20100129544A - Method for forming pattern using negative spacer patterning technology - Google Patents

Method for forming pattern using negative spacer patterning technology Download PDF

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Publication number
KR20100129544A
KR20100129544A KR1020090048152A KR20090048152A KR20100129544A KR 20100129544 A KR20100129544 A KR 20100129544A KR 1020090048152 A KR1020090048152 A KR 1020090048152A KR 20090048152 A KR20090048152 A KR 20090048152A KR 20100129544 A KR20100129544 A KR 20100129544A
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KR
South Korea
Prior art keywords
pattern
polysilicon
line width
semiconductor device
forming
Prior art date
Application number
KR1020090048152A
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Korean (ko)
Inventor
구선영
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020090048152A priority Critical patent/KR20100129544A/en
Publication of KR20100129544A publication Critical patent/KR20100129544A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

Abstract

The present invention relates to a method of constructing a frame for applying a spacer patterning process in a DRAM, wherein a plurality of line widths are reduced when forming a pattern having a larger size than a pattern of a cell region such as an alignment key or an overlay vernier. By forming a to prevent unnecessary patterns from appearing in the subsequent process provides an effect of preventing the collapse of the pattern or lifting phenomenon.

Description

Pattern forming method for negative spacer patterning process {Method for forming pattern using negative spacer patterning technology}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a pattern for applying spacer patterning in a semiconductor memory device.

BACKGROUND With the rapid spread of information media such as computers, semiconductor memory devices are also rapidly developing. In terms of its function, the semiconductor memory device must operate at a high speed and have a large storage capacity. In order to meet these demands, it is required to develop process equipment or process technology for manufacturing semiconductor memory devices having low manufacturing atoms, and having improved integration, reliability, and electrical characteristics for accessing data.

Photolithography is one of the methods for improving the degree of integration of semiconductor memory devices. Photolithography is a technique for exposing and developing a photoresist material with a deep ultra violet (DUV) light source, which is a short wavelength chemically amplified type such as ArF (193 nm) or VUV (157 nm), to form a fine pattern.

As semiconductor device sizes become smaller and smaller, controlling critical dimensions of pattern line widths has become an important issue when applying photolithography technology. In general, the speed of a semiconductor device is faster as the critical dimension of the pattern line width, that is, the size of the pattern line is smaller, and the performance of the device is also improved. However, it is difficult to form a line-and-space pattern of 40 nm or less in a single exposure process due to the limitation of photolithography technology using ArF exposure equipment having a numerical aperture of 1.2 or less. Accordingly, double patterning technology has been developed as part of resolution enhancement and process margin expansion of photolithography technology. Double patterning is a technique for exposing and developing two masks on a photoresist-coated wafer, respectively, to form complex patterns, dense patterns, and isolated patterns. .

On the other hand, since the double patterning technique uses two different masks for patterning, the manufacturing cost and turn-around-time are lower than the patterning technique using the single mask, resulting in lower throughput. . In addition, when forming a pattern having a pitch smaller than the resolution of the exposure equipment in the cell region, the aerial images are overlapped to obtain a pattern of a desired shape, and overlay misalignment at the time of alignment. There are several disadvantages such as this occurring.

In order to alleviate this drawback, double exposure etch technology (DEET) and spacer patterning technology (SPT) have been developed and applied to the semiconductor device mass production process. DEET is a technique of forming a first pattern having a line width twice as large as a desired pattern line width, and then forming a second pattern having the same line width period as the first pattern between neighboring first patterns.

However, since the DEET method uses two kinds of masks or one mask to form a pattern having a desired resolution, the process step is complicated, manufacturing costs are increased, and the alignment of the pattern when forming the second photoresist pattern is achieved. Misalignment is likely to occur in the process.

Another technique, the SPT method, is a technique in which a self-align method is applied to prevent misalignment by performing a mask process only once to form a pattern of a cell region. However, the process step is complicated because an additional mask process is required to form a pattern in the core and peri regions or to separate the pattern portion of the mini cell block region. Since it is difficult to control the line width, the uniformity of the fine pattern line width in the semiconductor device determined by the line width of the spacer is low.

In the negative spacer patterning process, the gap fill polysilicon may be etched, and then a mask mask may be formed into the dark region using a pad mask without applying a trim process that removes the remaining polysilicon on the wide sidewall. Looking at it as shown in Figures 1a to 1g.

Referring to FIG. 1A, a hard mask 102, a polysilicon 104, an amorphous carbon 106, and silicon oxy are formed on a semiconductor substrate 100 on which cell regions, peripheral circuit regions, alignment keys, and overlay vernier regions are defined. The nitride 108 and the antireflection film 110 are sequentially deposited. Subsequently, after the photoresist film (not shown) is applied to the upper portion, the photoresist pattern 112 is formed.

Referring to FIG. 1B, the photoresist layer 112 is etched to form a polysilicon pattern 104a by etching the lower etched layer until the hard mask 102 is exposed, and the etched layer formed on the polysilicon 104. Is removed by a stripping process.

Referring to FIG. 1C, the spacer material 120 is deposited on the entire surface of the pattern formed in FIG. 1B.

Referring to FIG. 1D, a polysilicon (not shown) is gapfilled over the spacer material 120. In the Alignment Key / Overlay Vernier area where the space is relatively large, the polysilicon is not filled properly, so the thickness is thin. Afterwards, the etchback process removes the polysilicon at the bottom and the pattern The polysilicon of the sidewalls remains in the form of spacers. At this time, a polysilicon pattern 125 in the form of a spacer is formed on the pattern sidewall existing in the overlay vernier region, and another unnecessary polysilicon pattern 132 is formed on the sidewall of the peripheral circuit region.

Referring to FIG. 1E, a photoresist film is coated, exposed, and developed to cover a portion of a peripheral circuit region and a cell region to form a photoresist pattern 130.

Referring to FIG. 1F, an etchback process is performed to etch away the exposed spacer material 120 in an area not covered by the photoresist pattern 130. In this case, the polysilicon pattern 125 having a spacer shape formed on the sidewall of the pattern existing in the overlay vernier region in FIG. 1E is formed as an unnecessary isolation pattern 125a.

Referring to FIG. 1G, the hard mask at the bottom may be etched using the pattern of the cell region and the overlay vernier region formed in FIG. 1F as a barrier. The isolation pattern 127 of the overlay vernier region formed in this process becomes relatively vulnerable to pattern collapse due to a relatively large aspect ratio, and may cause problems such as lifting. In addition, the process is complicated because the polysilicon pattern 132a additionally formed at the end of the peripheral circuit area has to use another mask to remove it.

Referring to FIG. 2, a representative example of a conventional alignment key is shown. The size of the space between the pattern and the pattern is about 1.6 μm, and when exposed to the exposed spacer material 120 as in the process of FIG. In the um box, a pattern spaced apart by the interval of the spacer material 120, that is, a pattern having a relatively high aspect ratio is formed on the left and right to have a fragile shape that is easily broken.

The present invention is a technique for manufacturing a semiconductor device for preventing the collapse of the pattern or lifting when forming a space in a negative manner in the spacer patterning process.

The semiconductor device of the present invention is characterized in that one overlay vernier pattern is formed by arranging a plurality of fine patterns in a matrix.

The line width of the fine pattern is characterized in that less than 1/3 of the overlay vernier line width, the line width of the overlay vernier pattern is characterized in that the sum of three times the fine pattern line width and two times the fine pattern interval, The interval between the fine patterns may be the same as the thickness of the spacer formed on the sidewall of the gate pattern of the cell region.

In the method of manufacturing a semiconductor device of the present invention, depositing a first polysilicon on the etched layer, patterning the first polysilicon using a mask. Depositing a spacer material over the first polysilicon and the etched layer, depositing and etching a gapfill polysilicon on the spacer material, forming a photoresist pattern covering a portion of a peripheral circuit region and a cell region, Etching the spacer material exposing the photoresist pattern as a barrier to form a polysilicon pattern comprising first polysilicon and the gapfill polysilicon; and etching the etched layer using the polysilicon pattern as a barrier. .

The etched layer may be formed by sequentially depositing amorphous carbon on the first polysilicon, silicon oxynitride on the upper surface, and an antireflection film on the upper side, wherein the spacer material is LP-PEOS. .

According to the present invention, when a large pattern is formed in a cell mask step in a cell mask step, a pattern larger in size than a cell area existing in an alignment key or an overlay vernier area is formed into a pillar or hole array pattern, thereby eliminating unnecessary patterns. Once formed, it eliminates the need for another mask to remove it, reducing the number of masks needed to form one layer, increasing throughput and reducing process costs.

In addition, since the thickness of the polysilicon deposited between the pattern and the pattern, such as the cell region, is thick, there is an effect of preventing the collapse of the pattern or lifting phenomenon.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In order to solve the conventional problem, a large area of the pattern, such as an overlay vernier area, is reduced to a gap between the patterns and a line width similar to the pattern of the cell area so that the spacers are not formed on the sidewalls when gapfilling and etching back polysilicon. Should be. To this end, there is a method of forming a pattern into a pillar pattern or a hole array pattern.

Referring to FIG. 3A, a layout for forming a pattern existing in a typical alignment key area into a pattern having a small size and integrated hole array form is shown. A line pattern having a line width of 1.6 mu m is conventionally formed into three hole array patterns, and the line width is 0.34 mu m and the interval between the patterns is 0.29 mu m.

3B is a layout for making a smaller and integrated pillar pattern. As in FIG. 3A, a line pattern having a line width of 1.6 μm is formed into three pillar patterns, and the line width is 0.3 μm and the interval between the patterns is 0.35 μm.

The pillar-shaped pattern of Figure 3b is as shown in Figures 4a to 4d, the hole-array pattern of Figure 3a is formed as shown in Figures 5a to 5d, the schematic diagram of the top is a plan view from above of the pattern is formed, the bottom is The sectional view seen from the side is shown.

Referring to FIG. 4A, a conventional line pattern is formed of a pillar pattern 400 having a pillar shape.

Referring to FIG. 4B, a schematic diagram of a spacer material 402 deposited on the pillar pattern 400 is illustrated. It is preferable to use LP-TEOS as the spacer material.

Subsequently, when the gapfill polysilicon 404 is deposited as shown in FIG. 4C, since the gap between the patterns is narrowed like the cell region, the polysilicon 404 is formed to be similar to the thickness of the cell region pattern, so that the polysilicon 404 is formed. After etching back, the gapfill polysilicon 404 remains unremoved.

Referring to FIG. 4D, even after the spacer 402 is etched back and removed, densely aligned pillar patterns 407 are formed so that the polysilicon patterns do not form easily and are not collapsed.

Even in the case of the hole pattern, as shown in FIG. 5C, the gap-filled polysilicon 505 is thick in a narrow space of the hole when the gapfill polysilicon 505 is deposited, and thus is not removed even in the subsequent polysilicon 505 etchback process. Accordingly, even when the exposed spacer material 503 is etched and removed as shown in FIG. 5D, the polysilicon pattern does not easily collapse.

Referring to FIG. 6A, a layout for forming a pattern of an overlay vernier region into a pillar pattern in the above manner is illustrated, and FIG. 6B illustrates a layout for forming a hole array pattern.

In the present invention, the size and aligned number of pillars and holes may vary depending on the size of the components forming the pattern, and also depends on the pattern size of the cell region during gap fill polysilicon deposition.

In addition, frame elements that are difficult to form in pillar- and hole-shaped patterns may be formed in a line and space pattern so as to have a similar size to the pattern of the cell zero region, thereby preventing unnecessary patterns from being easily collapsed. .

In the semiconductor device manufacturing method of the present invention, when forming a pattern having a large line width of an overlay vernier region, one layer is formed through a method of forming a plurality of patterns by reducing a gap between patterns and reducing a line width of a pattern, such as a pattern of a cell region. It is possible to prevent the formation of unnecessary patterns in the process of forming a. This reduces process costs and improves yield.

In addition, the preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and modifications are the following patents It should be regarded as belonging to the claims.

1A to 1D are cross-sectional views illustrating a conventional spacer patterning process.

2 is a cross-sectional view showing a pattern of a conventional alignment key region.

3A is a layout for forming a pattern of an alignment key region into a hole array pattern.

3B is a layout for forming a pattern of an alignment key region into a pillar pattern.

4A to 4D illustrate a process of forming a pillar pattern when forming a cell pattern.

5A to 5D illustrate a process of forming a hole array pattern when forming a cell pattern.

6A-6B are cross-sectional views illustrating a layout for forming an overlay vernier.

Claims (6)

A semiconductor device, characterized in that one overlay vernier pattern is formed by arranging a plurality of fine patterns in a matrix. The method of claim 1, The line width of the fine pattern is a semiconductor device, characterized in that less than 1/3 of the line width of the overlay vernier pattern. The method of claim 1, The line width of the overlay vernier pattern is a semiconductor device, characterized in that the sum of three times the fine pattern line width and twice the interval of the fine turn. The method of claim 1, Wherein the spacing of the fine patterns is equal to the thickness of the spacers formed on the sidewalls of the gate patterns of the cell region. Depositing a first polysilicon over the etched layer; Patterning the first polysilicon using a mask; Depositing a spacer material over the first polysilicon and the etched layer; Depositing and etching a gapfill polysilicon on the spacer material; Forming a photoresist pattern covering a portion of the peripheral circuit region and the cell region; Etching the spacer material exposing the photoresist pattern as a barrier to form a polysilicon pattern comprising first polysilicon and the gapfill polysilicon; And Etching the etched layer using the polysilicon pattern as a barrier Method of manufacturing a semiconductor device comprising a. The method of claim 5, The etched layer is a method of manufacturing a semiconductor device, characterized in that the deposition of amorphous carbon on the first polysilicon, silicon oxynitride on the upper portion, and an anti-reflection film on the top.
KR1020090048152A 2009-06-01 2009-06-01 Method for forming pattern using negative spacer patterning technology KR20100129544A (en)

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