CN101150108A - 半导体封装构造 - Google Patents

半导体封装构造 Download PDF

Info

Publication number
CN101150108A
CN101150108A CNA2007101672805A CN200710167280A CN101150108A CN 101150108 A CN101150108 A CN 101150108A CN A2007101672805 A CNA2007101672805 A CN A2007101672805A CN 200710167280 A CN200710167280 A CN 200710167280A CN 101150108 A CN101150108 A CN 101150108A
Authority
CN
China
Prior art keywords
groove
chip
lead foot
packaging structure
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2007101672805A
Other languages
English (en)
Inventor
曾燕雯
谢玫璘
徐志宏
陈光雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CNA2007101672805A priority Critical patent/CN101150108A/zh
Publication of CN101150108A publication Critical patent/CN101150108A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

一种半导体封装构造。此半导体封装构造至少包含有芯片承座、芯片、导脚、凹槽及封胶体。芯片设置于芯片承座上，导脚设置于芯片承座的外周围，并电性连接至芯片，其中凹槽形成于导脚的上表面，并延伸至导脚的外侧面。封胶体用以包覆芯片承座、芯片、导脚及凹槽。

Description

半导体封装构造
技术领域
本发明是有关于一种半导体封装构造，且特别是有关于半导体封装构造的导脚的结构。
背景技术
在半导体生产过程中，集成电路封装(IC package)是制造的重要步骤的一，其用以保护IC芯片与提供外部电性连接。其中，IC导线架(IC leadframe)提供IC芯片安放的基座，并可将IC芯片与印刷电路板连接起来。
随着集成电路的积集度的日益提升，以及对高效能电子产品的需求，驱使封装技术朝向提高封装密度、减小封装尺寸、以及缩短传输距离等方向发展，以适应集成电路组件的尺寸微缩化以及持续成长的输入/输出(Input/Output；I/O)数的趋势。
集成电路的封装型态的种类繁多，其中相当常见的一种封装型态是先提供导线架，其中此导线架具有芯片座以及多个导脚配置在芯片座的外围。接下来，利用设置在芯片上的焊球将芯片贴附在芯片座以及外围的导脚上。随后，利用封胶材料包覆芯片、芯片座、以及导脚的一部分上，并填满芯片与芯片座的间的空间，因而完成芯片的封装，封装完成后的芯片可透过焊球与导脚而与外界组件电性连接。
然而，在芯片完成封装后，若封胶材料与芯片和导线架的密合度不佳时，则可能发生封胶材料脱落的情形，因而严重影响芯片的封装质量和最终成品的制程良率。
发明内容
因此本发明的目的之一在于提供一种半导体封装构造，其可增加封胶体对于芯片和承载器的密合度，提升封装质量。
本发明的另一目的在于提供一种半导体封装用的承载器构造，其结构可增加封胶体对于芯片和承载器的密合度，提升封装质量。
本发明的又一目的在于提供一种半导体封装构造，以减少刀具在裁切框体时的磨耗，增加刀具的使用寿命。
根据本发明的实施例，本发明的半导体封装构造至少包含有芯片承座、芯片、导脚、凹槽及封胶体。芯片设置于芯片承座上，导脚设置于芯片承座的外周围，并电性连接至芯片，其中导脚具有一上表面和一外侧面，外侧面相对远离于芯片。凹槽形成于导脚的上表面，并延伸至外侧面。封胶体包覆芯片承座、芯片、导脚及凹槽。
又，根据本发明的实施例，本发明的半导体封装用的承载器构造至少包含有框体、导脚及凹槽。导脚连接于框体，其中导脚具有一上表面，凹槽形成于导脚的上表面，并延伸至导脚与框体的连接处。
又，根据本发明的实施例，上述半导体封装用的承载器构造的框体具有若干个封装区域，用以在切除框体后形成若干个半导体封装构造。
因此，本发明的半导体封装构造通过在承载器的导脚的上表面形成凹槽，且凹槽延伸至导脚与框体的连接处。而当完成本发明的半导体封装构造时，凹槽是延伸至导脚外侧面，以增加封胶体对于芯片和承载器的密合度，因而提升封装质量和制程良率。且凹槽可减少刀具在裁切框体时的磨耗，以增加刀具的使用寿命。
附图说明
图1是依照本发明的第一实施例的半导体封装构造的侧视示意图。
图2是依照本发明的第一实施例的半导体封装构造的承载器的俯视示意图。
图3是依照本发明的第一实施例的半导体封装构造的承载器的局部立体图。
图4是依照本发明的第二实施例的半导体封装构造的单一导脚的剖面示意图。
图5是依照本发明的第三实施例的半导体封装构造的单一导脚的剖面示意图。
图6是依照本发明的第四实施例的半导体封装构造的单一导脚的剖面示意图。
图7是依照本发明的第三实施例的半导体封装构造的单一导脚的俯视示意图。
图8是依照本发明的第四实施例的半导体封装构造的俯视示意图。
图9是依照本发明的第五实施例的半导体封装构造的侧视示意图。
具体实施方式
请参照图1，其是依照本发明的第一实施例的半导体封装构造的侧视示意图。本实施例的半导体封装构造100包含有承载器110、芯片120及封胶体130。承载器110用以承载芯片120，封胶体130用以包覆住芯片120和承载器110，因而形成本实施例的半导体封装构造100。另外，本实施例的半导体封装构造100可例如为四边平坦无引脚(QFN)封装构造，但本发明的半导体封装构造并不限于此，本实施例的半导体封装构造100也可是其它具有外部引脚的封装构造。
请参照图2至图4，图2是依照本发明的第一实施例的半导体封装构造的承载器的俯视示意图，图3是依照本发明的第一实施例的半导体封装构造的承载器的局部立体图，图4是依照本发明的第一实施例的半导体封装构造的单一导脚的剖面示意图。本实施例的承载器110是由例如：银、金、铝、铜及其合金等高导电材质制成的导线架，其包含有若干个导脚111、至少一凹槽112、芯片承座113、支撑条114及框体115。此些导脚111分别连接于框体115(例如为矩形框体)，并设置于框体115的周围内侧，其中每一导脚111具有上表面111a、第一侧面111b及第二侧面111c，第一侧面111b及第二侧面111c分别相邻于上表面111a。凹槽112形成于每一导脚111的上表面111a，且凹槽112延伸至导脚111与框体115的连接处，并形成于第一侧面111b或第二侧面111c与上表面111a所形成的接角上，其中凹槽112是利用蚀刻、雷射蚀刻或冲压的方式来形成，可以是矩形、弧形或不规格形凹槽。芯片承座113设置于承载器110的中间位置，并通过支撑条114来连接框体115，以承载此芯片120。支撑条114分别设置于框体115四个角落，以稳固地连接芯片承座113。
如图1所示，当本实施进行封装时，首先，使芯片120黏贴于承载器110的芯片承座113上。接着，使芯片120与承载器110的导脚111形成电性连接。在本实施中，芯片120是通过若干条导线140来形成电性连接。接着，通过封胶体130来包覆芯片120和承载器110成一体，其中封胶体130至少包覆至导脚111的凹槽112处，并通过导脚111的凹槽112来增加封胶体130与芯片120和承载器110的密合度。然后，进行一切除步骤，以切除承载器110的框体115，因而形成本实施例的半导体封装构造100。此时，由于凹槽112是延伸至导脚111与框体115的连接处，故导脚111的凹槽112可进一步减少裁切刀具(未绘示)的受刀面积，进而减少刀具的磨耗。
值得注意的是，本实施例的半导体封装构造100的封胶体130可以完全包覆住凹槽112；或部分包覆住凹槽112，而外露出部分凹槽112。
如图1和图3所示，在完成本实施例的半导体封装构造100后，此时，由于承载器110的框体115已被切除，故本实施例的每一此些导脚111分别具有一外侧面111d，且导脚111的凹槽112是形成于导脚111的上表面111a，并延伸至此外侧面111b，因而本实施的封胶体130可通过导脚111的凹槽112来稳固地包覆住芯片120和承载器110，避免因封胶体130的密合度不佳而导致封胶体130脱落的情形，以提升封装质量和制程良率。
请参照图5，其是依照本发明的第二实施例的半导体封装构造的单一导脚的剖面示意图。与第一实施例相比，第二实施例的半导体封装构造100的每一导脚211具有二个凹槽212，其分别形成于导脚211的第一侧面211b和第二侧面211c与上表面211a所形成的二个接角上，并延伸至导脚211的外侧面211d。因而第二实施例的导脚211的凹槽212可进一步增加封胶体130的密合度，使本实施例的半导体封装构造100更加稳固。
请参照图6和图7，图6是依照本发明的第三实施例的半导体封装构造的单一导脚的剖面示意图，图7是依照本发明的第三实施例的半导体封装构造的单一导脚的俯视示意图。与第一实施例相比，第三实施例的每一此些导脚311的凹槽312是形成于导脚311的第一侧面311b或第二侧面311c与上表面311a所形成的二个接角上，并延伸至导脚311的外侧面311d，且凹槽312的深度深及导脚311的底面311e，以增加封胶体130的密合度。
请参照图8，其是依照本发明的第四实施例的半导体封装构造的俯视示意图。与第一实施例相比，第四实施例的承载器410具有若干个导脚411、若干个凹槽412、若干个芯片承座413、若干个支撑条414、框体415及若干个封装区域416。此些封装区域416通过框体415来形成，此时，导脚411分别设置于此些封装区域416的周围内侧，而凹槽412延伸至导脚411与框体415的连接处，芯片承座413分别设置于此些封装区域416的中间位置，并通过支撑条414来连接框体415。此时，此些封装区域416可承载若干个芯片120，并在包覆封胶体130和切除框体415后，即形成若干个半导体封装构造100。
请参照图9，其是依照本发明的第五实施例的半导体封装构造的侧视示意图。与第一实施例相比，第五实施例的芯片520是通过若干个焊球540来覆晶结合于承载器510的导脚511和芯片承座513，并电性连接于导脚511，而导脚511形成有凹槽512，以增加封胶体130的密合度。
由上述本发明的实施例可知，本发明的半导体封装构造通过在导脚的上表面形成凹槽，且凹槽延伸至导脚与框体的连接处。而当完成本发明的半导体封装构造时(切除承载器的框体后)，凹槽延伸至导脚的外侧面，以增加封胶体对于芯片和承载器的密合度，提升封装质量和制程良率。另外，凹槽可进一步减少刀具在裁切框体时的磨耗。

Claims (16)

1.一种半导体封装构造，其包括一芯片承座；至少一芯片，设置于该芯片承座上；若干个导脚，设置于该芯片承座的外周围，并电性连接至该芯片，其中每一该些导脚具有一上表面和一外侧面，该外侧面相对远离于该芯片；以及一封胶体，包覆该芯片承座、该芯片和该些导脚；其特征在于：至少一凹槽，形成于每一该些导脚的该上表面上，并延伸至该外侧面，该封胶体包覆该凹槽。
2.如权利要求1所述的半导体封装构造，其特征在于：部分该凹槽外露于该封胶体。
3.如权利要求1所述的半导体封装构造，其特征在于：该些导脚是通过若干条导线来电性连接于该芯片。
4.如权利要求1所述的半导体封装构造，其特征在于：该芯片是通过若干个焊球来覆晶接合于该些导脚，以形成电性连接。
5.如权利要求1所述的半导体封装构造，其特征在于：每一该些导脚更具有一第一侧面、一第二侧面和一底面，其中该第一侧面是相对于该第二侧面，且该第一侧面和该第二侧面是分别相邻于该上表面及该外侧面，而该凹槽是形成于该第一侧面与该上表面所形成的一接角上。
6.如权利要求5所述的半导体封装构造，其特征在于：每一该些导脚的该第二侧面与该上表面所形成的另一接角上形成有另一凹槽。
7.如权利要求5所述的半导体封装构造，其特征在于：该凹槽的深度深及该导脚的底面。
8.如权利要求1所述的半导体封装构造，其特征在于：该凹槽为矩形凹槽、弧形凹槽、不规格形凹槽的一种。
9.如权利要求1所述的半导体封装构造，其特征在于：该凹槽是以蚀刻、雷射蚀刻、冲压的其中一种方式来形成。
10.一种半导体封装用的承载器构造，其包括一框体以及连接于该框体的若干导脚，其中每一该些导脚具有一上表面及一外侧面；其特征在于：至少一凹槽，形成于每一该些导脚的该上表面上，并延伸至该导脚与该框体的连接处。
11.如权利要求10所述的半导体封装用的承载器构造，其特征在于：至少更包含：一芯片承座，其中该些导脚围绕该芯片承座。
12.如权利要求10所述的半导体封装用的承载器构造，其特征在于：每一该些导脚更具有一第一侧面、一第二侧面和一底面，其中该第一侧面相对于该第二侧面，且该第一侧面和该第二侧面分别相邻于该上表面及该外侧面，而该凹槽是形成于该第一侧面或第二侧面与该上表面所形成的一接角上。
13.如权利要求12所述的半导体封装用的承载器构造，其特征在于：每一该些导脚的该第二侧面与该上表面所形成的另一接角上形成有另一凹槽。
14.如权利要求12所述的半导体封装用的承载器构造，其特征在于：该凹槽的深度深及该导脚的底面。
15.如权利要求10所述的半导体封装用的承载器构造，其特征在于：该凹槽为矩形凹槽、弧形凹槽、不规格形凹槽的一种。
16.如权利要求10所述的半导体封装用的承载器构造，其特征在于：该凹槽是以蚀刻、雷射蚀刻、冲压的其中一种方式来形成。
CNA2007101672805A 2007-10-31 2007-10-31 半导体封装构造 Pending CN101150108A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNA2007101672805A CN101150108A (zh) 2007-10-31 2007-10-31 半导体封装构造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNA2007101672805A CN101150108A (zh) 2007-10-31 2007-10-31 半导体封装构造

Publications (1)

Publication Number Publication Date
CN101150108A true CN101150108A (zh) 2008-03-26

Family

ID=39250541

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2007101672805A Pending CN101150108A (zh) 2007-10-31 2007-10-31 半导体封装构造

Country Status (1)

Country Link
CN (1) CN101150108A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101335221B (zh) * 2008-07-30 2010-06-02 江苏长电科技股份有限公司 凹槽金属板式新型半导体封装方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101335221B (zh) * 2008-07-30 2010-06-02 江苏长电科技股份有限公司 凹槽金属板式新型半导体封装方法

Similar Documents

Publication Publication Date Title
US7786557B2 (en) QFN Semiconductor package
US7816769B2 (en) Stackable packages for three-dimensional packaging of semiconductor dice
US6927483B1 (en) Semiconductor package exhibiting efficient lead placement
US7112875B1 (en) Secure digital memory card using land grid array structure
US7728414B2 (en) Lead frame and resin-encapsulated semiconductor device
TWI474455B (zh) 先進四方扁平無引腳封裝結構
US6967125B2 (en) Quad flat no lead (QFN) grid array package, method of making and memory module and computer system including same
US7514293B2 (en) Method of manufacturing a semiconductor device
US20110049685A1 (en) Semiconductor device with electromagnetic interference shielding
JP2005191240A (ja) 半導体装置及びその製造方法
US20060049523A1 (en) Wire-bonding method for connecting wire-bond pads and chip and the structure formed thereby
US20110042794A1 (en) Qfn semiconductor package and circuit board structure adapted for the same
US20040238923A1 (en) Surface-mount-enhanced lead frame and method for fabricating semiconductor package with the same
US8835225B2 (en) Method for fabricating quad flat non-leaded semiconductor package
US6692991B2 (en) Resin-encapsulated semiconductor device and method for manufacturing the same
US20080185698A1 (en) Semiconductor package structure and carrier structure
CN101150108A (zh) 半导体封装构造
JP3222955U (ja) 予備成形リードフレーム
JP5499437B2 (ja) モールドパッケージ
CN113140469A (zh) 封装结构及其成型方法
US20040262773A1 (en) Chip-stacked package
JP4278568B2 (ja) 半導体装置
CN220873575U (zh) 导线架以及封装结构
CN218996696U (zh) 提高芯片引脚密度的封装结构
CN101807561B (zh) 电子元件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication