CN101140878A - Polycrystalline silicon medium flat method - Google Patents

Abstract

The invention discloses a method for interpoly dielectric planarization used for the dielectric planarization in the circuit manufacturing process, which comprises steps as follows: first, growing 200nm oxide layer on the silicon chip with slot; second, depositing thin polycrystalline silicon layer of 30 to 50nm in grain diameter to fill in the slot on the said oxide layer; third, depositing thick polycrystalline silicon layer of 40 to 50 Mu m in thickness and 0.9 to 2.0 Mu m in grain diameter on the said thin polycrystalline silicon layer; fourth, mechanical thinning the silicon chip deposited with thick polycrystalline silicon layer to remain its thickness away from the said oxide layer of 0.8 to 1.5 Mu m; fifth, chemico-mechanical polishing the said silicon chip with the remaining residual polycrystalline silicon layer to the oxide layer; sixth, drifting the left oxide layer to make the slot face and the silicon surface plainness and uniformed. The method provided in the invention can efficiently solve various problems of sagsandcrests on the surface of silicon chip with slot filled with polycrystalline silicon, meeting the requirement of more than 90% of finished products in technical process.

Description

The method of polycrystalline silicon medium flat

(1) technical field

The present invention relates to the medium flat technology in the integrated circuit technology manufacturing, particularly relate to a kind of method of polycrystalline silicon medium flat technology.

(2) background technology

Along with after the size of integrated circuit (IC)-components enters micron and sub-micrometer range, in order to improve the integrated level of integrated circuit, will adopt multilayer wiring, the medium flat technology is the most key factor that guarantees the multilayer wiring quality in the integrated circuit fabrication process.At present, planarization mainly contains five kinds: heat flow method (Thermal Flow), spin-on glasses method (Spin On Glass), eat-back method (Etch Back), electronics circulating type resonance method (Electron Cyclotron Resonance), chemical mechanical polishing method (Chemical Mechanical Polishing).The smooth technology of chemico-mechanical polishing is the most frequently used method, and chemico-mechanical polishing is different with polishing pad according to polishing fluid, can polished silicon and polysilicon, silicon nitride, silicon dioxide and wiring in various metal levels.Its common method is: adopt the thin polysilicon of low pressure chemical vapor deposition (LPCVD) technology deposit to fill deep trouth earlier, after the deep trouth filling is expired, adopt chemico-mechanical polishing (CMP) method to come the platform polysilicon again, make silicon chip surface reach smooth.Its shortcoming is: behind the polysilicon filling slot, groove fills up the back silicon chip surface and serious " concavo-convex " injustice occurs, when adopting chemico-mechanical polishing, " recessed " of silicon chip surface and " protruding " become more obvious in the zone of " recessed " and " protruding " under chemical corrosion, mechanism, cause " concavo-convex " uneven phenomenon of silicon chip surface still to exist, as shown in Figure 1.Step thicknesses between recessed and protruding generally reaches more than several microns, and silicon chip surface is " wave " figure.Irregular like this silicon chip surface directly causes the rate of finished products of back technological requirement lower, generally can only reach 75%.

(3) summary of the invention

The method that the purpose of this invention is to provide a kind of polycrystalline silicon medium flat technology, the silicon chip that makes band " V " type groove, " U " type groove, " square " type groove is behind the polysilicon filling slot, its silicon chip plane is more smooth, improves the rate of finished products of silicon chip planarization, satisfies the requirement of back technology.

For achieving the above object, the method for polycrystalline silicon medium flat of the present invention may further comprise the steps:

1. having the thick SiO of growth 200nm on the silicon chip of groove ₂Oxide layer;

2. the thin polysilicon layer of deposit particle diameter 30-50nm on the silicon chip of described oxide layer of having grown is to fill up groove;

3. deposition thickness is the thick polysilicon layer of 40-50 μ m, particle diameter 0.9-2.0 μ m on the described silicon chip that fills up thin polysilicon;

To described deposit the silicon chip behind the thick polysilicon layer carry out mechanical reduction, polysilicon layer thickness is kept apart from described oxide layer 0.8-1.5 μ m;

5. the described silicon chip that remains with the remaining polysilicon layer is carried out chemico-mechanical polishing (CMP), be polished to the oxide layer place;

6. float the residue oxide layer, make groove face and silicon face smooth consistent.

Beneficial effect:

The present invention has following characteristics owing to taked above technical scheme:

1. the present invention adopts the method that accurate attenuate and two kinds of technologies of chemico-mechanical polishing combine, behind accurate attenuate, no longer there is the uneven phenomenon in surface " concavo-convex " in polysilicon surface, " concavo-convex " uneven problem appears in silicon chip surface after having solved various flute profiles filling polysilicons effectively, again by chemico-mechanical polishing, make the polysilicon of silicon chip surface further smooth, evenness reaches below the 1.0 μ m.

2. adopt the method for general chemico-mechanical polishing (CMP), the rate of finished products that the back technological requirement is satisfied in the planarization of polysilicon is 75%, and after adopting method of the present invention, the rate of finished products that the back technological requirement is satisfied in the planarization of polysilicon reaches more than 90%.Therefore improved the smooth rate of finished products of polysilicon.Test result contrast table after the method processing of table 1 method of the present invention and conventional CMP sees Table 1.

Test result contrast table after the method processing of table 1 method of the present invention and conventional CMP

(the tester of data in the table: multifunctional tester ADE9500)

Title		Adopt the method for conventional CMP	Adopt method of the present invention
				The evenness of silicon chip	FPD	8.82μm	-7.09μm
TIR	0.98μm	0.54μm
			The silicon chip total thickness variations		TTV	9.47μm	1.20μm
Satisfy the rate of finished products of back technological requirement		75％		90％

In the table 1, the English full name of FPD is Focal Plane Deviation, general claim " focal plane side-play amount ", be meant silicon chip surface o'clock to the distance of a specific plane.Focal plane side-play amount (FPD) can be on the occasion of (this point is on given plane) on every of silicon chip, also can be negative value (this point is under given plane).It should be noted that it is on the smooth basis that FPD is based upon the silicon chip back side.The English full name of TIR is Total Indicator Reading, is meant the difference of minimum and maximum focal plane side-play amount.The English full name of TTV is Total Thickness Variation, is meant the difference between silicon chip maximum ga(u)ge and the minimum thickness.

(4) description of drawings

Fig. 1 is the generalized section after the general chemico-mechanical polishing (CMP);

Fig. 2 is the generalized section after deposited oxide layer on the silicon chip that has groove (" square " type groove);

Fig. 3 is the generalized section after filling thin polysilicon on the silicon chip of Fig. 2;

Fig. 4 is the generalized section behind the thick polysilicon of deposit on the silicon chip of Fig. 3;

Fig. 5 carries out generalized section behind the attenuate to the polysilicon layer on Fig. 4 silicon chip;

Fig. 6 is the generalized section after the polysilicon on Fig. 5 silicon chip is polished.

Fig. 7 is the generalized section after the oxide layer of floating on Fig. 6 silicon chip.

(5) embodiment

Below in conjunction with specific embodiment and accompanying drawing, the present invention is described in further detail.Here, the silicon chip with " square " type groove is an example.

The method of polysilicon planarization of the present invention comprises following processing step:

1. with the conventional method for oxidation layer of oxide layer 2 of on the silicon chip 1 that has groove, growing, adopt U.S. THERMCO diffusion furnace TMX9000 equipment, make all deposit SiO of silicon chip surface and groove inner surface 950 ℃ of following oxidations 2 hours 10 minutes ₂Oxide layer 2, oxidated layer thickness are 200nm.As shown in Figure 2.

To described deposit the silicon chip of oxide layer, the thin polysilicon 3 of deposit, adopt U.S. THERMCO diffusion furnace TMX9000 equipment, at 600 ℃ of following deposit 3-8 hours, deposition speed 50-70 dust/minute, deposition thickness is 1-5 μ m, makes thin polysilicon 3 fill up groove, and the particle size range of thin polysilicon is 30-50nm.As shown in Figure 3.

3. the described silicon chip that has filled up thin polysilicon is carried out the thick polysilicon 4 of deposit, adopt Russian epitaxial furnace MT121, at 1100 ℃ of following deposit 20-40 minutes, deposition speed 1-2 μ m/ minute, deposition thickness 40-50 μ m.The particle size range of thick polysilicon is 0.9-2.0 μ m.As shown in Figure 4.

To described deposit the silicon chip of thick polysilicon carry out mechanical reduction, adopt the Japanese Okamoto VG202MKII of company stripping apparatus, attenuate polysilicon thickness keeps apart from oxide layer 0.8-1.5 μ m polysilicon thickness.Adopt infrared test instrument QS-300 to measure.As shown in Figure 5.

5. there is the silicon chip of polysilicon to carry out chemico-mechanical polishing to described also remaining, adopts the AVANTI472 polishing machine of U.S. Speedfam IPEC company, be polished to described oxide layer 2 places, as shown in Figure 6.

6. float residue oxide layer 2 on the described silicon chip after having polished with hydrofluoric acid, make groove face and silicon face smooth consistent, as shown in Figure 7.

Above-mentioned described processing technology and parameter thereof, chemical solution, process equipment etc., except that having described, remaining is the common technology known to those of ordinary skills, is no longer described in detail.

Claims (1)

1. the flattening method of a polycrystalline silicon medium, it may further comprise the steps:

(1) having the thick SiO of growth 200nm on the silicon chip of groove ₂Oxide layer;

(2) the thin polysilicon layer of deposit particle diameter 30-50nm on the silicon chip of described oxide layer of having grown is to fill up groove;

(3) deposition thickness is the thick polysilicon layer of 40-50 μ m, particle diameter 0.9-2.0 μ m on the described silicon chip that fills up thin polysilicon;

(4) to described deposit the silicon chip behind the thick polysilicon layer carry out mechanical reduction, polysilicon layer thickness is kept apart from described oxide layer 0.8-1.5 μ m;

(5) the described silicon chip that remains with the remaining polysilicon layer is carried out chemico-mechanical polishing (CMP), be polished to described oxide layer place;

(6) float the residue oxide layer, make groove face and silicon face smooth consistent.

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