CN101136326A - Fabricating method for semiconductor device - Google Patents
Fabricating method for semiconductor device Download PDFInfo
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- CN101136326A CN101136326A CNA2006100306277A CN200610030627A CN101136326A CN 101136326 A CN101136326 A CN 101136326A CN A2006100306277 A CNA2006100306277 A CN A2006100306277A CN 200610030627 A CN200610030627 A CN 200610030627A CN 101136326 A CN101136326 A CN 101136326A
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Abstract
This invention discloses a manufacturing method for semiconductor apparatuses including: forming a dielectric layer on the substrate of the semiconductor, forming a polysilicon layer on the dielectric layer, forming and patternizing a hard mask layer on the polysilicon layer, etching the polysilicon layer to the surface of the dielectric layer and forming a grid, forming a medium layer on the substrate with the grid to cover side wall of the grid, the dielectric layer and the surface of the hard mask layer, eliminating the medium layer on the surfaces of the dielectric layer and the hard mask layer and eliminating the hard mask layer and the medium layer on the side of the grid with phosphoric acid to form a side wall protection layer on the side wall of the grid for isolating erosion liquid and grid.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of formation method of grid electrode of semiconductor.
Background technology
Develop rapidly along with semiconductor fabrication, semiconductor device is in order to reach arithmetic speed faster, bigger memory data output and more function, wafer develops towards higher component density, high integration direction, and for example the grid of CMOS becomes more and more thinner semiconductor device and length becomes shorter.After manufacturing process entered the 65nm process node, the minimum feature size of grid reached below the 65nm, even reached 40nm.
Polysilicon is a preferred material of making grid, and it has special is the hot and higher accurate surname of figure that is etched into.In the mistake that forms grid becomes, usually need be at gate polysilicon layer surface coverage hard mask layer (hard mask).Application number is the etching technics that 200410089397.2 Chinese patent application discloses a kind of may command grid structural length.This method adds hard mask layer under the photoresist of patterning, earlier with the design transfer of patterning photoresist to hard mask layer, and the patterning photoresist removed, be that mask carries out etching with the hard mask of this patterning more at last.
Fig. 1 to Fig. 3 is the generalized section of the existing grid forming process of explanation.As shown in Figure 1, on Semiconductor substrate 100, form one deck gate oxidation silicon 110, deposit spathic silicon layer 120 on grid oxic horizon 110, utilize deposition hard mask layer 130 on the chemical vapor deposition technology polysilicon layers 120 such as (CVD) then, the material of this hard mask layer 130 is silicon nitride (SIN) or silicon oxynitride (SION), is coated with photoresist subsequently and photoresist is carried out patterning.
As shown in Figure 2, the photoresist figure 140 after utilizing etching technics with patterning is transferred on the hard mask layer 130, forms the hard mask 180 of patterning.Described patterning photoresist figure 140 is removed, and the hard mask 180 with patterning is that mask etching polysilicon layer 120 forms grid 150 again.
Because the etching selection ratio of 180 pairs of polysilicon layers 120 of hard mask of patterning is very high, therefore can avoid photoresist because of patterning by the problem of overetch.Yet the material of above-mentioned hard mask 130 is silicon nitride (SIN) or silicon oxynitride (SION), needs to remove with the method for wet etching, and employed corrosive liquid is phosphoric acid (H
3PO
4).Because the material of hard mask 130 is dense, therefore the time of corrosion must could thoroughly remove hard mask 130 by long enough.As everyone knows, threshold voltage and drive current characteristic that the grid of NMOS in the cmos device and PMOS is mixed in advance and can improve device, thus improve device performance.For nmos device, preferential usually employing n type impurity for example phosphorus mixes to grid.With this understanding, when utilizing phosphoric acid to remove hard mask, phosphoric acid can corrode the polysilicon gate part of Doping Phosphorus impurity simultaneously, cause polysilicon gate 150 phenomenon of bottleneck (necking) 160 as shown in Figure 3 to occur, especially feature sizes of grids below the 65nm and phosphoric acid remove under the long situation of time of hard mask, bottleneck is particularly serious.
Summary of the invention
The object of the present invention is to provide a kind of formation method of grating of semiconductor element, can avoid the generation of bottleneck (necking) phenomenon of grid.
For achieving the above object, the manufacture method of a kind of semiconductor device provided by the invention comprises:
On Semiconductor substrate, form dielectric layer;
On described dielectric layer, form polysilicon layer;
On described polysilicon layer, form hard mask layer and the described hard mask layer of patterning;
The described polysilicon layer of etching to described dielectric layer surface forms grid;
Form side wall protective layer at described gate lateral wall;
Remove described hard mask layer.
The step of described formation side wall protective layer comprises:
Form dielectric layer having on the substrate of described grid; Described dielectric layer covers described gate lateral wall, dielectric layer and hard mask layer surface;
Removal is positioned at the described dielectric layer on described dielectric layer and hard mask layer surface.
Described dielectric layer is the mixture of silicon nitride or silicon oxynitride or silicon nitride and silicon oxynitride.Described hard mask layer is the mixture of silicon nitride or silicon oxynitride or silicon nitride and silicon oxynitride.The minimum thickness of described side wall protective layer is equal to or slightly greater than the thickness of described hard mask layer.The thickness of the described dielectric layer that is positioned at dielectric layer surface is less than the thickness of the dielectric layer that is positioned at gate lateral wall.Described hard mask layer utilizes phosphoric acid to remove.The thickness of the dielectric layer of described dielectric layer surface is identical with the thickness of the dielectric layer on hard mask layer surface.
The present invention has the manufacture method of the another kind of semiconductor device of identical or relevant art feature, comprising:
On Semiconductor substrate, form dielectric layer;
On described dielectric layer, form polysilicon layer;
On described polysilicon layer, form hard mask layer and the described hard mask layer of patterning;
The described polysilicon layer of etching to described dielectric layer surface forms grid;
Form dielectric layer having on the substrate of described grid; Described dielectric layer covers described gate lateral wall, dielectric layer and hard mask layer surface;
Removal is positioned at the described dielectric layer on described dielectric layer and hard mask layer surface;
Utilize phosphoric acid to remove described hard mask layer; And
The dielectric layer on gate lateral wall surface.
Described dielectric layer is the mixture of silicon nitride or silicon oxynitride or silicon nitride and silicon oxynitride.Described hard mask layer is the mixture of silicon nitride or silicon oxynitride or silicon nitride and silicon oxynitride.The minimum thickness of described side wall protective layer is equal to or slightly greater than the thickness of described hard mask layer.The thickness of the described dielectric layer that is positioned at dielectric layer surface is less than the minimum thickness of the dielectric layer that is positioned at gate lateral wall.The thickness of the dielectric layer of described dielectric layer surface is identical with the thickness of the dielectric layer on hard mask layer surface.
Compared with prior art, the present invention has the following advantages:
Method of the present invention is after utilizing hard mask etching polysilicon layer formation grid; wet method is removed before the hard mask; sidewall at described grid forms side wall protective layer; this protective layer has played the effect of isolating corrosive liquid and grid; make when hard mask being carried out wet etching with phosphoric acid; phosphoric acid can not touch the sidewall surfaces of grid, thereby has avoided the generation of bottleneck.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing in proportion, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, amplified the thickness in layer and zone.
Fig. 1 to Fig. 3 is the generalized section of the existing grid forming process of explanation;
Fig. 4 to Fig. 8 is the generalized section according to the grid formation method of the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
The formation method of grating of semiconductor element provided by the invention is applicable to the manufacturing of characteristic dimension of line width at 65nm and following grating of semiconductor element.Described semiconductor device is not only MOS transistor, can also be PMOS transistor and nmos pass transistor among the CMOS (complementary mos device).For the present invention is described better, be example in the following embodiments with the nmos device.
The manufacturing process of cmos device enters after the 65nm process node, and the electric property consistency of the NMOS of cmos device inside and PMOS and the consistency of performance between the device become extremely important.Pre-doping has been widely used in reducing the difference between NMOS and PMOS self electrology characteristic.The grid of NMOS in the cmos device and PMOS mixed has in advance become the threshold voltage of trim and drive current characteristic, obtains the important means of desirable device performance.For NMOS and PMOS device, preferential usually employing n type impurity for example phosphorus mixes to grid.But the polysilicon that contains phosphorus impurities is easily to the phosphoric acid sensitivity, and easily by phosphoric acid corrosion, and the degree of the high more corrosion of impurity concentration is serious more.When utilizing phosphoric acid to remove hard mask, phosphoric acid can corrode the polysilicon gate part of Doping Phosphorus impurity simultaneously, bottleneck occurs.Especially for the grid of NMOS impurity, compare PMOS, responsive more to phosphoric acid, when phosphoric acid is removed hard mask, very easily the high part of top portions of gates impurity concentration is caused corrosion, bottleneck occurs, the profile of grid is changed, the top portions of gates live width narrows down, and influences the formation of contact hole.These all have a strong impact on the stability of device.
Method, semi-conductor device manufacturing method etch polysilicon layer of the present invention forms after the grid; wet method is removed before the hard mask; sidewall at described grid forms side wall protective layer; this protective layer is isolated corrosive liquid and grid; make when hard mask carried out wet etching; corrosive liquid (phosphoric acid) can not touch the sidewall surfaces of grid, thereby has avoided the generation of bottleneck.
Fig. 4 to Fig. 8 is the generalized section according to the grid formation method of the embodiment of the invention.At first as shown in Figure 4, at first on Semiconductor substrate 100, form dielectric layer 110.Dielectric layer 110 can be silica (SiO2) or silicon oxynitride (SiNO).Substrate 100 can comprise semiconductor element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) also can be silicon-on-insulators (SO1).The material that perhaps can also comprise other, for example indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide.Though in these several examples of having described the material that can form substrate 100, any material that can be used as Semiconductor substrate all falls into the spirit and scope of the present invention.
Gate features size of the present invention is below 65nm, and dielectric layer 110 is as gate dielectric layer, and its material is preferably high-k (high K) material, can reduce the leakage current of grid.Can be used as the material that forms high-K gate dielectric layer and comprise hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc.Particularly preferably be hafnium oxide, zirconia and aluminium oxide.Though in this a few examples of having described the material that can be used for forming dielectric layer 11O, this layer can be formed by other material that reduces grid leakage current.The growing method of dielectric layer 110 can be any conventional vacuum coating technology, such as ald (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) technology, be preferably atom layer deposition process.In such technology, can form smooth atom interface between substrate 100 and the dielectric layer l10, can form the gate dielectric layer of ideal thickness.In the inventive method, the live width of grid is below 65nm, and the preferred thickness of dielectric layer ll0 is at 10-20
Between.
Then, on dielectric layer 11O, form polysilicon layer 120.The material of polysilicon layer l20 is the polysilicon of polysilicon or doping metals impurity, and metal impurities comprise a kind of metal (for example titanium, tantalum, tungsten etc.) and metal silicide at least.The method that forms polysilicon layer l20 comprises ald (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD) technology.In order to obtain NMOS and the PMOS consistency of electric property (for example Fujian threshold voltage and drive current) preferably, impurity particle in polycrystalline silicon material usually, the present invention is with n type impurity, and for example phosphorus is doped to example.
Utilize deposition hard mask layer 130 on the chemical vapor deposition technology polysilicon layers 120 such as (CVD) subsequently, the material of this hard mask layer l30 is silicon nitride (SIN) or silicon oxynitride (SION), or the mixture of silicon nitride and helium silica.Be coated with photoresist layer subsequently, also need forming one deck anti-reflecting layer (not shown) so that the photoresist figure after developing is more clear in hard mask surface before the coating.By technologies such as exposure, developments photoresist is carried out patterning, obtain having the photoresist figure 140 of the following width of 65nm, it has defined the position and the width of grid.
In ensuing processing step, the photoresist figure 140 after utilizing plasma etching or reactive ion etching (RlE) technology with patterning in reative cell is transferred on the hard mask layer l30, forms the hard mask l80 of patterning.Described patterning photoresist figure 140 is removed, can adopt the method for wet-cleaned or plasma ashing (ashing) to remove photoresist figure 140.Hard mask 180 with patterning is a mask again, utilize plasma etching or RIE etch polysilicon layer l20, the etching selection ratio of 180 couples of polysilicon layer l20 of hard mask of patterning is very high, and hard mask 180 is dense, therefore can obtain the good grid of appearance profile 150, as shown in Figure 5.
Next, as shown in Figure 6, on substrate 100, in reative cell, under the suitable pressure and temperature, utilize CVD technology deposit protective dielectric layer with grid 150; The sidewall of this layer dielectric layer cover gate l50, gate dielectric layer 110 and hard mask 180 surfaces.Here this layer dielectric layer with cover gate 150 sidewalls is called side wall protective layer, i.e. 170 among Fig. 6.The material of this dielectric layer is preferably the mixture of silicon nitride or silicon oxynitride or silicon nitride and silicon oxynitride, and is identical with the material of hard mask, so that when follow-up phosphoric acid was removed hard mask 180, the side wall protective layer 170 of grid 150 also can be removed.The minimum thickness of side wall protective layer 170 will be equal to or slightly greater than the thickness of hard mask layer 180, in order to avoid side wall protective layer 170 is fallen by phosphoric acid corrosion prior to hard mask layer 180.Because the protective layer 170 at the gate lateral wall surface deposition has certain gradient; when etching away the dielectric layer 171 on gate dielectric layer 110 surfaces; side wall protective layer 170 also can be etched away; therefore the thickness that is positioned at the dielectric layer 171 on gate dielectric layer 110 surfaces is less than the minimum thickness of the side wall protective layer 170 of grid 150; like this; when etching away the dielectric layer on gate dielectric layer 110 surfaces, side wall protective layer 170 can not be etched thinly excessively.In addition, the thickness of the dielectric layer 171 on gate dielectric layer 110 surfaces is identical with the thickness of the dielectric layer 172 on hard mask layer 180 surfaces, and described dielectric layer 171 and 172 can be etched away simultaneously.
Next the dielectric layer 172 on the dielectric layer 171 on etching gate dielectric layer 110 surfaces and hard mask layer 180 surfaces.As shown in Figure 7, at this moment expose on the surface of hard mask layer 180, utilizes phosphoric acid to remove hard mask layer 180.The side wall protective layer 170 of grid 150 plays a part isolated gate sidewall and phosphoric acid, makes phosphoric acid can not corrode grid 150, has avoided the generation of bottleneck.
At last, as shown in Figure 8, hard mask 180 has been removed, owing to formed protective layer at gate lateral wall in the inventive method, corrosive liquid does not touch gate lateral wall, has guaranteed that well the appearance profile of grid is not destroyed.
The present invention forms the process of gate lateral wall protective layer 170 and forms side wall (offset spacer) technology basic identical; the material of side wall protective layer 170 and the material of side wall are also basic identical; therefore; though side wall protective layer perhaps also can a residual part when hard mask was corroded, this does not influence the formation of subsequent gate side wall.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (14)
1. the manufacture method of a semiconductor device comprises:
On Semiconductor substrate, form dielectric layer;
On described dielectric layer, form polysilicon layer;
On described polysilicon layer, form hard mask layer and the described hard mask layer of patterning;
The described polysilicon layer of etching to described dielectric layer surface forms grid;
Form side wall protective layer at described gate lateral wall;
Remove described hard mask layer.
2. the method for claim 1, it is characterized in that: the step of described formation side wall protective layer comprises:
Form dielectric layer having on the substrate of described grid; Described dielectric layer covers described gate lateral wall, dielectric layer and hard mask layer surface;
Removal is positioned at the described dielectric layer on described dielectric layer and hard mask layer surface.
3. method as claimed in claim 2 is characterized in that: described dielectric layer is the mixture of silicon nitride or silicon oxynitride or silicon nitride and helium silica.
4. method as claimed in claim 2 is characterized in that: described hard mask layer is the mixture of silicon nitride or silicon oxynitride or silicon nitride and silicon oxynitride.
5. method as claimed in claim 2 is characterized in that: the minimum thickness of described side wall protective layer is equal to or slightly greater than the thickness of described hard mask layer.
6. method as claimed in claim 2 is characterized in that: the thickness of the described dielectric layer that is positioned at dielectric layer surface is less than the thickness of the dielectric layer that is positioned at gate lateral wall.
7. method as claimed in claim 1 or 2 is characterized in that: described hard mask layer utilizes phosphoric acid to remove.
8. method as claimed in claim 2 is characterized in that: the thickness of the dielectric layer of described dielectric layer surface is identical with the thickness of the dielectric layer on hard mask layer surface.
9. the manufacture method of a semiconductor device comprises:
On Semiconductor substrate, form dielectric layer;
On described dielectric layer, form polysilicon layer;
On described polysilicon layer, form hard mask layer and the described hard mask layer of patterning;
The described polysilicon layer of etching to described dielectric layer surface forms grid;
Form dielectric layer having on the substrate of described grid; Described dielectric layer covers described gate lateral wall, dielectric layer and hard mask layer surface;
Removal is positioned at the described dielectric layer on described dielectric layer and hard mask layer surface;
Utilize phosphoric acid to remove described hard mask layer; And
The dielectric layer on gate lateral wall surface.
10. method as claimed in claim 9 is characterized in that: described dielectric layer is the mixture of silicon nitride or silicon oxynitride or silicon nitride and silicon oxynitride.
11. method as claimed in claim 9 is characterized in that: described hard mask layer is the mixture of silicon nitride or silicon oxynitride or silicon nitride and silicon oxynitride.
12. method as claimed in claim 9 is characterized in that: the minimum thickness of described side wall protective layer is equal to or slightly greater than the thickness of described hard mask layer.
13. method as claimed in claim 9 is characterized in that: the thickness of the described dielectric layer that is positioned at dielectric layer surface is less than the minimum thickness of the dielectric layer that is positioned at gate lateral wall.
14. method as claimed in claim 9 is characterized in that: the thickness of the dielectric layer of described dielectric layer surface is identical with the thickness of the dielectric layer on hard mask layer surface.
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| CNB2006100306277A CN100483633C (en) | 2006-08-31 | 2006-08-31 | Fabricating method for semiconductor device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102214563A (en) * | 2010-04-09 | 2011-10-12 | 中国科学院微电子研究所 | Method for preparing and forming metal gate/high-K gate dielectric laminated structure |
| CN103794504A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Flash memory and manufacturing method thereof |
| WO2015042769A1 (en) * | 2013-09-24 | 2015-04-02 | 李利锋 | Method for forming semiconductor assembly |
| CN105990111B (en) * | 2015-01-28 | 2019-01-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and preparation method thereof |
-
2006
- 2006-08-31 CN CNB2006100306277A patent/CN100483633C/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102214563A (en) * | 2010-04-09 | 2011-10-12 | 中国科学院微电子研究所 | Method for preparing and forming metal gate/high-K gate dielectric laminated structure |
| CN102214563B (en) * | 2010-04-09 | 2013-03-13 | 中国科学院微电子研究所 | Method for preparing and forming metal gate/high-K gate dielectric laminated structure |
| CN103794504A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Flash memory and manufacturing method thereof |
| WO2015042769A1 (en) * | 2013-09-24 | 2015-04-02 | 李利锋 | Method for forming semiconductor assembly |
| CN105990111B (en) * | 2015-01-28 | 2019-01-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and preparation method thereof |
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| Publication number | Publication date |
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| CN100483633C (en) | 2009-04-29 |
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Effective date of registration: 20111115 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |