CN100468636C - Forming method of metal oxide semiconductor device grids structure - Google Patents
Forming method of metal oxide semiconductor device grids structure Download PDFInfo
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- CN100468636C CN100468636C CNB2006100307937A CN200610030793A CN100468636C CN 100468636 C CN100468636 C CN 100468636C CN B2006100307937 A CNB2006100307937 A CN B2006100307937A CN 200610030793 A CN200610030793 A CN 200610030793A CN 100468636 C CN100468636 C CN 100468636C
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Abstract
The invention provides a grid structure forming method for semiconductor device of metal oxide, which comprises forming dielectric layer on the semiconductor underlay; forming polycrystalline silicon layer on the said dielectric layer; forming stack layer and positioning the grid location on the said polycrystalline silicon layer; etching the said polycrystalline silicon layer for the mask layer by the said stack layer to form grid; The invention can produce grid with good shape without forming the hard mask layer, which is especially applicable to grid making with characteristic dimension of line width under 65nm.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of formation method of metal oxide semiconductor device grids structure.
Background technology
Polysilicon is a preferred material of making grid, and it has special thermal endurance and the higher accurate surname of figure that is etched into.The manufacture method of grid at first needs to form one deck gate oxidation silicon on Semiconductor substrate, deposit spathic silicon layer on grid oxic horizon then, coating subsequently has mobile bottom anti-reflective layer (BARC) and photoresist, and the etch polysilicon layer forms grid behind the patterning photoresist layer.Fig. 1 to Fig. 4 is the generalized section of the existing grid production method of explanation.As shown in Figure 1, growth one deck grid oxic horizon 110 on substrate 100, deposit spathic silicon layer 120 on grid oxic horizon 110 carries out etching to polysilicon layer then so that form grid.In this process, at first need to form BARC layer 130, and then the coating photoresist is so that the figure after developing is more clear on the polysilicon layer surface.After photoresist carried out patterning, be that the mask etching polysilicon layer forms grid with photoresist figure 140.
Develop rapidly along with semiconductor fabrication, semiconductor device is in order to reach arithmetic speed faster, bigger memory data output and more function, wafer develops towards higher component density, high integration direction, and the grid of semiconductor device becomes more and more thinner and length becomes shorter.After manufacturing process entered the 65nm process node, the minimum feature size of grid reached below the 65nm, even reached 40nm.With this understanding, the width of photoresist figure 140 will adapt with grid width, and for the requirement of etching technics need have high narrow shape characteristic.Yet as shown in Figure 2, high and narrow photoresist figure 140 is prone to the phenomenon that the physics pattern collapses in long-time reduction and etching process.If avoid collapsing phenomenon and the height that reduces photoresist figure 140; in the subsequent etching process, because the photoresist quantity not sufficient, photoresist is etched to the greatest extent very soon so; thereby the BARC layer 130 that has flowability and lose photoresist protection is caused irregular reduction etching, as shown in Figure 3.If continue etch polysilicon layer 120 with the irregular BARC layer of appearance profile as mask, then can cause grid 170 shape profiles irregular, as shown in Figure 4.
Application number is that 200410093459 Chinese patent application discloses a kind of grid production method that can reduce grid characteristic dimension; it adopts two-step reduction etching technique; the first step is that photoresist and anti-reflecting layer are cut down; form the hard mask of autoregistration by anisotropic etching again; under the protection of photoresist and organic antireflection layer, hard mask is carried out isotropic lateral etching then; finished for second step and cut down, form hard mask less than 90 nanometers.Though it has solved photoresist and has cut down for a long time in the technology the excessive a series of size offsets that bring of loss, physics pattern technological problems such as collapse, but the process of the manufacturing grid of this two-step reduction need form the hard mask of being made up of silicon nitride, this has increased the complex process degree undoubtedly, and the removal of hard mask use phosphoric acid, easily the grid that mixes up is caused corrosion.
For addressing the above problem, present a kind of measure of taking is to adopt multilayer etch mask technology, is typically three layers of etching polysilicon mask.Fig. 5 is for adopting the device profile map of multilayer etch mask.As shown in Figure 5, three layers of etch mask are included in the carbon containing adhesion layer 130 (A-Carbon) that polysilicon layer 120 surfaces form; Silicon nitride of Xing Chenging or silicon oxynitride layer 131 thereon; At the anti-reflecting layer 132 (BARC) of described silicon nitride or silicon oxynitride layer 131 surperficial spin coatings (spin on) formation, carbon containing adhesion layer 130 helps improving the adhesive ability of silicon nitride or silicon oxynitride layer 131.By the photoresist figure 140 of photoetching process formation patterning, utilizing photoresist figure 140 and three layers of etch mask (anti-reflecting layer 132, silicon nitride or silicon oxynitride layer 131 and carbon containing adhesion layer 130) then is that the mask etching polysilicon layer forms grid.Though this method can access appearance profile grid preferably, carbon containing adhesion layer 130 easily pollutes substrate surface in etching process, forms medium layer defect; Simultaneously, because silicon nitride or silicon oxynitride layer 131 quality are harder, cause the etching difficulty to increase, the etch period lengthening has reduced production efficiency.
Summary of the invention
The invention provides a kind of formation method of metal oxide semiconductor device grids structure, can obtain the good grid structure of appearance profile, and technology is simple, be fit to the high efficiency manufacturing of the following process node device of 65nm.
One object of the present invention is to provide a kind of formation method of metal oxide semiconductor device grids structure, comprising:
On Semiconductor substrate, form dielectric layer;
On described dielectric layer, form polysilicon layer;
On described polysilicon layer, form stack layer and define the position of grid;
Utilize described stack layer to form grid for the described polysilicon layer of mask etching.
Described stack layer structure comprises:
First anti-reflecting layer that on described polysilicon layer, forms;
Second anti-reflecting layer that on described first anti-reflecting layer, forms;
The photoresist layer that on described second anti-reflecting layer, forms.
Described first anti-reflecting layer is the Silicon-rich polymer, utilizes spin coating (spin-on) technology to form, and thickness is 100nm～2000nm.Described Silicon-rich polymer is that brewer Science and Technology Ltd. trade mark is the GF series of products.Described second anti-reflecting layer is silicon-based antifrelective layer (Si-BARC), and thickness is 50nm～500nm.The thickness of described photoresist layer is 500nm～2000nm.Described photoresist layer is comprised the position of the photoetching process of exposure, development with the definition grid.Described method comprises that also ashing removes the step of described first anti-reflecting layer.
Another object of the present invention is to provide a kind of formation method of metal oxide semiconductor device grids structure, comprising:
On Semiconductor substrate, form dielectric layer;
On described dielectric layer, form polysilicon layer;
On described polysilicon layer, form first anti-reflecting layer;
Second anti-reflecting layer that on described first anti-reflecting layer, forms;
The photoresist layer that on described second anti-reflecting layer, forms;
The described photoresist layer of patterning is with the position of definition grid;
The described photoresist layer of etching, second antireflection, first anti-reflecting layer and polysilicon layer successively.
Described first anti-reflecting layer is the Silicon-rich polymer, utilizes spin coating (spin-on) technology to form, and thickness is 100nm～2000nm.Described Silicon-rich polymer is that brewer Science and Technology Ltd. trade mark is the GF series of products.Described second anti-reflecting layer is silicon-based antifrelective layer (Si-BARC), 50nm～500nm.The thickness of described photoresist layer is 500nm～2000nm.Described method also comprises the step of utilizing cineration technics to remove described first anti-reflecting layer.
Compared with prior art, the present invention has the following advantages:
1, grid production method of the present invention has formed the three layer stack mask structures of being made up of anti-reflecting layer-silicon-based antifrelective layer (Si-BARC)-photoresist between polysilicon layer and photoresist layer, has simplified etching technics.Stack layer is as the multilayer etch mask of etch polysilicon grid.Owing to adopted this stack layer structure, the stack layer thickness of structure has guaranteed to exist all the time the mask of etching grid in the process of etching polysilicon, it is blocked up to make that photoresist layer need not to be coated with, even the photoresist figure is very narrow, for example reach 40nm, the problem that also can avoid the photoresist figure to collapse.And the texture material exquisiteness of silicon-based antifrelective layer, anti-reflecting layer adopts the Silicon-rich polymer, and hardness is higher, and the etching selection of these two kinds of materials is all better, helps characteristic dimension of line width and form the good grating of semiconductor element of appearance profile below 65nm.
2, because grid production method of the present invention adopts the stack layer structure with the mask of photoresist layer as the etch polysilicon grid, and the stack layer thickness of structure is enough to satisfy the needs as the grid etch mask, therefore need not to form hard mask, avoided because of using phosphoric acid to remove hard mask easily causes corrosion to grid problem.
3, the anti-reflecting layer of polysilicon surface is removed easyly, utilizes method such as oxygen ashing to be easy to remove, and helps forming the good grid of appearance profile.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing in proportion, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, amplified the thickness in layer and zone.
Fig. 1 to Fig. 5 is the generalized section of the existing grid production method of explanation;
Fig. 6 to Figure 10 is the generalized section according to the grid structure formation method of the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
The formation method of metal oxide semiconductor device grids structure provided by the invention is specially adapted to the manufacturing of characteristic size at 65nm and following grating of semiconductor element.Described semiconductor device is not only MOS transistor, can also be PMOS transistor and nmos pass transistor among the CMOS (complementary mos device).
Fig. 6 to Figure 10 is the generalized section according to the grid structure formation method of the embodiment of the invention.At first as shown in Figure 6, Fig. 6 shows the three layer stack mask structures that the formation method that adopts metal oxide semiconductor device grids structure of the present invention need form on Semiconductor substrate.Metal oxide semiconductor device of the present invention at first forms dielectric layer 110 on Semiconductor substrate 100.Substrate 100 can comprise semiconductor element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).The material that perhaps can also comprise other, for example indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide.Though in these several examples of having described the material that can form substrate 100, any material that can be used as Semiconductor substrate all falls into the spirit and scope of the present invention.
Gate features size of the present invention is below 65nm, and dielectric layer 110 is as gate dielectric layer, and its material is preferably high-k (high K) material.Can be used as the material that forms high-K gate dielectric layer and comprise hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc.Particularly preferably be hafnium oxide, zirconia and aluminium oxide.Though in this a few examples of having described the material that can be used for forming dielectric layer 110, this layer can be formed by other material that reduces grid leakage current.The growing method of dielectric layer 110 can be any conventional vacuum coating technology, such as ald (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) technology, be preferably atom layer deposition process.In such technology, can form smooth atom interface between substrate 100 and the dielectric layer 110, can form the gate dielectric layer of ideal thickness.In the inventive method, the live width of grid is below 65nm, and dielectric layer 110 preferred thickness are at 10-20
Between.It should be noted that in different situations dielectric layer 110 can adopt different materials and different thickness.
Then, on dielectric layer 110, form polysilicon layer 120.The material of polysilicon layer 120 is polysilicon or the polysilicon that mixes up metal impurities, and metal impurities comprise a kind of metal (for example titanium, tantalum, tungsten etc.) and metal silicide at least.The method that forms polysilicon layer 120 comprises ald (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD) technology.The film forming thickness of polysilicon layer 120 is 800
～1200
, be preferably 1000
In ensuing processing step, method of the present invention has formed stack layer 180 on polysilicon layer 120.Stack layer 180 comprises three layers, i.e. first anti-reflecting layer 150 that forms on described polysilicon 120; Second anti-reflecting layer 160 that on described first anti-reflecting layer 150, forms, and the photoresist layer 140 of patterning.First anti-reflecting layer 150 is the Silicon-rich polymer, and being preferably brewer Science and Technology Ltd. trade mark is the GF series of products, preferred GF315 or GF320.This GF layer 150 can utilize spin coating (spin-on) technology to form, and thickness is 100nm～2000nm, is preferably 1700nm.The inventive method still utilizes spin coating (spin-on) technology to form second anti-reflecting layer 160 on GF layer 150 surface, its thickness is preferably 300nm between 50nm～500nm.The material of second anti-reflecting layer 160 of the inventive method is Si-BARC, and its hardness and fine and smooth degree are all higher, very helps improving etching selection ratio.
Subsequently, form the photoresist layer at above-mentioned Si-BARC laminar surface, thickness is 500nm～2000nm, is preferably 1950nm.Utilize art pattern CAD photoresist layers such as conventional photoetching process is for example exposed, development, cleaning, to form the figure 140 of definition gate location.
The formation method of metal oxide semiconductor device grids structure of the present invention has formed the three layer stack mask structures of being made up of GF layer 150, Si-BARC layer 160 and photoresist figure 140 180 on polysilicon layer 120 surfaces.Owing to adopted this multilayer storehouse mask structure, the stack layer thickness of structure has guaranteed to exist all the time the mask of etching grid in the process of etching polysilicon, it is blocked up to make that photoresist layer need not to be coated with, even photoresist figure 140 is very narrow, for example has only 40nm, also the problem that can avoid the photoresist figure to collapse helps the manufacturing of the grid of characteristic dimension of line width below 65nm.
The patterning photoresist forms after the figure 140, and described storehouse mask layer 180 of etching and polysilicon layer 120 form grid.In this process, in reative cell, the using plasma etching technics carries out etching to above-mentioned each layer.During etching, the directivity of etching can realize by the bias power and negative electrode (substrate just) substrate bias power of control plasma source.Can control the etch period of storehouse mask layer 180 and polysilicon layer 120 by the control substrate bias power.In the present embodiment, feed etchant gas flow 50-400sccm in the reative cell, underlayer temperature is controlled between 20 ℃ and 90 ℃, and chamber pressure is 4-80mTorr, plasma source power output 50W-2000W.Etching agent adopts admixture of gas, and mist can comprise such as SF6, CHF3, CF4, chlorine Cl
2, oxygen O
2, nitrogen N
2, helium He and oxygen O
2Mist, perhaps helium-oxygen He-O
2, and inert gas or its mist (such as hydrogen Ar, neon Ne, helium He or the like), or its combination.This etching agent has very high etching selection for storehouse mask layer 180 and polysilicon layer 120.
With photoresist figure 140 is mask, and at first to second anti-reflecting layer 160 in the storehouse mask layer 180, just the Si-BARC layer carries out etching.In etching Si-BARC layer 160, photoresist figure 140 also is etched, thereby makes the reduced thickness of photoresist figure 140, as shown in Figure 7.
Continuation with remaining photoresist figure 140 and Si-BARC layer just second anti-reflecting layer 160 be mask, etching first anti-reflecting layer is GF layer 150 just.Etching this when two-layer, photoresist figure 140 has been etched to the greatest extent, Si-BARC layer 160 also is etched and attenuate, as shown in Figure 8.
Continuation is a mask with remaining Si-BARC layer 160, GF layer 150, etch polysilicon layer 120.In the process of etch polysilicon layer 120, remaining Si-BARC layer 160 at first is etched to the greatest extent, then etching GF layer 150.The higher GF layer 150 of the hardness that forms in the inventive method can slow down the etching to himself, thereby can not occur that polysilicon layer 120 is not etched as yet and GF layer 150 has been etched away and makes polysilicon layer 120 by the phenomenon of over etching.Polysilicon layer 120 be etched finish form grid 170 in, Si-BARC layer 160 has been etched away, but also may remain a spot of GF layer 150, as shown in Figure 9.
Rest parts GF layer 150 can adopt oxygen (O
2) removal of plasma ashing technology, and then obtain the good grid of appearance profile 170, as shown in figure 10.
Method of the present invention is by forming above-mentioned storehouse mask layer has guaranteed to exist all the time the etching grid in the process of etching polysilicon mask, it is blocked up to make that photoresist layer need not to be coated with, even the photoresist figure is very narrow, for example reach 40nm, the problem that also can avoid the photoresist figure to collapse helps the manufacturing of the grid of characteristic dimension of line width below 65nm.Because the mask effect of the storehouse mask layer structure of the inventive method, and the thickness of storehouse mask layer is enough to satisfy the needs as the grid etch mask, therefore need not to form hard mask, avoided because of using phosphoric acid to remove hard mask easily causes corrosion to grid problem.The anti-reflecting layer of polysilicon surface is removed easy, utilizes method such as oxygen ashing to be easy to remove, and helps forming the good grid of appearance profile.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (13)
1, a kind of formation method of metal oxide semiconductor device grids structure comprises:
On Semiconductor substrate, form dielectric layer;
On described dielectric layer, form polysilicon layer;
On described polysilicon layer, form stack layer and define the position of grid, the step that forms described stack layer comprises, first anti-reflecting layer that on described polysilicon layer, forms, second anti-reflecting layer that on described first anti-reflecting layer, forms, the photoresist layer that on described second anti-reflecting layer, forms, wherein, described first anti-reflecting layer is the Silicon-rich polymer, and described second anti-reflecting layer is the silicon-based antifrelective layer;
Utilize described stack layer to form grid for the described polysilicon layer of mask etching.
2, the method for claim 1 is characterized in that: described first anti-reflecting layer utilizes spin coating proceeding to form, and thickness is 100nm～2000nm.
3, method as claimed in claim 2 is characterized in that: described Silicon-rich polymer is that brewer Science and Technology Ltd. trade mark is the GF series of products.
4, method as claimed in claim 2 is characterized in that: the thickness of described second anti-reflecting layer is 50nm～500nm.
5, the method for claim 1 is characterized in that: the thickness of described photoresist layer is 500nm～2000nm.
6, the method for claim 1 is characterized in that: described photoresist layer is comprised the position of the photoetching process of exposure, development with the definition grid.
7, method as claimed in claim 6 is characterized in that: described method comprises that also ashing removes the step of described first anti-reflecting layer.
8, a kind of formation method of metal oxide semiconductor device grids structure comprises:
On Semiconductor substrate, form dielectric layer;
On described dielectric layer, form polysilicon layer;
Form first anti-reflecting layer on described polysilicon layer, described first anti-reflecting layer is the Silicon-rich polymer;
Second anti-reflecting layer that on described first anti-reflecting layer, forms, described second anti-reflecting layer is silicon-based antifrelective Si-BARC;
The photoresist layer that on described second anti-reflecting layer, forms;
The described photoresist layer of patterning is with the position of definition grid;
The described photoresist layer of etching, second antireflection, first anti-reflecting layer and polysilicon layer successively.
9, method as claimed in claim 8 is characterized in that: described first anti-reflecting layer, and utilize spin coating proceeding to form, thickness is 100nm～2000nm.
10, method as claimed in claim 9 is characterized in that: described Silicon-rich polymer is that brewer Science and Technology Ltd. trade mark is the GF series of products.
11, method as claimed in claim 9 is characterized in that: the thickness of described second anti-reflecting layer is 50nm～500nm.
12, method as claimed in claim 8 is characterized in that: the thickness of described photoresist layer is 500nm～2000nm.
13, method as claimed in claim 8 is characterized in that: described method also comprises the step of utilizing cineration technics to remove described first anti-reflecting layer.
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| CN102299100B (en) * | 2010-06-23 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of contact hole |
| CN102184852B (en) * | 2011-03-15 | 2016-03-02 | 上海集成电路研发中心有限公司 | Method for etching double-doped polysilicon |
| CN102842607B (en) * | 2011-06-23 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | Hard mask membrane layer structure in a kind of germanium silicon triode base and preparation method thereof |
| CN102446752B (en) * | 2011-10-21 | 2014-02-05 | 上海华力微电子有限公司 | Method for forming side wall and storage unit formed thereby |
| CN103137564B (en) * | 2011-11-22 | 2015-02-04 | 上海华虹宏力半导体制造有限公司 | Method for achieving expanding base region structure in bipolar-complementary metal oxide semiconductor (BiCMOS) device |
| CN109387902B (en) * | 2018-09-21 | 2021-06-04 | 中南大学 | Thermal compensation light wave multiplexing and demultiplexing chip and preparation method thereof |
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