CN101126876B

CN101126876B - Thin-film transistor LCD pixel structure and its making method

Info

Publication number: CN101126876B
Application number: CN200610109866A
Authority: CN
Inventors: 陈旭
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Priority date: 2006-08-18
Filing date: 2006-08-18
Publication date: 2010-05-12
Anticipated expiration: 2026-08-18
Also published as: CN101126876A

Abstract

The utility model discloses an LCD pixel structure of a thin film transistor (TFT), which comprises a glass substrate, a plurality of grid lines, a grid electrode, a grid insulating layer, a silicon island, a source electrode, a leakage electrode, a plurality of data lines, a passivation layer and a pixel electrode. A hole is formed in the grid insulating layer and the passivation layer at the upper end of the grid lines, and a pixel electrode material layer is formed at the lower end of the hole. The utility model also discloses a manufacturing method of the thin film transistor (TFT) LCD pixel architecture, with the through hole forming in the pixel electrode, and also forming a matched hole with the columnar pad in shape and size at the upper end of the grid lines corresponding to the position of the columnar pad. The utility model has the advantages of effectively improving the phenomenon of white Mura comparing with the prior art, increasing the craft degree of freedom, reducing process defects, and improving the picture quality.

Description

The manufacture method of pixel structure for thin film transistor liquid crystal display

Technical field

The present invention relates to Thin Film Transistor-LCD (TFT LCD) one pixel structure process method, relate in particular to a kind of manufacture method of thin film transistor pixel structure of improvement white Mura (the heterogeneity phenomenon that picture quality is white in color) phenomenon.

Background technology

In recent years, along with popularizing of digital to television, traditional CRT shows owing to its digitizing difficulty, and volume is big, weight is big, and shortcomings such as radiation are arranged, and the trend that is substituted by display technique of new generation occurred, representational new display technique has PDP, OLED, LCD etc.Wherein, LCD (LCD) is in light weight owing to having, and volume is thin, and radiationless, power consumption is little, and the display resolution advantages of higher has begun a large amount of popularizing, begins to become main product.

But existing LCD technology still has much room for improvement.For control enclosure thick, generally adopt spherical chock insulator matter (Ball Spacer) or cylindrical spacer (Post Spacer) to reach the thick purpose of control enclosure in the LCD technology, because having, cylindrical spacer can eliminate the light scattering that partition produces, can effectively improve advantages such as contrast, in nearest thin film transistor (TFT) (TFT) manufacturing process, adopt in a large number.But, because cylindrical spacer can produce slip when being under pressure, cause black matrix and TFT dislocation to produce light leak, on picture quality, show as white Mura phenomenon.

Fig. 1 a is depicted as a prior art array plane structural drawing, and the sectional view that A-A ' locates among Fig. 1 a is shown in Fig. 1 b.This array structure comprises: dielectric substrate; Be formed on grid line 1, gate electrode 2 on the dielectric substrate; Be formed on the gate insulation layer 4 on the gate electrode 2; Be formed on the silicon island 3 on the gate insulation layer 4; Be formed on the top drain electrode 6 and the source electrode 7 of silicon island 3; Data line 5 is structure as a whole with the drain electrode 6 of source-drain electrode; Be formed on passivation layer 8 on the source-drain electrode, and cover whole base plate; Passivation layer via hole 9 on the passivation layer on the formation source electrode 7; Pixel electrode 10 links to each other with source electrode 7 by passivation layer via hole 9; Grid line protuberance 11 and pixel electrode 10 common formation memory capacitance.

The manufacture craft flow process that it is concrete, shown in Fig. 3 a, deposition grid metal level on glass substrate forms grid line 1 (comprising grid protuberance 11), gate electrode 2 by common photoetching and etching technics earlier, and the sectional view that B-B ' locates among Fig. 3 a is shown in Fig. 3 b; Then, shown in Fig. 4 a, deposition gate insulation layer 4, semiconductor layer (active layer and ohmic contact layer) form active silicon island 3 by common photoetching and etching technics, and the sectional view that C-C ' locates among Fig. 4 a is shown in Fig. 4 b; Afterwards, shown in Fig. 5 a, sedimentary origin leaks metallic film, forms source electrode 7 and drain electrode 6 by common photoetching and etching, and the sectional view that D-D ' locates among Fig. 5 a is shown in Fig. 5 b; Subsequently, deposit passivation layer 8 shown in Fig. 6 a, and form passivation layer via hole 9 by common photoetching and etching, and the sectional view that E-E ' locates among Fig. 6 a is shown in Fig. 6 b; At last, the pixel deposition electrode film, and by photoetching formation pixel electrode 10, wherein pixel electrode 10 links to each other with source electrode 7 by passivation layer via hole 9, promptly finishes the making of matrix structure, shown in Fig. 1 a, 1b.

Fig. 2 is that cylindrical spacer is at the sectional view that becomes after box (Cell) technology finishes, after forming black matrix 13 and color film 14 on the color membrane substrates, position with TFT grid line correspondence below black matrix 13 forms cylindrical spacer 12, by finding out among the figure that cylindrical spacer 12 is supported on the insulation course of grid line top, thereby keep thick the stablizing of box, but when being under pressure, cylindrical spacer 12 can produce and slide, cause the black matrix 13 and the grid line of below to misplace, thereby the generation light leakage phenomena promptly produces white Mura.

Summary of the invention

The objective of the invention is defective, a kind of manufacture method of improved thin film transistor pixel structure is provided, by this structure-improved and manufacture method thereof at prior art, can effectively improve white Mura phenomenon, can increase the technology degree of freedom, reduce defective workmanship, improve picture quality.

To achieve these goals, the invention provides a kind of pixel structure for thin film transistor liquid crystal display, comprise: glass substrate, grid line, gate electrode, gate insulation layer, silicon island, source electrode, drain electrode, data line, passivation layer, and pixel electrode, wherein a hole is formed on the gate insulation layer and passivation layer of grid line top, and one deck pixel electrode material layer is formed at the hole bottom.

In the such scheme, the size and dimension of described hole is suitable with the column shaped spacer in becoming box.Described grid line and gate electrode are the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, perhaps are one of AlNd, Al, Cu, Mo, MoW or Cr or composite membrane that combination in any constituted.Described gate insulation layer or passivation layer are the monofilm of SiNx, SiOx or SiOxNy, perhaps are one of SiNx, SiOx or SiOxNy or composite membrane that combination in any constituted.The monofilm of described source electrode, data line or leak electricity very Mo, MoW or Cr perhaps is one of Mo, MoW or Cr or composite membrane that combination in any constituted.

To achieve these goals, the present invention provides a kind of manufacture method of pixel structure for thin film transistor liquid crystal display simultaneously, comprising:

Step 1 forms grid line, gate electrode, gate insulation layer, silicon island, data line, source electrode and drain electrode on transparent substrates;

Step 2, deposition one deck passivation layer on the substrate of completing steps one, form the pixel electrode via hole by passivation layer mask, exposure and etching, and the formation of the position of the corresponding cylindrical spacer strong point and cylindrical spacer shape and the suitable hole of size above grid line simultaneously;

Step 3, pixel deposition electrode layer on the substrate of completing steps two, by mask mask, exposure, above forming pixel electrode and hole, keep photoresist, carry out etching subsequently and obtain pixel electrode, also remain with the pixel electrode material layer in the hole simultaneously, carry out photoresist stripping process at last.

The present invention is with respect to prior art, owing on the insulation course above the grid line below the cylindrical spacer and passivation layer, formed hole with corresponding size in cylindrical spacer top and shape, like this in molding process, cylindrical spacer can be inserted in the hole, so not only can keep thick the stablizing of box, and when being subjected to the external force extruding, cylindrical spacer is owing to blocked by hole, can not be moved, thereby can effectively improve white Mura phenomenon, increase the technology degree of freedom, reduce defective workmanship, improve picture quality.

Below in conjunction with the drawings and specific embodiments the present invention is further illustrated in more detail.

Description of drawings

Fig. 1 a is the pixel planes structural drawing of prior art;

Fig. 1 b is the sectional view that A-A ' locates among Fig. 1 a;

Fig. 2 is the sectional view after the prior art molding process finishes;

Fig. 3 a is the floor map after prior art forms grid line and gate electrode;

Fig. 3 b is the sectional view that B-B ' locates among Fig. 3 a;

Fig. 4 a is the floor map after prior art forms the silicon island;

Fig. 4 b is the sectional view that C-C ' locates among Fig. 4 a;

Fig. 5 a is the floor map after prior art forms data line and source-drain electrode;

Fig. 5 b is the sectional view that D-D ' locates among Fig. 5 a;

Fig. 6 a is the floor map after prior art forms via hole;

Fig. 6 b is the sectional view that E-E ' locates among Fig. 6 a;

Fig. 7 a is a pixel planes structural drawing of the present invention;

Fig. 7 b is the sectional view that F-F ' locates among Fig. 7 a;

Fig. 8 is the sectional view of cylindrical spacer after molding process finishes among the present invention;

Fig. 9 a is the floor map after the present invention forms grid line and grid;

Fig. 9 b is the sectional view that G-G ' locates among Fig. 9 a;

Figure 10 a is the floor map after the present invention forms the silicon island;

Figure 10 b is the sectional view that H-H ' locates among Figure 10 a;

Figure 11 a is the floor map after the present invention forms data line and source, drain electrode;

Figure 11 b is the sectional view that I-I ' locates among Figure 11 a;

Figure 12 a is the floor map after the present invention forms via hole;

Figure 12 b is the sectional view that J-J ' locates among Figure 12 a.

Mark among the figure:

1, grid line; 2, gate electrode; 3, silicon island; 4, gate insulation layer; 5, data line; 6, drain electrode; 7, source electrode; 8, passivation layer; 8a, hole; 9, via hole; 10, pixel electrode; 10a, transparent pixels material layer; 11, grid line teat; 12, cylindrical spacer; 13, black matrix; 14, color film.

Embodiment

Shown in Fig. 7 a, be the present invention's one pixel planes structural drawing.This dot structure comprises: dielectric substrate; Be formed on grid line 1, gate electrode 2 on the dielectric substrate; Be formed on the gate insulation layer 4 on the gate electrode 2; Be formed on the silicon island 3 of gate insulation layer 4; Be formed on the drain electrode 6 and the source electrode 7 of 3 tops, silicon island; Data line 5 is structure as a whole with the drain electrode 6 of source-drain electrode; Be formed on the passivation layer 8 on the source-drain electrode, and cover whole base plate; Passivation layer via hole 9 on the formation source electrode 7; Pixel electrode 10 links to each other with source electrode 7 by passivation layer via hole 9; Grid line protuberance 11 and pixel electrode 10 common formation memory capacitance.These parts and prior art indifference, this dot structure is different from prior art and is characterised in that, and a hole 8a is formed on the gate insulation layer 4 and passivation layer 8 of grid line 1 top, and one deck pixel electrode material layer 10a is formed at the hole bottom.The sectional view that F-F ' locates among Fig. 7 a is shown in Fig. 7 b.

Fig. 8 is the sectional view of dot structure of the present invention after Cell technology finishes, after forming black matrix 13 and color film 14 on the color membrane substrates, position with thin film transistor (TFT) grid line correspondence below black matrix 13 forms cylindrical spacer 12, owing on the insulation course above the grid line below the cylindrical spacer 12 and passivation layer, formed hole 8a with corresponding size in cylindrical spacer 12 tops and shape, like this in Cell technology, cylindrical spacer 12 can be inserted in the hole 8a, so not only can keep thick the stablizing of box, and when being subjected to the external force extruding, cylindrical spacer 12 is owing to blocked by hole 8a, can not be moved, thereby can effectively improve white Mura phenomenon, increase technology Margin, reduce defective workmanship, improve picture quality.

Wherein, grid line 1 and gate electrode 2 can be the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, also can adopt among AlNd, Al, the Cu one of or arbitrarily and one of Mo, MoW or Cr or any composite membrane of forming, as Mo/AlND/Mo, AlNd/Mo.Gate insulation layer 4 or passivation layer 8 can be one of the monofilm of SiNx, SiOx or SiOxNy or SiNx, SiOx, SiOxNy or any composite membrane of forming.Source electrode 7 and drain electrode 6 can be the monofilm of Mo, MoW or Cr, perhaps for one of Mo, MoW, Cr or form composite membrane arbitrarily.

Fig. 9 a to 12b has provided above-mentioned one pixel structure process method.

At first, shown in Fig. 9 a, adopting magnetically controlled sputter method deposition grid metallic film on the glass substrate or on other substrates, that the grid metallic film adopts is the Mo/AlND/Mo (400/4000/600 of three-decker

), forming grid line 1 (comprising grid protuberance 11), gate electrode 2 by common photoetching and etching technics, the sectional view that G-G ' locates among Fig. 9 a is shown in Fig. 9 b.

Grid metallic film in this step can be the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, also can adopt among AlNd, Al, the Cu one of or arbitrarily and one of Mo, MoW or Cr or any composite membrane of forming, as Mo/AlND/Mo, AlNd/Mo.

Then, shown in Figure 10 a, deposition grid insulating film (4000

SiNx), semiconductive thin film (comprises active layer (1800 Amorphous silicon layer) with ohmic contact layer (N+ silicon layer 500

)), forming silicon island 3 by common mask etching, the sectional view that H-H ' locates among Figure 10 a is shown in Figure 10 b.

Grid insulating film in this step can be one of the monofilm of SiNx, SiOx or SiOxNy or SiNx, SiOx, SiOxNy or any composite membrane of forming.

Then, shown in Figure 11 a, sedimentary origin leaks metallic film, and the source is leaked metal level and adopted Mo (2200 ), forming source electrode 7 and drain electrode 6 by common photoetching and etching, the sectional view that I-I ' locates among Figure 11 a is shown in Figure 11 b.

The monofilm that metallic film can be Mo, MoW or Cr is leaked in this step source, perhaps for one of Mo, MoW, Cr or form composite membrane arbitrarily.

Subsequently, shown in Figure 12 a, deposition passivation protection film (2500

PVX), form via hole 9 by passivation layer mask and passivation layer etching, when forming via hole 9, the position of the corresponding cylindrical spacer strong point is by the hole 8a of passivation layer etching formation with the corresponding size in cylindrical spacer top above grid line 1, and the sectional view that J-J ' locates among Figure 12 a is shown in Figure 12 b.

At last; pixel deposition electrode ITO layer; form pixel electrode 10 and make pixel electrode 10 contact conducting by pixel electrode mask and pixel electrode etching with source electrode 7 by via hole; when pixel electrode mask and exposure back; keep photoresist simultaneously at pixel electrode and hole 8a place; like this when carrying out the pixel electrode etching; just can protect the grid line of hole below; simultaneously; in hole 8b, also remain with pixel electrode material layer 10a; obtain complete dot structure after finishing photoresist lift off at last, shown in Fig. 7 a, 7b.

Said structure and manufacture method provide as specific embodiment for the present invention is directed to a specific pixel structure and manufacture method, spirit of the present invention is to form the via hole of column shaped spacer and moving by this via hole control column shaped spacer on insulation course and/or passivation layer, thereby improve display quality, it may be used among various dot structures and the manufacture method thereof.

It should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art should can use different materials and equipment to realize it as required, promptly can make amendment or be equal to replacement, and not break away from the spirit and scope of technical solution of the present invention technical scheme of the present invention.

Claims

1. the manufacture method of a pixel structure for thin film transistor liquid crystal display is characterized in that, comprising:

Step 1 forms grid line, gate electrode, grid insulating film, silicon island, data line, source electrode and drain electrode on transparent substrates;

Step 2, deposition one deck passivation layer forms the pixel electrode via hole by passivation layer mask, exposure and etching on the substrate of completing steps one, and while position of the corresponding cylindrical spacer strong point on gate insulation layer above the grid line and passivation layer forms a hole;

Step 3, pixel deposition electrode layer on the substrate of completing steps two, by mask mask, exposure, above forming pixel electrode and hole, keep photoresist, carry out etching subsequently and obtain pixel electrode, one deck pixel electrode material layer is formed at the hole bottom, and this pixel electrode material layer contacts with grid line, carries out photoresist stripping process at last.

2. the manufacture method of pixel structure for thin film transistor liquid crystal display according to claim 1, it is characterized in that: the column shaped spacer in bore hole size that forms in the described step 2 and shape and the follow-up molding process is suitable.

3. the manufacture method of pixel structure for thin film transistor liquid crystal display according to claim 1 and 2, it is characterized in that: described grid line and gate electrode are the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, perhaps the composite membrane that is constituted for AlNd, Al, Cu, Mo, MoW and Cr combination in any.

4. the manufacture method of pixel structure for thin film transistor liquid crystal display according to claim 1 and 2, it is characterized in that: described grid insulating film or passivation layer are the monofilm of SiNx, SiOx or SiOxNy, perhaps are the composite membrane that SiNx, SiOx and SiOxNy combination in any are constituted.

5. the manufacture method of pixel structure for thin film transistor liquid crystal display according to claim 1 and 2, it is characterized in that: the monofilm of described source electrode, data line or leak electricity very Mo, MoW or Cr, the perhaps composite membrane that is constituted for Mo, MoW and Cr combination in any.