CN206975366U - Display device - Google Patents
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- CN206975366U CN206975366U CN201720837526.4U CN201720837526U CN206975366U CN 206975366 U CN206975366 U CN 206975366U CN 201720837526 U CN201720837526 U CN 201720837526U CN 206975366 U CN206975366 U CN 206975366U
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Abstract
A kind of display device; including array base palte and color membrane substrates; array base palte includes the first substrate; thin film transistor (TFT) array, flatness layer, common electrode layer, the second protective layer and pixel electrode layer are disposed with first substrate; via is provided with flatness layer, pixel electrode layer is contacted by the via with the drain electrode layer of thin film transistor (TFT) array；Color membrane substrates include the second substrate, are stretched on the second substrate formed with main spacer material, auxiliary spacer material and spacing spacer material, the position face of spacing spacer material and via and the bottom of spacing spacer material in via.Display device provided by the utility model, spacing spacer material is formed on color membrane substrates using existing via, a segment distance in via is stretched into the bottom of spacing spacer material, when the screen of display device has external force effect, the bottom that spacing spacer material is used to limit main spacer material is relative to the slip of array base palte upper surface, so as to limit the relative slip of color membrane substrates and array base palte, to improve the image quality of display device.
Description
Technical field
Display technology field is the utility model is related to, and more particularly to a kind of display device.
Background technology
Display device generally includes the array base palte to box shaping, color membrane substrates and is distributed in array base palte and color film base
Liquid crystal between plate, multiple posts for supporting array base palte and color membrane substrates are distributed between array base palte and color membrane substrates well
Shape PS (Photo Spacer, spacer material), liquid crystal are located in the space that column PS is supported.Wherein, multiple column PS are set
The homogeneity of display device integral thickness can be improved by putting, and improve the tolerance that display device is stirred to liquid crystal, and then be improved aobvious
The yield of showing device.Wherein, multiple column PS generally comprise main PS (Main Photo Spacer, main spacer material) and auxiliary PS
(Sub Photo Spacer, auxiliary spacer material), difference in height is generally there are between main PS and auxiliary PS, for example, main PS height is more than
Auxiliary PS, when display device is by ambient pressure, main PS first bears pressure and compressed, when main PS is compressed between main PS and auxiliary PS
Segment difference when being reduced to 0, main PS and auxiliary PS bears ambient pressure jointly.
With pursuit of the development and consumer of liquid crystal panel to high-penetration rate product, IPS (In-Plane
Switching, plane conversion) screen product increasingly favored, and it is also LCD (Liquid Crystal to reduce power consumption
Display, liquid crystal display) industry problems faced always.OC (organic planarization layer) processing procedure is added not only to reduce data wire
With the parasitic capacitance of gate line, reduction power consumption purpose can also be reached by reducing the parasitic capacitance of pixel electrode and data wire.
But after increasing OC in array base palte side, thin film transistor (TFT) upper surface can be caused to planarize, Main PS and film crystal upper surface
Frictional force diminish, when being acted on by external force, Main PS be easier to slide and cause to offset, cause pixel light leak and directly affect
The image quality of panel, if preventing pixel light leak by increasing the area in black matrix region, the aperture opening ratio of display screen can be reduced.
Utility model content
The purpose of this utility model is to provide a kind of display device, to solve to increase in the prior art pixel after OC processing procedures
The problem of light leak.
The utility model, which solves its technical problem, to be realized using following technical scheme.
The utility model provides a kind of display device, including array base palte and color membrane substrates, and array base palte includes the first lining
Bottom, thin film transistor (TFT) array, flatness layer, common electrode layer, the second protective layer and pixel electrode are disposed with the first substrate
Layer, via is provided with flatness layer, pixel electrode layer is contacted by via with the drain electrode layer of thin film transistor (TFT) array；Color membrane substrates
Including the second substrate, formed with main spacer material, auxiliary spacer material and spacing spacer material on the second substrate, spacing spacer material and via
The bottom of position face and spacing spacer material is stretched in via.
Further, array base palte also includes the first protective layer, the first protective layer cover film transistor array, flatness layer
Cover the first protective layer.
Further, via runs through the first protective layer.
Further, thin film transistor (TFT) array also include setting gradually grid layer on the first substrate, gate insulator,
Semiconductor layer and source layer, source layer are located at same layer with drain electrode layer.
Further, multiple main spacer materials, multiple auxiliary spacer materials and multiple spacing spacer material composition spacer material units, every
Auxiliary spacer material is set around main spacer material and spacing spacer material in underbed unit.
Further, spacing spacer material is equal with the height of main spacer material.
Further, distributed quantity of the spacing spacer material with main spacer material on color membrane substrates is equal.
Further, the height of auxiliary spacer material is less than the height of the spacing spacer material of main spacer material.
Further, spacing spacer material is frustum cone structure.
Further, spacing spacer material is terrace with edge structure.
Display device provided by the utility model, formed by using existing via on array base palte on color membrane substrates
Spacing spacer material, the position face of spacing spacer material and via and the bottom of spacing spacer material are stretched in via, are filled in display
When the screen put has external force effect, the bottom that spacing spacer material is used to limit main spacer material is relative to the cunning of array base palte upper surface
It is dynamic, so as to limit the relative slip of color membrane substrates and array base palte, to prevent pixel light leak under conditions of aperture opening ratio is constant, from
And improve the image quality of display device.
Brief description of the drawings
Fig. 1 is the partial plan view of array base palte in the utility model embodiment.
Fig. 2 is Fig. 1 partial structural diagram.
Fig. 3 is the partial cutaway schematic view of display device in the utility model embodiment.
Fig. 4 is the distribution schematic diagram of three kinds of spacer materials on color membrane substrates in the utility model embodiment.
Fig. 5 is the schematic flow sheet of the manufacture method of display device in the utility model embodiment.
Fig. 6 is the schematic flow sheet of the manufacture method of array base palte in the utility model embodiment.
Embodiment
In order to which the technical solution of the utility model is explained further, below in conjunction with attached in the utility model embodiment
Figure, the technical scheme in the embodiment of the utility model is clearly and completely described, it is clear that described embodiment is only
It is the utility model part of the embodiment, rather than whole embodiments.It is general based on the embodiment in the utility model, this area
The every other embodiment that logical technical staff is obtained under the premise of creative work is not made, belong to the utility model guarantor
The scope of shield.
Fig. 1 is the partial plan view of array base palte in the utility model embodiment, and the partial structurtes that Fig. 2 is Fig. 1 are shown
It is intended to, Fig. 3 is the partial cutaway schematic view of display device in the utility model embodiment.Fig. 1 to Fig. 3 is refer to, this practicality is new
The display device that type embodiment provides includes array base palte 100 and color membrane substrates 200, and array base palte 100 includes the first substrate 10,
Thin film transistor (TFT) array, flatness layer 70, common electrode layer 81, the second protective layer 90 and pixel are disposed with first substrate 10
Electrode layer 82, via 701 is provided with flatness layer 70, and pixel electrode layer 82 passes through the leakage of via 701 and thin film transistor (TFT) array
Pole layer 51 contacts；Color membrane substrates 200 include the second substrate 20, formed with main spacer material (Main Photo on the second substrate 20
Spacer, main PS) 21, auxiliary spacer material (Sub PS, auxiliary PS) 22 and spacing spacer material (Photo Spacer, spacing PS) 23, limit
Position spacer material 23 is stretched in via 701 with the position face of via 701 and the bottom of spacing spacer material 23.
Further, the first protective layer 60 is additionally provided with array base palte 100, the cover film crystal of the first protective layer 60
Pipe array, flatness layer 70 cover first protective layer 60, and the via 701 being arranged on flatness layer 70 runs through first protective layer
60。
As shown in figure 1, grid layer 20, the grid that thin film transistor (TFT) array also includes being successively set on the first substrate 10 are exhausted
Edge layer 30, semiconductor layer 40 and source layer 52, wherein, source layer 52 is located at same layer with drain electrode layer 51, and drain electrode layer 51 passes through
Via 701 contacts with pixel electrode layer 82.
Incorporated by reference to Fig. 2, in the present embodiment, orthographic projection of the spacing spacer material 23 on the first substrate 10 is right against via 701
Orthographic projection on the first substrate 10.The projection of main spacer material 21 and auxiliary spacer material 22 on the first substrate 10 is respectively positioned on source layer
Between 52 and drain electrode layer 51.In other embodiments, the projection of main spacer material 21 and auxiliary spacer material 22 on the first substrate 10 can
With not between source layer 52 and drain electrode layer 51.
Fig. 4 is the distribution schematic diagram of three kinds of spacer materials on color membrane substrates in the utility model embodiment.Incorporated by reference to Fig. 4, limit
The height of position spacer material 23 is identical with the height of main spacer material 21 and quantity is equal；The height of main spacer material 21 and spacing spacer material 23
Degree is more than the height of auxiliary spacer material 22, and distribution density of the main spacer material 21 on color membrane substrates 200 exists much smaller than auxiliary spacer material 22
Distribution density on color membrane substrates 200, distribution density of the spacing spacer material 23 on color membrane substrates 200 is with main spacer material 21 in coloured silk
Distribution density in ilm substrate 200 is equal.
In the present embodiment, the structure of main spacer material 21, auxiliary spacer material 22 and spacing spacer material 23 is round platform rod structure,
In other embodiment, main spacer material 21, auxiliary spacer material 22 and spacing spacer material 23 can also be terrace with edge rod structure.
Incorporated by reference to Fig. 3, when main spacer material 21 and spacing spacer material 23 are frustum cone structure, the bottom of main spacer material 21 is straight
When footpath is more than or equal to setting value T (i.e. close to the small disc diameter of array base palte 100), the base diameter of spacing spacer material 23
Equal to setting value T；When the base diameter (i.e. small disc diameter) of main spacer material 21 is less than setting value T, the bottom of spacing spacer material 23
Portion's diameter is equal to the base diameter of main spacer material 21, and in the present embodiment, T is, for example, 12um.
Please continue to refer to Fig. 3, the bottom of spacing spacer material 23 stretches into a segment distance in via 701 and is used to limit array base
The relative movement of plate 100 and color membrane substrates 200, in the present embodiment, the distance that spacing spacer material 23 is stretched into via 701 is, for example,
0.3~0.4um.
In the present embodiment, the facet diameter of spacing spacer material 23 is, for example, X, and array base palte 100 and color membrane substrates 200 are right
Precision during position is, for example, Y, to avoid array base palte 100 and color membrane substrates 200 from having deviation in contraposition, causes spacing spacer material
23 bottom can not be right against via 701 and stretch into the segment distance of via 701 1, and therefore, the minimum-value aperture of via 701 is, for example, (X
+2Y)。
In the present embodiment, semiconductor layer 40 is, for example, non-crystalline silicon or indium gallium zinc oxide.
Incorporated by reference to Fig. 4, three kinds of spacer materials (main spacer material 21, auxiliary spacer material 22 and spacing spacer material on color membrane substrates 200
23) be distributed with color membrane substrates 200 it is multiple, wherein, main spacer material 21 and spacing spacer material 23 are on color membrane substrates 200
Distributed quantity of the distributed quantity far fewer than auxiliary spacer material 22 on color membrane substrates 200.Multiple pixels are provided with color membrane substrates 200
Unit, each pixel cell is for example including three sub-pixels 300.In other embodiments, each pixel cell is for example including four
Individual sub-pixel 300.Further, Fig. 4, multiple main spacer materials 21, multiple auxiliary spacer materials 22 and multiple spacing dottle pins be refer to
Thing 23 forms spacer material unit 201.With main spacer material 21, auxiliary spacer material 22 and spacing spacer material in a spacer material unit 201
Exemplified by 23 distributed number, a spacer material unit 201 is for example including 36 pixel cells, a spacer material unit 201
Inside include five main spacer materials 21 and five spacing spacer materials 23, and each main spacer material 21 is adjacent with each spacing spacer material 23
Set, multiple auxiliary spacer materials 22 are set around main spacer material 21 and spacing spacer material 23.In the present embodiment, because of array base palte 100
OC processing procedures are employed, and the bottom of each main spacer material 21 is in contact with the upper surface of array base palte 100, when the face of display device
When on plate by external pressure, main spacer material 21 enters line slip easily with respect to the upper surface of array base palte 100, and spacing spacer material
23 bottom can limit the slip of main spacer material 21, so as to prevent light leak because being placed in via 701.In other embodiments,
The quantity for the pixel cell that each spacer material unit 201 includes can not be defined by the above-described embodiment, each spacer material unit
The quantity of the 201 three kinds of spacer materials included (main spacer material 21, auxiliary spacer material 22 and spacing spacer material 23) is not also by above-mentioned implementation
The restriction of example.
Fig. 5 is the schematic flow sheet of the manufacture method of display device in the utility model embodiment.It refer to Fig. 5, this reality
A kind of manufacture method of display device of example offer, including step are provided：
Array base palte 100 is formed, forming array base palte 100 includes：Thin film transistor (TFT) is sequentially formed on the first substrate 10
Array and flatness layer 70, formed with via 701 on flatness layer 70；
Formed color membrane substrates 200, formed color membrane substrates 200 be included on color membrane substrates 200 formed main spacer material 21, it is auxiliary every
Underbed 22 and spacing spacer material 23；
By color membrane substrates 200 and array base palte 100 to box, make the position face of spacing spacer material 23 and via 701, and limit
The bottom of position spacer material 23 is stretched in via 701.
The manufacture method of display device as described above, main spacer material 21, auxiliary spacer material 22 and spacing spacer material 23 pass through
It is fabricated using intermediate tone mask version.
In the present embodiment, thin film transistor (TFT) array also includes grid layer 20, the grid being successively set on the first substrate 10
Insulating barrier 30, semiconductor layer 40 and source layer 52, source layer 52 are located at same layer with drain electrode layer 51.
Fig. 6 is the schematic flow sheet of the manufacture method of array base palte in the utility model embodiment.In the present embodiment, formed
Array base palte 100 includes：
Grid layer 20 is formed on the first substrate 10；
Gate insulator 30 is formed on the first substrate 10 formed with grid layer 20；
Semiconductor layer 40 is formed on the first substrate 10 formed with gate insulator 30；
Drain electrode layer 51 and source layer 52, drain electrode layer 51 and source electrode are formed on the first substrate 10 formed with semiconductor layer 40
Same layer of the layer 52 on the first substrate 10；；
The first protective layer 60 is formed on the first substrate 10 formed with drain electrode layer 51 and source layer 52；
Flatness layer 70 is formed on the first substrate 10 formed with the first protective layer 60, formed with via on flatness layer 70
701, via 701 runs through first protective layer 60；
Pixel electrode layer 82 and common electrode layer 81, pixel electrode are formed on the first substrate 10 formed with flatness layer 70
Layer 82 is contacted by via 701 with drain electrode layer 51.
Incorporated by reference to Fig. 6, the method as described above for manufacturing array base palte 100, pixel electrode layer 82 and public is additionally included in
The second protective layer 90 is formed between electrode layer 81.Second protective layer 90 is between common electrode layer 81 and pixel electrode layer 82.
Display device provided by the utility model, the via 701 formed by using existing flatness layer 70, in color film base
Spacing spacer material 23 is formed on plate 200, wherein, orthographic projection of the spacing spacer material 23 on the first substrate 10 of array base palte 100
The orthographic projection on the first substrate 10 in via 701 is right against, a segment distance in via 701 is stretched into the bottom of spacing spacer material 23
So that the bottom of spacing spacer material 23 is limited in via 701, and when the screen of display device is acted on by external force, spacing dottle pin
The bottom that thing 23 is used to limit main spacer material 21 is relative to the slip of the upper surface of array base palte 100, so as to limit color membrane substrates 200
The relative slip with array base palte 100, to be prevented under conditions of aperture opening ratio is constant using small number of spacing spacer material 23
Only pixel light leak, so as to improve the image quality of display device.
Herein, term " comprising ", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, are removed
Those listed key elements are included, but also the other element being not expressly set out can be included.
Herein, the involved noun of locality such as forward and backward, upper and lower is to be located at parts in accompanying drawing in figure and zero
The mutual position of part is intended merely to the clear of expression technology scheme and conveniently come what is defined.It should be appreciated that the noun of locality
Use should not limit the claimed scope of the application.
Preferred embodiment of the present utility model is the foregoing is only, it is all in this practicality not to limit the utility model
Within new spirit and principle, any modification, equivalent substitution and improvements made etc., guarantor of the present utility model should be included in
Within the scope of shield.
Claims (10)
1. a kind of display device, it is characterised in that including array base palte (100) and color membrane substrates (200), the array base palte
(100) include the first substrate (10), be disposed with first substrate (10) thin film transistor (TFT) array, flatness layer (70),
Common electrode layer (81), the second protective layer (90) and pixel electrode layer (82), via is provided with the flatness layer (70)
(701), the pixel electrode layer (82) is connect by the drain electrode layer (51) of the via (701) and the thin film transistor (TFT) array
Touch；The color membrane substrates (200) include the second substrate (20), formed with main spacer material (21), auxiliary on second substrate (20)
Spacer material (22) and spacing spacer material (23), the position face of the spacing spacer material (23) and the via (701) and described
The bottom of spacing spacer material (23) is stretched in the via (701).
2. display device as claimed in claim 1, it is characterised in that the array base palte (100) also includes the first protective layer
(60), first protective layer (60) covers the thin film transistor (TFT) array, flatness layer (70) covering first protection
Layer (60).
3. display device as claimed in claim 2, it is characterised in that the via (701) runs through first protective layer
(60)。
4. display device as claimed in claim 1, it is characterised in that the thin film transistor (TFT) array also includes being successively set on
Grid layer (20), gate insulator (30), semiconductor layer (40) and source layer (52) on first substrate (10), the source
Pole layer (52) is located at same layer with the drain electrode layer (51).
5. display device as claimed in claim 1, it is characterised in that multiple main spacer materials (21), it is multiple it is described it is auxiliary every
Underbed (22) and multiple spacing spacer material (23) composition spacer material units (201), in the spacer material unit (201)
The auxiliary spacer material (22) is set around the main spacer material (21) and the spacing spacer material (23).
6. the display device as described in the claim 1, it is characterised in that the spacing spacer material (23) and the main dottle pin
The height of thing (21) is equal.
7. the display device as described in the claim 1, it is characterised in that the spacing spacer material (23) and the main dottle pin
Distributed quantity of the thing (21) on the color membrane substrates (200) is equal.
8. the display device as described in the claim 1, it is characterised in that the height of the auxiliary spacer material (22) is less than described
Main spacer material (21) and the height of the spacing spacer material (23).
9. the display device as described in the claim 1, it is characterised in that the spacing spacer material (23) is frustum cone structure.
10. the display device as described in the claim 1, it is characterised in that the spacing spacer material (23) is terrace with edge structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720837526.4U CN206975366U (en) | 2017-07-11 | 2017-07-11 | Display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720837526.4U CN206975366U (en) | 2017-07-11 | 2017-07-11 | Display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206975366U true CN206975366U (en) | 2018-02-06 |
Family
ID=61401899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720837526.4U Active CN206975366U (en) | 2017-07-11 | 2017-07-11 | Display device |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109509759A (en) * | 2019-01-04 | 2019-03-22 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display panel, display device |
| CN109904175A (en) * | 2019-03-19 | 2019-06-18 | 合肥京东方显示技术有限公司 | A kind of production method of display panel and a kind of display panel |
| CN111025780A (en) * | 2019-12-13 | 2020-04-17 | 武汉华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display device |
| CN113589598A (en) * | 2021-07-30 | 2021-11-02 | 惠科股份有限公司 | Display panel and display device |
| CN113741101A (en) * | 2021-08-31 | 2021-12-03 | 惠科股份有限公司 | Display panel and display device |
| CN114217481A (en) * | 2021-12-30 | 2022-03-22 | 绵阳惠科光电科技有限公司 | Display panel and display device |
| CN114371568A (en) * | 2022-01-18 | 2022-04-19 | 京东方科技集团股份有限公司 | Display panel and display device |
-
2017
- 2017-07-11 CN CN201720837526.4U patent/CN206975366U/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109509759A (en) * | 2019-01-04 | 2019-03-22 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display panel, display device |
| CN109904175A (en) * | 2019-03-19 | 2019-06-18 | 合肥京东方显示技术有限公司 | A kind of production method of display panel and a kind of display panel |
| CN111025780A (en) * | 2019-12-13 | 2020-04-17 | 武汉华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display device |
| CN113589598A (en) * | 2021-07-30 | 2021-11-02 | 惠科股份有限公司 | Display panel and display device |
| CN113741101A (en) * | 2021-08-31 | 2021-12-03 | 惠科股份有限公司 | Display panel and display device |
| CN114217481A (en) * | 2021-12-30 | 2022-03-22 | 绵阳惠科光电科技有限公司 | Display panel and display device |
| CN114371568A (en) * | 2022-01-18 | 2022-04-19 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN114371568B (en) * | 2022-01-18 | 2023-11-28 | 京东方科技集团股份有限公司 | Display panel and display device |
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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee after: Kunshan Longteng Au Optronics Co Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee before: Kunshan Longteng Optronics Co., Ltd. |