CN101098148A - Asynchronous sample rate correction by time domain interpolation - Google Patents
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Abstract
A circuit is provided to correct a sample rate by way of time domain interpolation having a first circuit loop having an up/down counter configured to receive an input signal and a feedback signal and an adder configured to receive the output signal from the up/down counter and to output a carry output as the feedback signal to the up/down counter and a second circuit loop configured to transmit a sum output from the adder to a modulator and to feed back an output signal from the modulator to an input of the adder.
Description
Technical field
The present invention relates to proofread and correct sample rate, particularly relate to by time domain interpolation and proofread and correct asynchronous sample rate.
Background technology
Analog signal is continuous variable quantity; It has value always and has continuous amplitude.Usually, Analog signals'digital is approximate to be to be undertaken by producing quantized values (numerical value with finite resolving power) sequence, and each quantized values is all with time interval of rule, the most approximate analog quantity.For example, by the digitlization of the audio signal of CD Player, finish by gathering each sample with so-called " 16 bit resolution " at the conventional ratio (regular ratio) of 44.1kHz." 16 bit resolution " means that the numeral of amplitude surpasses 16 binary digits, and therefore is accurate to about 1/65536 or about 16ppm (1,000,000/).Another is exemplified as the digital audio that is recorded on the DVD dish.In this case, each sample of amplitude can be differentiated 24 or about 0.06ppm, and the conventional ratio of gathering these samples is at 48kHz.Therefore, in the audio frequency consumer used, we used at least two kinds of different sample rates (44.1 kHz and 48kHz) usually, and two kinds of different amplitude resolutions (16 and 24).Figure 1A shows example: signal 1 is sampled at 44.1kHz here, and obtains the point sequence with " x " mark.Signal 2 is sampled at higher ratio (48kHz), and obtains the point sequence with " o " mark.
In system, exist two kinds of sample rates may be inconvenient: to consider such situation-arrive from the DVD source at 48 kHz digital audio data streams, and arrive when ADC coding chanteur (this situation occurs in when " OK a karaoke club ok " player and uses DVD musical instrument as a setting, and) from ADC and microphone source at second stream of 44.1kHz.Should how to mix these two kinds of signals and pass through identical audio output device output? this is a problem, if be used to move digital signal processor (or more precisely in different time arrival-48kHz sources because respectively import sample, if DSP is configured to operate on each sample of 48kHz), then each sample of 44.1kHz signal between each sample of 48kHz, arrive-they must be delayed, otherwise approximate conventional ratio to 48 kHz is so that handle together.This is " asynchronous sample rate " transfer problem, and present disclosure instruction, each sample with the clock signal relevant, asynchronous arrival of some selections, how can be approximately the sample at this clock: each asynchronous sample is converted to each synchronized samples in given clock zone, this given clock zone is still represented this signal exactly, just as this signal is sampled in original (new relatively now clock is asynchronous) territory.
The clock rate that the present invention need select is in fact than input sampling rate height.Figure 1B is presented at each sample sequence of 44.1kHz, how can be by approximate to clock rate higher, that carry out " zeroth order keeps (zero orderhold) " function.
" zeroth order maintenance " function only is to repeat the last sample seen by the higher speed clock.Notice in Figure 1B, do not reduce simultaneously usually with arbitrary sample at higher clock rate at each sample of 44.1kHz.Each higher clock rate sample is the repetition of the sample seen at last in the 44.1kHz territory.Therefore have error: as shown in Fig. 2 D-sample of first change in higher clock zone before, the input sample slightly changes.
With reference to Fig. 1 C, diagram operates in the sample analog input signal of frequency " f ".In putting into practice usually, each sample of signal is gathered at each sample point, and the quantity n of each sample determines the precision of sample here.The quantity of each sample is high more, can collect the more accurate reading of analog signal more.Therefore, the frequency of each sample of collection is far above the frequency of entering signal.For example with reference to Fig. 2 A, if entering signal 202 operates in 44.1kHz, then each data sample point 204 can be gathered at 27MHz.
Yet, when attempting the exact value that prediction signal locates on one point, produce error.Delay in the circuit of sampled data can cause the error that reads this signal.Sample point 206, for example with before each sample by continuous acquisition.Yet sample 208 is at transition point, in this case a sample 210 on the way (halfway) point read, next read sample 212 then, next be sample point 214 and 216.Continue, gather sample point 218, sample point 220 is at another transition point then.Traditional circuit reads a little 222, next is 224 and 226.Yet the actual each point that is different from ideal case is corner point 228 and 230.Once more, the delay in the circuit causes false signal (artifact), will produce as those, and for each signal that will in the middle of each error, read.In traditional system, input system imports over-sampling with accurate location (pinpoint) f (in), incoming frequency.Yet this method is inaccurate, and needs expensive circuit to gather sample more accurately.
With reference to Fig. 2 B, the diagram at hour when having compared each input point and each output.The hour occurred in after each corresponding input point when as can be seen, each was exported.Therefore, they are in different frequencies.With reference to Fig. 2 C, show the diagram of digitized signal.Wherein each x correspondence is in the actual input of input clock.Each o is corresponding correct hour when respectively exporting.Ideally, o is with each clock signal point of correspondence.In each legacy system that uses each synchronised clock, this is impossible, and produces false signal.
Therefore, there is demand in this area to being used for sampled signal more accurately, proofreading and correct the system and method for common (common) false signal.As will be seen, the present invention has realized these in good mode.
Summary of the invention
The invention provides a kind of circuit, configuration is proofreaied and correct each sample rate by the mode of time domain interpolation, comprising: first circuit loop, have on first/following counter, and dispose its first input signal and first feedback signal to be received in first incoming frequency; And first adder, dispose its with receive from first/first counter output signal of following counter, and on first/following counter exports the output of first carry as first feedback signal; The second circuit loop, dispose its with transmission from first adder first and output to first modulator, and will be from the first modulator output signal of first modulator, feed back to first input of first adder, wherein the first modulator output signal has first output frequency greater than first incoming frequency; The tertiary circuit loop has on second/following counter, disposes it to receive second feedback signal and at second input signal of second incoming frequency, described second incoming frequency is different with described first incoming frequency; And second adder, dispose its with receive from second/second counter output signal of following counter, and on second/following counter exports the output of second carry as second feedback signal; And the 4th circuit loop, dispose its with transmission from second adder second and output to second modulator, and will be from the second modulator output signal of second modulator, feed back to second input of second adder, wherein the second modulator output signal has first output frequency greater than second incoming frequency.
The present invention also provides a kind of method of proofreading and correct sample rate, comprising: receive first input signal that operates in first incoming frequency; Transmit on first input signal to the first/following counter first in the input; Transmission from first/first output signal of following counter, to first input of first adder; Outputing in first modulator of transmission first adder, wherein said first modulator is in the first output frequency timing greater than first incoming frequency, and wherein said first modulator produces the output of first modulator, and this first modulator output is fed second input as first adder; And if overflow at first adder, then transmit first carry output from first adder, resetting on first/following counter, described first carry output is fed back on first/first time input of following counter; Reception operates in second input signal of second incoming frequency; Transmit on second input signal to the second/following counter second in the input; Transmission from second/second output signal of following counter is to first input of second adder; Outputing in second modulator of transmission second adder, wherein said second modulator is in the first output frequency timing greater than second incoming frequency, and wherein said second modulator produces the output of second modulator, and this second modulator output is fed second input as second adder; And if overflow at second adder, then transmit second carry output from second adder, resetting on second/following counter, described second carry output is fed back on second/second time input of following counter.
The present invention also provides a kind of circuit, comprising: first circuit loop, have on first/following counter, and dispose its first input signal and first feedback signal to be received in first incoming frequency; And first adder, dispose its with receive from first/first counter output signal of following counter, and on first/following counter exports the output of first carry as first feedback signal; The second circuit loop, dispose its with transmission from first adder first and output to first modulator, and will be from the first modulator output signal of first modulator, feed back to first input of first adder, the wherein said first modulator output signal has first output frequency greater than first incoming frequency; Mix the circuit that has the first modulator output signal of first output frequency and have the blender input signal of first output frequency, wherein said blender input signal is processed from second input signal, and described second input signal has second incoming frequency less than first output frequency.
The present invention also provides a kind of method, comprising: receive first input signal that operates in first incoming frequency; Transmit on first input signal to the first/following counter first in the input; Transmission from first/first output signal of following counter is to first input of first adder; Outputing in first modulator of transmission first adder, wherein said first modulator is in the first output frequency timing greater than first incoming frequency, and wherein said first modulator produces the output of first modulator, and this first modulator output is fed second input as first adder; If overflow at first adder, then transmit from the output of first carry of first adder, resetting on first/following counter, described first carry output is fed back on first/first time input of following counter; And mix first modulator output with first output frequency and blender input signal with first output frequency, wherein said blender input signal is processed from second input signal, and described second input signal has second incoming frequency less than first output frequency.
Description of drawings
Figure 1A and Figure 1B illustrate the example of traditional method of sampling sampling;
Fig. 1 C and Fig. 2 A-2K illustrate each sample input signal and each sample point accordingly;
The digital phase-locked loop of Fig. 3 diagram configuration according to the present invention;
Fig. 4 is the flow chart of diagram the method according to this invention;
Fig. 5 is the sequential chart of the circuit output function of pictorial image 1C;
Fig. 6 illustrates the figure of error component;
Fig. 7 and Fig. 8 illustrate the figure that error frequency reduces.
Embodiment
The present invention is directed to the Signal Processing Element that is used for by time domain interpolation, execution asynchronous sample rate correction.In operation, digital signal is expressed as by the fixing digital quantity with the relative big time interval separates and flows.This signal is received as input, and processed to produce the output stream of the digital quantity of being separated by the different time intervals with relative weak point.This processing is operated and false signal or error is not incorporated in the signal flow of new generation, no matter different these facts of the time interval between input traffic and the output stream, and may be without any common factor in frequency separately.
According to the present invention, most of samples of output are the simple copys of input sample.Yet when detecting the change of input signal, for a such sample, output signal is set to the median between the new value of the old value of input and output.After producing this single intermediate sample, the sample of new input is now duplicated in output once more.Therefore, all regularly and the correction of sampling error all realize by this single intermediate sample of generation, and when this single intermediate sample was created in and detects input signal at every turn and changed, described input signal operated in than low rate.
The data point of observing interpolation has been inserted in the output stream, so that correction to be provided.The value of intermediate sample determines that from the relative timing of the input sample point between two output sample points described two output sample points surround the input sample.Determining of exact position between the output sample point, the input sample point is by the logical operation at output sampling rate is definite fully.That is to say that no matter there is not logical operation specific output sample rate true faster, the present invention still provides the device of accurately determining the input sample time.
Usually, the present invention is directed to the system and method with three fundamental characteristics: faster output clock, the point of determining the input clock change and execution time domain interpolation.Purpose is to solve the difference in the input and output data.
In one embodiment, faster output clock is used for gathering better each input signal point.In practice, input clock can be exported between the clock and reduce at each, and each input clock produces new sample point.In each output input of clock cycle may sampling simply.Yet (retrieved) input clock signal value that obtains again still may be lost.Therefore, from the figure angle, with reference to Fig. 2 D, shaded area 234 is the input signal parts of losing.Therefore, system will need to wait for the next clock cycle.This will be the situation in the legacy system.On the contrary, according to the present invention, ignore and pass through for the first time, and will lose the period 1.In next step,, produce the height point of present input signal and the intermediate point between the place as illustrated among Fig. 2 E.Therefore, point 238 is the points before the input signal, and point 240 is the intermediate points that obtain, and is new input points and put 242.According to the present invention, the area 236 shown in Fig. 2 E is the new signals with the median that obtains.The mode that obtains this value below will further be discussed.
Therefore, if the input sample that we only utilize when having input clock to be seen will produce error.Only after a last clock cycle, input will can not change.The shaded area of input is lost.Yet output can be delayed any amount of clock cycle.This will can not twist output.Therefore, input can be sampled, and postpones to produce one or more clock cycle, as top example.This permission system inserts the point between old value and the new value.Such value is inserted on one point, makes area identical.Output only once (ever) changed on the output cycle.System can compensate the fact that input does not change at clock by using intermediate point.In last result, each area keeps identical as top area 234 and 236.This realizes in one embodiment by using as illustrated in Figure 3 phase-locked loop.
With reference to Fig. 3, illustrate one embodiment of the present of invention, it provides a kind of system, is configured to come accurate location frequency by time domain interpolation.The phase-locked loop 300 of receiving inputted signal 302 is provided, this input signal 302 on each cycle of synchronous input signal/(U/D) counter controls 304 receives down.On/following counter output signal 306 (being 10 in this specific example) is to mould accumulator 308.The part of two feedback loops that accumulator 308 formation circuit move therein.Accumulator output signal 309 (also being 10 in this example) is to modulator 310, and this modulator 310 is according to clock 312 (being 27MHz in this example) operation, and generation is by the feedback signal and the corresponding output signal 316 of feedback loop 314 transmission.Mould accumulator output signal 320, it is the carry output pulse as the output of 44.1kHz carry output (carry-out) signal, and feeds back to/the following input of following counter 304 by feedback loop 322.In input signal 302 feed-ins/the last input of following counter 304.
Be in operation, operate in for example input signal of 44.1kHz of first frequency, be input to/the last input of following counter in.On/output of following counter is transferred to an input of adder.The output of mould accumulator is imported in the modulator, and it is in for example 27 MHz timing of second frequency, and first output " M " of the output generation circuit of modulator, also feeds back as second input of adder.Adder has and feeds back to/the carry output of the D score input of following counter.When adder is overflowed, on carry output is reset/following counter, the forward position of replacement output signal (second output).Adder adds to 10 output signals from " M " with the output (for example 10 outputs) of counter.Therefore, the point of sample rate is by formula x
O=x
N+ (M/N) (x
N+1-x
N) determine that wherein M/N is a timing error.
The definite following of sample time carries out in input.At first, mould accumulator 308 is configured to will import 313 and be added to operation sum (running total) at output clock rate 312.Accumulator 308 can be configured as digital adder and register with the operation of limited integer width, or other known adder of the increment value that is configured to add up.The operation sum will overflow at last to produce output pulse 320, because adder is a finite width, and will surpass maximum the most at last and will overflow.According to the present invention, relatively respectively overflow 320 the frequency speed and the arrival rate (rate of arrival) of each input sample 305 from mould accumulator 308.If the arrival rate of respectively importing sample surpasses the speed of respectively overflowing of accumulator, then increase the input of adder 313, this input is the amount of each output cycle addition.On the contrary, be lower than the speed of respectively overflowing, then reduce the input of adder from counter if respectively import the arrival rate of sample.Therefore, have control loop 314, wherein the input of adder will be fixed a value, make each speed equate.
With reference to Fig. 4, illustrate the flow chart 400 of the operation of describe, in general terms circuit 300.In step 402, receive the input signal that operates in incoming frequency.In step 404, in last/following counter, call upwards counting.In step 406, determined whether carry output pulse.If there is not carry output, process is recovered counting in step 408.Export in case carry occurs, process is transferred to step 410, here go up/it is to count the baseline value B among Fig. 5 down that following counter is reset.
Initial value in the counter is zero (318 are counter output among Fig. 3), so adder is never overflowed.Adder is adding zero.Yet final input signal increases counter.Now, adder is finally necessarily overflowed.In addition, when the speed of respectively overflowing of adder equals the speed of each input clock, counter will only arrive balance.For example, if the input clock rate is 48kHz, the output clock rate is that 1MegH2 and highway width are N=20, and then working as numerical value is that following hour counter stops to move:
This is that it is 46137/2 that adder is overflowed speed because at this numerical value
20* 1mhz=44e
3Therefore, existence is to " the upwards counting " of counter many just as " counting downwards ".
Observe when the system of describing pins, when the numerical value in the counter in fact fixedly the time, when input clock arrives, the error of the numeric representation input position in the counter.More particularly, when carry output took place, the numerical value in the register was checked by system.It has just exceeded total size (full scale).And this also is why the reason of overflowing was once arranged.With reference to Fig. 2 F, numerical value (A) (Counter Value) just has been added to the numerical value in the register.Therefore, the numerical value in the present register is certain numerical value that lacks than A.Numerical value in Fig. 2 F diagram register shows FS.Put it at certain at every turn (A) is added to sum, it has exceeded FS B, and B must be less than A.In this embodiment, numerical value is N in the counter, and the register spill-out is M.
With reference to Fig. 2 G, the quantity of observing M/N is sampling time error.This also will further specify in Fig. 2 H.Therefore, this is that system can know that the input clock point is positioned at situation where, the M/N among the discussed above and Fig. 3 of its consideration (lookat) in the illustrated loop.With reference to Fig. 2 I, illustrate intermediate sample and obtain by old sample P and old sample Q.Intermediate sample is
S＝P+M/N(Q-P).
Once more, where system can know the input clock position now, and can draw intermediate point S from these values.System inserts single sample in output stream.It is in the middle of a last input sample and next input sample.It is checked by the numeral of pinning the input and output clock and calculates.The amount that " M " overflows for the loop register, and " N " is the numerical value in the loop counter.Intermediate sample is
S＝P+M/N(Q-P)。
The present invention adopts observation: the position of input sample can be by just overflowing residue numerical value decision default in the accumulator of back.Position in the time signal of its amount of overflowing and relative time clock is proportional.Particularly, when detecting the overflowing of mould accumulator, surplus value be considered to and relative position between each sample of output speed, the input sample rate proportional, described surplus value is a remaining quantity in the finite width accumulator.Therefore, the position is determined, and intermediate sample can utilize this determine to produce, and need not any logical operation any faster than the output sampling rate clock.
With reference to Fig. 5, illustrate the sequential chart of compensating signal.Be in operation, the whole cycle (overcycle) of process is repeated, is C1-C4 in this example, and its per 4 cycles repeat.In illustrated specific example, there are four passages.One skilled in the art will appreciate that and to have more or less passage as may expect specific application the time.The duration of each passage is by determining divided by signal frequency with mould adder clock frequency 312, as in this example: 27MHz/44.1kHz=612.25.Therefore, each C1-C4 equates basically.Accumulator is crossed over time span N in each step, with increment accumulation size M.In case the mould accumulator overflows with the amount that surpasses greatest limit L, the circuit minimum baseline B that resets back then.According to the present invention, the spill-out M1-M4 in each stage is used to determine the point more accurately of the transformation of entering signal.Observe that this value changes in time and even may reduce example as shown in Figure 5.In fact, by every 612.25ms each sample point is set, error reduces.
Area definition compensation area.More particularly, with reference to Fig. 6, A
1Be the area of input, and A2 is the area about intermediate point.Each area is made up of each little area sample, and each area with the same.With reference to Fig. 2 J, the input signal area is by each the δ A from input
iAnd form, and the output signal area by from output signal and each δ A
iForm.Yet the center of gravity difference of each area sees it is tangible from each area sample shown in Fig. 2 J.With reference to Fig. 2 K, can obtain mathematic(al) treatment.If i (x) is an input signal, and x is the distance from interval starting point, and o (x) is an output signal.Each is arranged feasible at interval
o
ΔT∫i(x)δx＝o
ΔT∫o(x)δx，
Area under a curve is identical, yet,
o
ΔT∫ix(x)δx≠o
ΔT∫xo(x)δx，
This expression formula is the center of gravity in first moment (moment) of function.They do not match at the area that respectively separates.Yet according to the present invention, utilize two intermediate points, first moment can mate as follows:
o
2 Δ T∫ i (x) δ x=o
2 Δ T∫ o (x) δ x and o
2 Δ T∫ xi (x) δ x=o
2 Δ T∫ xo (x) δ x
Therefore the moment of each extra coupling increases the approximate rank of carrying out.In frequency domain, with reference to Fig. 7, if each is area matched, then error frequency reduces with 20dB/decade.In addition, with reference to Fig. 8, if each of each area mated constantly, then error frequency reduces with 40dB/decade.
Therefore, the invention provides a kind of system, it can have n rank time domain asynchronous signal sudden change (rage) transducer (ASRC) interpolation device.This reaches to find that actual input changes by using digital phase-locked loop.By using each intermediate sample, eliminated high order of frequency error arbitrarily.
The cross reference of related application
The present invention requires to submit on August 25th, 2005, application number is the priority of the applying date of 60/712661 U.S. Provisional Application.
Claims (22)
1. a circuit disposes and proofreaies and correct each sample rate by the mode of time domain interpolation, comprising:
First circuit loop has on first/following counter, disposes its first input signal and first feedback signal to be received in first incoming frequency; And first adder, dispose its with receive from first/first counter output signal of following counter, and on first/following counter exports the output of first carry as first feedback signal;
The second circuit loop, dispose its with transmission from first adder first and output to first modulator, and will be from the first modulator output signal of first modulator, feed back to first input of first adder, wherein the first modulator output signal has first output frequency greater than first incoming frequency;
The tertiary circuit loop has on second/following counter, disposes it to receive second feedback signal and at second input signal of second incoming frequency, described second incoming frequency is different with described first incoming frequency; And second adder, dispose its with receive from second/second counter output signal of following counter, and on second/following counter exports the output of second carry as second feedback signal; And
The 4th circuit loop, dispose its with transmission from second adder second and output to second modulator, and will be from the second modulator output signal of second modulator, feed back to second input of second adder, wherein the second modulator output signal has first output frequency greater than second incoming frequency.
2. circuit as claimed in claim 1, wherein said first incoming frequency is 44.1kHz.
3. circuit as claimed in claim 1, wherein said second incoming frequency is 48kHz.
4. circuit as claimed in claim 1, wherein said first output frequency is 27MHz.
5. circuit as claimed in claim 1 further comprises:
Mix and have first modulator output signal of first output frequency and circuit with second modulator output signal of first output frequency.
6. method of proofreading and correct sample rate comprises:
Reception operates in first input signal of first incoming frequency;
Transmit on first input signal to the first/following counter first in the input;
Transmission from first/first output signal of following counter is to first input of first adder;
Outputing in first modulator of transmission first adder, wherein said first modulator is in the first output frequency timing greater than first incoming frequency, and wherein said first modulator produces the output of first modulator, and this first modulator output is fed second input as first adder; And
If overflow at first adder, then transmit from the output of first carry of first adder, resetting on first/following counter, described first carry output is fed back on first/first time input of following counter;
Reception operates in second input signal of second incoming frequency;
Transmit on second input signal to the second/following counter second in the input;
Transmission from second/second output signal of following counter is to first input of second adder;
Outputing in second modulator of transmission second adder, wherein said second modulator is in the first output frequency timing greater than second incoming frequency, and wherein said second modulator produces the output of second modulator, and this second modulator output is fed second input as second adder; And
If overflow at second adder, then transmit from the output of second carry of second adder, resetting on second/following counter, described second carry output is fed back on second/second time input of following counter.
7. method as claimed in claim 6 further comprises:
Utilize first adder, with on first/first output signal of following counter, be added to first modulator output from first modulator.
8. method as claimed in claim 6 further comprises:
Utilize second adder, with on second/second output signal of following counter, be added to second modulator output from second modulator.
9. method as claimed in claim 6 further comprises:
Utilize first adder, with on first/first output signal of following counter, be added to first modulator output from first modulator; And
Utilize second adder, with on second/second output signal of following counter, be added to second modulator output from second modulator.
10. method as claimed in claim 6, wherein said first incoming frequency is 44.1kHz.
11. method as claimed in claim 6, wherein said second incoming frequency is 48kHz.
12. method as claimed in claim 6, wherein said first output frequency is 27MHz.
13. method as claimed in claim 6 further comprises:
Mix first modulator output with first output frequency and second modulator output with first output frequency.
14. a circuit comprises:
First circuit loop has on first/following counter, disposes its first input signal and first feedback signal to be received in first incoming frequency; And first adder, dispose its with receive from first/first counter output signal of following counter, and on first/following counter exports the output of first carry as first feedback signal;
The second circuit loop, dispose its with transmission from first adder first and output to first modulator, and will be from the first modulator output signal of first modulator, feed back to first input of first adder, the wherein said first modulator output signal has first output frequency greater than first incoming frequency;
Mix the circuit that has the first modulator output signal of first output frequency and have the blender input signal of first output frequency, wherein said blender input signal is processed from second input signal, and described second input signal has second incoming frequency less than first output frequency.
15. circuit as claimed in claim 14, wherein said first incoming frequency is 44.1kHz.
16. circuit as claimed in claim 14, wherein said first incoming frequency is 48kHz.
17. circuit as claimed in claim 14, wherein said first output frequency is 27MHz.
18. a method comprises:
Reception operates in first input signal of first incoming frequency;
Transmit on first input signal to the first/following counter first in the input;
Transmission from first/first output signal of following counter is to first input of first adder;
Outputing in first modulator of transmission first adder, wherein said first modulator is in the first output frequency timing greater than first incoming frequency, and wherein said first modulator produces the output of first modulator, and this first modulator output is fed second input as first adder;
If overflow at first adder, then transmit from the output of first carry of first adder, resetting on first/following counter, described first carry output is fed back on first/first time input of following counter; And
Mix first modulator output with first output frequency and blender input signal with first output frequency, wherein said blender input signal is processed from second input signal, and described second input signal has second incoming frequency less than first output frequency.
19. method as claimed in claim 18 further comprises:
Utilize first adder, with on first/first output signal of following counter, be added to first modulator output from first modulator.
20. method as claimed in claim 18, wherein said first incoming frequency is 44.1kHz.
21. method as claimed in claim 18, wherein said first incoming frequency is 48kHz.
22. method as claimed in claim 18, wherein said first output frequency is 27MHz.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/479,691 US7330138B2 (en) | 2005-08-29 | 2006-06-30 | Asynchronous sample rate correction by time domain interpolation |
| US11/479,691 | 2006-06-30 |
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| Publication Number | Publication Date |
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| CN101098148A true CN101098148A (en) | 2008-01-02 |
| CN100578940C CN100578940C (en) | 2010-01-06 |
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| CN200710127374A Active CN100578940C (en) | 2006-06-30 | 2007-07-02 | Circuit and method for correcting sample rate |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101645273B (en) * | 2009-07-10 | 2012-02-01 | 中国科学院声学研究所 | System for estimating and correcting difference in sampling rates and processing method thereof |
| CN102739596A (en) * | 2011-04-15 | 2012-10-17 | 南开大学 | Multiband OFDM-UWB system-based sigma-delta modulation method |
| CN101753133B (en) * | 2008-12-05 | 2014-06-25 | 飞思卡尔半导体公司 | Fast tracking and jitter improving method for asynchronous sampling rate conversion |
| CN110708069A (en) * | 2019-06-24 | 2020-01-17 | 珠海全志科技股份有限公司 | Asynchronous sampling rate conversion device and conversion method |
-
2007
- 2007-07-02 CN CN200710127374A patent/CN100578940C/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101753133B (en) * | 2008-12-05 | 2014-06-25 | 飞思卡尔半导体公司 | Fast tracking and jitter improving method for asynchronous sampling rate conversion |
| CN101645273B (en) * | 2009-07-10 | 2012-02-01 | 中国科学院声学研究所 | System for estimating and correcting difference in sampling rates and processing method thereof |
| CN102739596A (en) * | 2011-04-15 | 2012-10-17 | 南开大学 | Multiband OFDM-UWB system-based sigma-delta modulation method |
| CN102739596B (en) * | 2011-04-15 | 2015-09-09 | 南开大学 | A kind of ∑ △ modulator approach based on study of MB-OFDM-UWB system |
| CN110708069A (en) * | 2019-06-24 | 2020-01-17 | 珠海全志科技股份有限公司 | Asynchronous sampling rate conversion device and conversion method |
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| CN100578940C (en) | 2010-01-06 |
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