JP2007071865A - Method and circuit for interpolating encoder output - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce synchronization errors between the data request signal from exterior and the interpolated data, with an improvement in dynamic precision. <P>SOLUTION: Two-phase sinusoidal signals QA and QB output from an encoder 40 are interpolated by sample-and-hold (S/H) circuits 11a and 11b and A/D conversion (ADC) circuits 12a and 12b, and data D is output in accordance with a data request signal RQ from exterior. For this interpolation of encoder output, a direction discrimination up/down counter 52 is arranged near a two-phase square-wave uniform pulse generating circuit 6, and the data D is latched and output using a signal RQ2 which is obtained by delaying the data request signal RQ. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an encoder output interpolation method and an interpolation circuit, and in particular, an encoder (photoelectric type, magnetic type, electromagnetic induction type, capacitance type, etc.) that outputs a two-phase sine wave signal having a phase difference of 90 °. The two-phase sine wave signal output from the encoder, which is suitable for use in laser length measuring instruments, is interpolated by sample hold and A / D conversion, and data is output in response to an external data request signal The present invention relates to an encoder output interpolation method and an interpolation circuit.

  There is a processing limit on the interval between the gratings formed on the encoder scale. Therefore, in order to measure an interval finer than the scale grating, it is necessary to further subdivide the spatial period of the phase change of the sinusoidal signal output from the encoder, and for this reason, various interpolation circuits have been used conventionally. It has been.

  One of them is an A / D conversion method. In this method, sampling for A / D conversion must be performed discretely due to restrictions on the calculation time for A / D conversion and signal correction. At this time, if the sampling time is large, the origin signal and the external trigger signal (data request signal) such as servo control cannot be accurately synchronized, resulting in misalignment.

Therefore, as proposed in Patent Document 1, the applicant, as shown in FIG. 1 (corresponding to FIG. 1 of Patent Document 1), in accordance with encoder (not shown) outputs INA and INB, Sample and hold (S / H) circuits 11a and 11b, A / D conversion circuits 12a and 12b, a look-up table (LUT) memory 13 for generating a phase angle tan ⁻¹ (B / A), a register (REG) 14 Thus, a phase angle PH (also expressed as θ) is generated at the timing of the first clock CK1, and as shown in FIG. 2 (corresponding to FIG. 3 of Patent Document 1), the phase angle PH is higher than that of the first clock CK1 (8 in Patent Document 1). The dynamic accuracy is improved by linearly interpolating with a second clock CK2 and outputting two-phase square wave signals OUTA and OUTB (also referred to as QA and QB). In the figure, 2 is a data update circuit including a subtractor 21, an absolute value device 22, a polarity detection circuit 23, a limiter 24, a polarity addition circuit 25, an adder 26 and a register 27, 3 is a register 31, an adder 32, An integration circuit including the register 33, 4 is a carry detection circuit, and 5 is a two-phase square wave generation circuit.

  According to the interpolation circuit 42 shown in FIG. 1 of Patent Document 1, it is assumed that the trigger signal TRG is input from an external touch probe 38, for example, as shown in FIG. 3 (overall configuration diagram) and FIG. 4 (timing chart). In addition, by latching the output data D of the up / down counter 52 of the counter processing unit 50 that counts the two-phase square wave by the latch circuit 54, the position can be held in synchronization with the TRG without impairing the dynamic accuracy. In FIG. 3, 44 is an RS485 line driver, 46 is a cable, 48 is an RS485 line receiver, for example.

JP-A-10-132606 JP 2000-337854 A Japanese Patent Laid-Open No. 10-311741 JP-A-8-201111 JP 2005-77137 A

  However, (1) as the number of interpolations increases, the weight of the two-phase square wave increases, and the frequency of the two-phase square wave increases even at the same feed rate. Furthermore, (2) there is a problem that the cycle Pck1 of the first clock CK1 increases and the dynamic accuracy decreases. Details will be described below.

(1) Increasing the output frequency of a two-phase square wave For example, when the feed rate v = 1 m / s and the signal pitch λ = 20 μm, the resolution R is reduced from 0.1 μm by increasing the interpolation number Ni from 200 to 2000. At the same time, the edge interval Δt of the two-phase square wave increases from 10 MHz (= 1 m / s ÷ 0.1 μm) to 100 MHz (= 1 m / s ÷ 0.01 μm).

  For this reason, an inexpensive transfer method with a transfer rate of about 10 to 40 MHz such as RS422 and RS485 cannot be used.

  As a method of avoiding this, there is a method of integrating the function of the up / down counter 52 of the two-phase square wave with the interpolation circuit 42. In this case, the problem of data transfer of a two-phase square wave can certainly be avoided, but it is necessary to transmit counter data having more information. Transmitting data in parallel for long-distance transmission of several tens of meters leads to an increase in the number of cable cores and increases cost and current consumption. Therefore, the serial data transmission method as shown in Patent Document 2 is known. It has been.

  This serial data transmission method is often used particularly in a numerical control (NC) device, and outputs a signal synchronized with a data request signal RQ from the NC device, for example, in an asynchronous manner. The cycle is output at about 50 to 200 μs.

  At this time, in order to improve the positioning accuracy of the control device, dynamic accuracy of position data is required for RQ, and high-precision synchronization of sampling time of A / D conversion (ADC) is required. For example, when the feed rate is 10 mm / s and the dynamic accuracy is 10 nm, a synchronization accuracy of 1 μs or less is required (10 mm / s ÷ 10 nm = 1 μs).

(2) Increase in ADC sampling period Pck1 On the other hand, there is a restriction on the ADC sampling period Pck1. When the ADC bit length is increased for high interpolation, the ADC conversion time generally increases. Further, if the offset or amplitude ratio of the two-phase sine wave is corrected as described in Patent Document 3 in order to improve the interpolation accuracy, the sampling period Pck1 increases depending on the calculation time. As a result, the sampling period Pck1 may be larger than the aforementioned synchronization error. Therefore, a method for avoiding this and reducing the synchronization error is required.

  Furthermore, if an ADC circuit with a large number of bits is used to increase the resolution, there is a problem that the calculation time increases.

  The present invention has been made to solve the above-described conventional problems, and an object of the present invention is to improve dynamic accuracy by reducing a synchronization error between an external data request signal and interpolation data.

  The present invention relates to an encoder output interpolation method for interpolating a two-phase sine wave signal output from an encoder by sample hold and A / D conversion, and outputting data according to a data request signal from the outside. In the above, the direction discrimination up / down counter is disposed near the two-phase square wave equal pulse generation circuit, and the data request signal is delayed and the data is latched and output to solve the above problem. It is a thing.

  The direction discrimination up / down counter can be disposed in the same IC as the two-phase square wave equal pulse generation circuit.

  The data request signal can be delayed at least twice the sampling period of A / D conversion.

  The present invention also interpolates the two-phase sine wave signal output from the encoder by sample hold and A / D conversion, and outputs the data in accordance with the data request signal from the outside. In the insertion method, the time from A / D conversion sampling to data request is counted, and the data is interpolated based on the counting time to solve the same problem.

  The interpolation can be linear interpolation or curve interpolation.

  The present invention also interpolates the two-phase sine wave signal output from the encoder by sample hold and A / D conversion, and outputs the data in accordance with the data request signal from the outside. In the insertion method, the A / D conversion sampling is performed in synchronization with the data request signal to solve the above problem.

  The present invention also interpolates the two-phase sine wave signal output from the encoder by sample hold and A / D conversion, and outputs the data in accordance with the data request signal from the outside. In the insertion circuit, a direction discrimination up / down counter is arranged near the two-phase square wave equal pulse generation circuit, and a delay circuit for delaying the data request signal is provided, and the data is latched by the output of the delay circuit. The present invention provides an encoder output interpolation circuit characterized in that an output is provided.

  The present invention also interpolates the two-phase sine wave signal output from the encoder by sample hold and A / D conversion, and outputs the data in accordance with the data request signal from the outside. In the interpolation circuit, an encoder output interpolation comprising: a counting circuit for counting a time from sampling of A / D conversion to a data request; and an interpolation approximation circuit for interpolating data based on the counting time. A circuit is provided.

  The present invention also interpolates the two-phase sine wave signal output from the encoder by sample hold and A / D conversion, and outputs the data in accordance with the data request signal from the outside. In the interpolating circuit, an encoder output interpolating circuit characterized in that A / D conversion sampling is performed in synchronization with the data request signal.

  According to the present invention, even when an ADC having a long conversion time or a process having a long calculation time is performed, it is possible to perform interpolation with high accuracy without impairing dynamic accuracy. Therefore, it is inexpensive and easy to downsize.

  Furthermore, since the data at the time when the data request signal is input can be accurately delayed and latched or interpolated, high accuracy and high resolution can be maintained without increasing the computation time.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 5, the first embodiment of the present invention includes an encoder 40, S / H circuits 11a and 11b, ADC circuits 12a and 12b, and an LUT, similar to the conventional example shown in FIGS. Memory 13, data update circuit 2, integration circuit 3, carry detection circuit 4, two-phase square wave equal pulse generation circuit 6 corresponding to two-phase square wave generation circuit 5, direction discrimination up / down counter 52, latch circuit In the encoder apparatus having 54, a correction circuit 60 for performing offset adjustment and amplitude ratio adjustment similar to that of Patent Document 3 is inserted between the ADCs 12 a and 12 b and the LUT 13.

  Moreover, although data is normally transmitted with a two-phase square wave, high frequency transmission is difficult as described in the previous problem. Therefore, in this embodiment, the direction discrimination up / down counter 52 generates a two-phase square wave equal pulse. It is arranged near the circuit 6 (or in the same IC).

Then, a delay circuit 62 that delays the data request signal RQ twice the ADC sampling period Pck1 is provided, and the latch circuit 54 is operated by the output signal RQ2 of the delay circuit 62 to latch the data. The serial data DT is output to an external NC device or the like via.

  The delay circuit 62 generates a signal RQ2 obtained by delaying RQ by 2 × Pck1 in order to synchronize the timing with the delay time of the two-phase square wave equal pulse, which is used as a latch signal.

FIG. 6 shows a timing chart. x _n−1 , x _n , x _{n + 1} ... represent encoder positions. n is the order of the first clock CK1. _{Now, x n-1} and if RQ is input between _{x n,} ADC 12a, 12b conversion time, the conversion of ^tan -1 calculation and LUT13 correction circuit 60 (B / A), the time from x to θ There is a delay. Since the dynamic accuracy is improved when the ADC sampling period Pck1 is as short as possible, this delay time is assumed to be the same as Pck1. Further, a delay Pck1 by the two-phase square wave uniform pulse generation circuit 6 is also added. Therefore, if the data D is latched with the signal RQ2 obtained by delaying RQ by 2 × Pck1, the position error can be minimized.

In the case of a pipeline type ADC, the delay time t _ADC may be longer than Pck1 depending on the number of pipeline stages. In this case, the data D may be latched with the signal RQ2 after a delay (t _ADC + t _QUAD ), which is the sum of the delay time of the ADC and the delay time (t _QUAD = Pck 1) of the two-phase square wave equalization pulse generation circuit.

  Next, a second embodiment of the present invention will be described in detail.

  In the present embodiment, as shown in FIG. 7, instead of the two-phase square wave equalizing pulse generation circuit 6 and the direction discrimination up / down counter 52 of the first embodiment shown in FIG. An interpolation approximation circuit 80 is used.

  The time difference counting circuit 70 is a circuit for counting the time difference m from CK1 and RQ shown in the timing chart shown in FIG. 8, and includes an up / down counter 72 and a latch circuit 74 as shown in detail in FIG. The

  Here, the third clock CK3 for the up / down counter 72 is a clock having a frequency N times that of the first clock CK1, and N = Pck1 / Pck3. Therefore, m can be generated by the up / down counter 72 and the latch circuit 74 shown in FIG. If N is a power of 2, such as 32 or 64, for example, division can be easily performed by bit shift.

The interpolation approximating circuit 80 comprises a register (Z ⁻¹ ) 82, an adder 84, a multiplier 86, and an adder 88, as shown in FIG. 10, and linearly interpolates as shown in the following equation. Generate data.

  This data is serially output from the serial output circuit 56 as in the first embodiment.

  According to the second embodiment, it is possible to output a position obtained by linear approximation interpolation at a higher speed than in the first embodiment.

The interpolation approximating circuit 80 can take either the method according to the equation (1) shown in FIG. 10 or the following equation based on θ _n−1 , although the equation is equivalent.

  Although considerably complicated, an interpolation method using a quadratic curve in consideration of acceleration by Newton's interpolation method as shown in the following equation is also possible.

  This equation (3) can also be constituted by a multiplier and an adder, as in FIG.

  Next, a third embodiment of the present invention will be described with reference to FIG.

  This embodiment also has a time difference counting circuit 70 and an interpolation approximating circuit 80 similar to those of the second embodiment, but the output waveform is a bus output. That is, the trigger TRG from the touch probe 38 or the scanning probe is input, and the bus I / O circuit 90 disposed on the output side of the interpolation approximating circuit 80 switches, for example, the 3-bit address A (2: 0) to synchronize. Data D is output to 16-bit bus B (15: 0).

  In addition to this, all-bit parallel output, etc., is not limited to the form of output, and synchronization by linear (primary) interpolation or secondary interpolation of position regardless of the control signal source such as the control period and probe. The purpose of improving accuracy can be achieved.

  On the other hand, a method of synchronizing ADC sampling with an external trigger (RQ) as in the fourth embodiment shown in FIG. That is, the ADC may be sampled in synchronism with the external trigger as long as the external trigger (RQ) is constantly input and the condition that it is sufficiently fast with a constant period is satisfied. In the figure, 92a and 92b are analog low-pass filters (LPF) 94a and 94b are digital filters.

  This embodiment employs a digital filter for the output of the ADC, and as shown in Patent Document 4 and Patent Document 5, it is known that it is effective in improving resolution and interpolation accuracy. When using a digital filter, the ADC sampling period is required to be constant. Therefore, it is difficult to use a digital filter while strictly synchronizing with an external trigger, but according to this embodiment, an output synchronized with TRG can be obtained. The digital filter may be omitted.

  In each of the embodiments, since the correction circuit 60 is provided, high-precision interpolation is possible. Note that the correction circuit 60 may be omitted depending on the required interpolation accuracy.

  Further, the phase angle θ (= PH) can be obtained by a method other than the LUT.

The circuit diagram which shows the structure of the interpolation circuit which the applicant proposed in patent document 1 Time chart showing the same effect The circuit diagram which shows the whole structure of the encoder apparatus containing the interpolation circuit of patent document 1 Same time chart The block diagram which shows the structure of 1st Embodiment of this invention. Timing chart showing the operation of the first embodiment The block diagram which shows the whole structure of 2nd Embodiment of this invention. The block diagram which shows the structure of the counting circuit of 2nd Embodiment. Timing chart showing the operation of the second embodiment The block diagram which shows the structure of the interpolation approximation circuit used by 2nd Embodiment. The block diagram which shows the structure of 3rd Embodiment of this invention. Similarly, a block diagram showing the configuration of the fourth embodiment

Explanation of symbols

DESCRIPTION OF SYMBOLS 38 ... Touch probe 40 ... Encoder 42 ... Interpolation circuit 50 ... Counter processing part 52 ... Direction discrimination up / down counter 54 ... Latch circuit 56 ... Serial output circuit 60 ... Correction circuit 62 ... Delay circuit 70 ... Time difference counting circuit 80 ... Interpolation approximation Circuit RQ: Data request signal

Claims (10)

In the interpolation method of the encoder output for interpolating the two-phase sine wave signal output from the encoder by sample hold and A / D conversion, and outputting the data according to the data request signal from the outside,
A directional discrimination up / down counter is arranged near the two-phase square wave equal pulse generation circuit,
An encoder output interpolation method, wherein data is latched and output by a signal obtained by delaying the data request signal.   The encoder output interpolation method according to claim 1, wherein the direction discrimination up / down counter is disposed in the same IC as the two-phase square wave equal pulse generation circuit.   The encoder output interpolation method according to claim 1, wherein the data request signal is delayed at least twice the sampling period of A / D conversion. In the interpolation method of the encoder output for interpolating the two-phase sine wave signal output from the encoder by sample hold and A / D conversion, and outputting the data according to the data request signal from the outside,
Count the time from A / D conversion sampling to data request,
An encoder output interpolation method, wherein data is interpolated based on the counting time.   The encoder output interpolation method according to claim 4, wherein the interpolation is linear interpolation.   The encoder output interpolation method according to claim 4, wherein the interpolation is curve interpolation. In the interpolation method of the encoder output for interpolating the two-phase sine wave signal output from the encoder by sample hold and A / D conversion, and outputting the data according to the data request signal from the outside,
An encoder output interpolation method, wherein sampling of A / D conversion is performed in synchronization with the data request signal. In the interpolation circuit of the encoder output for interpolating the two-phase sine wave signal output from the encoder by sample hold and A / D conversion and outputting data according to the data request signal from the outside,
A directional discrimination up / down counter is arranged near the two-phase square wave equal pulse generation circuit,
A delay circuit for delaying the data request signal;
An encoder output interpolation circuit characterized in that data is latched and output by the output of the delay circuit. In the interpolation circuit of the encoder output for interpolating the two-phase sine wave signal output from the encoder by sample hold and A / D conversion and outputting data according to the data request signal from the outside,
A counting circuit for counting time from sampling of A / D conversion to data request;
An interpolation approximation circuit for interpolating data based on the counting time;
An encoder output interpolating circuit characterized by comprising: In the interpolation circuit of the encoder output for interpolating the two-phase sine wave signal output from the encoder by sample hold and A / D conversion and outputting data according to the data request signal from the outside,
An encoder output interpolation circuit characterized in that sampling of A / D conversion is performed in synchronization with the data request signal.

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