CN101087128A - Heat isolation access locket and its application in heat isolation CMOS time sequence circuit of no heat isolation gate - Google Patents

Abstract

Thermal insulation flip-latch and application in thermal insulation CMOS time sequence circuit without thermal insulation gate, current thermal insulation time sequence circuit includes thermal insulation trigger and thermal insulation gate, the invention fuses 'thermal insulation combination circuit' and 'thermal insulation memory circuit' to a integer, information memory function and combination logic function can not be divided in space, any thermal insulation time sequence circuit is composed by thermal insulation latch, without thermal insulation gate, it is not composed by thermal insulation trigger, it is a practical method which fulfills characters of thermal insulation time sequence circuit, the thermal insulation latch of the invention possesses three-rank thermal insulation latch: basic thermal insulation latch, secondary prompting thermal insulation latch and primary prompting thermal insulation latch, said thermal insulation latch includes inner core of three tube thermal insulation inverter and two control gates, every thermal insulation latch includes a rank of thermal insulation combination circuit and used in low power large scale digital integrated circuit.

Description

Adiabatic latch and its application in the adiabatic cmos sequence circuit without insulated door

Technical field：

The present invention relates to a kind of adiabatic latch and its application in the adiabatic cmos sequence circuit without insulated door, belong to the ultra-large digital integrated electronic circuit VLSI technical fields of low-power consumption.

Background technology：

With developing rapidly for MOS integrated circuit techniques, collection is increasing on a large scale, speed more and more higher, the very fast demand for development of microprocessor improves integration density, improves clock frequency and improves computing capability, thus the increase of power consumption is inevitably caused, the development trend of microelectronic shows that the power consumption of VLSI circuits increases by four times in every 3 years.Actually integrated level, speed and power consumption three are the entirety that is mutually related.Microcomputer is from 486,586, to Pentium II, Pentium III, and Pentium IV series are always all divided by speed, so that the raising of speed makes power problemses be on the rise, such as CPU more than Pentium III has to incidentally small electric fan.High encapsulation and falling temperature technique must be taken in order to reduce power consumption, the excessively thermally-induced systematic function of the problem of increase of power consumption faces very big, particularly circuit is unstable.The fast development of battery powered all kinds of portable computers and its communication equipment, efficient energy occupation mode turns into a significant design index therewith.The problem of power consumption of integrated circuit turns into extremely urgent, therefore, 90 generations year american semiconductor industrial combination can confirm that low power design technique is an emergency technical needs of IC design.At present, numerous production men face the immense pressure of reduction or control product power consumption, Integrated circuit designers are often had to using the performance of sacrifice circuit as cost to design low consumption circuit, and power consumption has turned into one of the most key Consideration of integrated circuit and important design performance parameter.The problem of low-power consumption digital circuit is the important research direction that current ultra-large digital integrated electronic circuit VLSI is applied and is in the urgent need to address.

Power consumption for reduction circuit has taken various measures, for example, reduce operating voltage, reduce the number of clock transistor and using measures such as dual-edge triggers, but these measures are still traditional thinking, and the reduction amplitude to power consumption is very limited.To break through this limitation, occur in that the novel circuit pattern for the characteristics of recovering with energy, referred to as adiabatic circuits (or energy recovery-type circuit), circuit is in transient process almost without energy loss, adiabatic process in similar thermodynamics, the energy that electric capacity can be will be stored in largely recovers to power supply, for reusing, so the reduction amplitude of adiabatic circuits power consumption is maximum.Adiabatic circuits are the VLSI new approach of low-power consumption digital circuit.Adiabatic circuits are used alternating source instead and powered, compared with using the conventional CMOS circuit of DC energy source, with difficulty.

Prior art and there is problem：

Have the conventional synchronization sequence circuit implementation that the research of adiabatic synchronous sequential circuits still there are some areas to imitate DC source：The trigger that first design clock edge is triggered, such as d type flip flop, T triggers, JK flip-flop etc.；Then the trigger excitation function of each clock edge of abbreviation triggering, obtains simplified D expression formulas, simplified T expression formulas, simplified J expression formulas, simplified K expression formulas etc., is achieved in adiabatic synchronous sequential circuits.Note：In conventional synchronization sequence circuit, these expression formulas simplified of description trigger excitation function can be two grades, three-level or multistage combinational logic expression formula, multistage combinational logic expression formula is constituted with multistage gate circuit, namely if the excitation function of sequence circuit is very complicated in practicality, for traditional sequence circuit using DC energy source, complex incentive function is easy to be realized with multistage-combination circuit (conventional two grades or the realization of three-level combinational circuit).This is the method for designing of traditional sequence circuit, sequence circuit is regarded as and constituted by combinational circuit and storage circuit two are most of, two major parts are spatially alienable, and storage circuit is made up of N number of trigger, combinational circuit is made up of some gate circuits, is spatially separated from each other.Combinational circuit is met：The stable output of t depends only on the input of t, and unrelated with the input state before t.But adiabatic combinational circuit is unsatisfactory for combinations thereof circuit definitions, because actually adiabatic combinational circuit contains the feature of sequential, postpone and memory composition containing having, it is not that combinational logic function is simply realized, namely adiabatic combinational circuit and adiabatic memory cell are to include each other, and ' adiabatic sequence circuit ' is seen as by spatially alienable ' adiabatic combinational circuit ' and ' the characteristics of adiabatic storage circuit ' two are largely constituted not in full conformity with adiabatic sequence circuit.Obstinately by this two most of division, implement highly difficult.When that must be realized with multiple-stage adiabatic combinational circuit, 1 clock must be increased by often increasing by 1 grade of adiabatic combinational circuit, conventional two or three-level combination adiabatic circuits are needed to increase by 2 or 3 clocks, in addition to needing increase clock number, containing thering is delay and memory composition to ignore.In such cases, current adiabatic Sequential Circuit Design is concentrated on is realized with single-stage excitation function (combinational logic function), difficult to the adiabatic sequence circuit practical application containing complicated multistage-combination logical function.As can be seen here, by ' adiabatic combinational circuit ' and ' the most of entirety that permeates of adiabatic storage circuit ' two, information storage function and combination logic function is set spatially to include (indivisible) each other, the circuit implementing method for finding out the characteristics of meeting adiabatic sequence circuit is critically important, is the method for reality.

So far, to the seldom of the circuit studies in the power clock source that provides the adiabatic sequence circuit energy, the research for being related to adiabatic circuits is largely focused on the reduction of adiabatic circuits power consumption itself, wherein power clock source largely uses preferable voltage source and preferable clock waveform, simple itself heat-insulating property of research adiabatic circuits on this basis, usually ignore the research of the circuit to actual power clock source, even without consideration：Too many clock number and too preferable clock waveform cause the difficulty of the realization of the circuit in power clock source.Studied successfully to be not equal to preferable power clock source and can be achieved with actual power clock source, only work out the actual power clock source circuit being engaged simultaneously, and it is supplied to studied adiabatic circuits with this power clock source circuit, power clock source circuit and adiabatic circuits are combined together research, so studies and be successfully only real success.With this while on the premise of circuit heat-insulating property and stability and reliability is met, it is considered to which practical power clock waveform is also critically important with the most sharp clock number of selection.

The content of the invention：

It is an object of the invention to provide a kind of by adiabatic combinational circuit adiabatic latch of the fusion in adiabatic storage circuit and its application in the adiabatic cmos sequence circuit without insulated door, any thermal insulation sequence circuit is all made up of adiabatic latch, in addition to adiabatic latch, no longer add insulated door.

Above-mentioned purpose is realized by following technical scheme：

A kind of adiabatic latch, a shared adiabatic latch of three-level：Basic thermal insulation latch, the adiabatic latch of secondary excitation and the adiabatic latch of primary excitation, per one-level, adiabatic latch is realized comprising the adiabatic combinational circuit of one-level, and described adiabatic latch is made up of the adiabatic phase inverter kernel of three pipes and two control doors；The adiabatic phase inverter kernel of three described pipes：A PMOS p in three pipes₁Source ground be 0 current potential, two NMOS tube n₁And n₂Source electrode meet clock cp and bear alternation current potential, p₁Drain electrode and n₁Drain electrode and n₂Grid be connected to Q jointly_rOutput end, p₁Grid and n₁Grid and n₂Drain electrode be connected to jointly

Output end, Q_rWith the indirect control pipe p on ground₃I.e. simplest S controls door, p₃Grid connect control signal

With the indirect control pipe p on ground₂I.e. simplest R controls door, p₂Grid connect control signal

RS=0 is met, that is, meets p₂And p₃Two pipes are not simultaneously turned on, p during S=1₃Pipe is turned on, p during R=1₂Pipe is turned on, generally control pipe p₂And p₃The connection in series-parallel combination of multiple PMOS control pipes is changed to, that is, is changed to control door, p₃It is changed to S control doors, p₂It is changed to R control doors, it is exactly to meet S to control door and R control doors not to simultaneously turn on to meet RS=0, S control doors are each connected by S logical formulas and R logical formulas and R controls the series parallel structure of door, wherein logic add+be connected in parallel connection, logic multiply is to connect series connection, and negated by variable and connect input control signal, i.e., because of PMOS control pipes low level effectively, there is difference for 120 ° of three clock cp₀、cp₁And cp₂, it is primary to encourage adiabatic latch to meet clock cp₀, it is secondary to encourage adiabatic latch to meet clock cp₁, basic thermal insulation latch meets clock cp₂, three-level thermal insulation flip-latch circuit structure is identical, and described control door be the control by adiabatic sequence circuit requirement.

Above-mentioned adiabatic latch, the adiabatic latch of described three-level：Basic thermal insulation latch, the adiabatic latch of secondary excitation and the adiabatic latch of primary excitation, one be output as Q and

Basic thermal insulation latch L_QIt is a control pipe p using simplest S control doors₃It is a control pipe p with simplest R control doors₂；One is output as Q_bWith The adiabatic latch L of secondary excitation_QbControl door and general R to control door using general S, work as p₃Grid connect

And p₂Grid meet Q_bWhen, by the basic adiabatic latch L_QWith the adiabatic latch L of secondary excitation_QbA main adiabatic latch is merged into, described main adiabatic latch meets described clock cp₁And cp₂, wherein L_QbMeet described clock cp₁, L_QMeet described clock cp₂, usually add a PMOS p₁₀, pipe p₁₀Grid meet Q_b, source electrode and drain electrode connect and ground respectively.

Application of the above-mentioned adiabatic latch in the adiabatic cmos sequence circuit without insulated door.

Application of the above-mentioned adiabatic latch in the adiabatic cmos sequence circuit without insulated door, the adiabatic decimal subtraction counting circuit of two grades of excitations is constituted with described adiabatic latch entirely, in addition to adiabatic latch, no longer add any insulated door, 4 primary adiabatic latch control door S of excitation_3a、R_3a、、S_2y、R_2y、S_1y、R_1y、S_0a、R_0aInput meet main adiabatic latch output Q₃、Q₂、Q₁And Q₀And its it is non-, but corresponding PMOS grid is connected afterwards by "+for parallel connection, for series connection, variable negates "；S_3aIt is single tube to control door, and grid connects R_3aIt is single tube to control door, and grid meets Q₃；S_0aIt is single tube to control door, and grid connects R_0aIt is single tube to control door, and grid meets Q₀；S_2yDoor is controlled to be connected for 2 pipes, 2 tube grids meet Q respectively₂And Q₃；R_2yControl door in parallel for 2 pipes, 2 tube grids connect respectively

With S_1yDoor is controlled to be connected for 2 pipes, 2 tube grids meet Q respectively₀And Q₁；R_1y, control door in parallel for 2 pipes, 2 tube grids connect respectively

With

4 main adiabatic latch control door S₃、R₃、S₂、R₂、S₁、R₁、S₀、R₀Input meet the adiabatic latch output Q of primary excitation_3a、Q_2y、Q_1yAnd Q_0aAnd its it is non-, but to be negated by variable and be followed by corresponding PMOS grid：S₃Door is controlled to be connected for 2 pipes, 2 tube grids connect respectively

With

R₃Door is controlled to be connected for 2 pipes, 2 tube grids meet Q respectively_2yWith S₀It is single tube to control door, and grid meets Q_0a；R₀It is single tube to control door, and grid connects

S₂Door is controlled to be connected for 2 pipes, 2 tube grids connect respectively

With

R₂Door is controlled to be connected for 2 pipes, 2 tube grids meet Q respectively_3aWith

S₁Door is controlled to be connected for 2 pipes, 2 tube grids meet Q respectively_2yWith R₁Control door in parallel for 2 pipes, 2 tube grids meet Q respectively_1yAnd Q_0a。

Application of the above-mentioned adiabatic latch in the adiabatic cmos sequence circuit without insulated door, the system counting circuit of thermal insulation 31 of two grades of excitations is constituted with described adiabatic latch entirely, in addition to adiabatic latch, no longer add any insulated door, 5 primary adiabatic latch control door S of excitation_4a、R_4a、S_3y、R_3y、S_2a、R_2a、S_1y、R_1y、S_0a、R_0aInput meet main adiabatic latch output Q₄、Q₃、Q₂、Q₁And Q₀And its it is non-, but to connect corresponding PMOS by "+for parallel connection, for series connection, variable negates " mode：S_4aIt is single tube to control door, and grid connects

R_4aIt is single tube to control door, and grid meets Q₃；S_2aIt is single tube to control door, and grid connects

R_2aIt is single tube to control door, and grid meets Q₂；S_0aIt is single tube to control door, and grid connects

R_0aIt is single tube to control door, and grid meets Q₀；S_3yDoor is controlled to be connected for 3 pipes, 3 tube grids connect respectively With

R_3yControl door in parallel for 3 pipes, 3 tube grids meet Q respectively₃、Q₂And Q₁；S_1yDoor is controlled to be connected for 2 pipes, 2 tube grids connect respectively

With

R_1yControl door in parallel for 2 pipes, 2 tube grids meet Q respectively₀And Q₁；5 main adiabatic latch control door S₄、R₄、S₃、R₃、S₂、R₂、S₁、R₁、S₀、R₀Input meet the adiabatic latch output Q of primary excitation_4a、Q_3y、Q_2a、Q_1yAnd Q_0aAnd its it is non-, but to be negated by variable and be followed by corresponding PMOS grid：S₄Door is controlled to be connected for 2 pipes, 2 tube grids connect respectively With R₄Door is controlled to be connected for 2 pipes, 2 tube grids connect respectively

And Q_0a；S₃Door is controlled to be connected for 3 pipes, 3 tube grids meet Q respectively_3y,

With

R₃Control door to be connected again with single tube after the parallel connection of 2 pipes, 2 tube grids in parallel connect respectively

With

Series Sheet tube grid connects

S₂Door is controlled to be connected for 2 pipes, 2 tube grids meet Q respectively_2aWith R₂It is the series connection of simultaneously 2 pipes of di- to control door, and the grid of 2 pipes of series connection connects respectively

With

The grid of another 2 pipe of series connection connects respectively

With

S₁Door is controlled to be connected for 2 pipes, 2 tube grids meet Q respectively_1yWith

R₁Door is controlled for, again with single tube parallel connection, 2 tube grids of connecting connect respectively after the series connection of 2 pipes

With

Single tube grid connects S₀Control door to be connected again with single tube after the parallel connection of 2 pipes, 2 tube grids in parallel meet Q respectively_4aAnd Q_3y, Series Sheet tube grid meets Q_0a；R₀It is single tube to control door, and grid connects

This technical scheme has following beneficial effect：

1. thermal insulation latch of the invention, a shared adiabatic latch of three-level：Basic thermal insulation latch, the adiabatic latch of secondary excitation and the adiabatic latch of primary excitation, per one-level, adiabatic latch is realized comprising the adiabatic combinational circuit of one-level, the implementation method of two grades of excitation adiabatic cmos sequence circuits by the adiabatic latch combinations of two-stage into two grades of adiabatic combinational circuit fusions in adiabatic storage circuit can be completed using it, all it is made up of adiabatic latch, no longer plus insulated door, adiabatic cmos sequence circuit and power clock generator are combined together design, so that the power consumption of adiabatic sequence circuit is compared with the power consumption of other nonadiabatic sequence circuits, having significantly reduces.

2. the adiabatic latch of the present invention, is made up of the adiabatic phase inverter kernel of three pipes, per one-level, adiabatic latch can be comprising the adiabatic combinational circuit of one-level for it, a shared adiabatic latch of three-level：Basic thermal insulation latch, the adiabatic latch of secondary excitation and the adiabatic latch of primary excitation, two grades of excitation functions are included in primary and secondary and encouraged in adiabatic latch, namely they realize two grades of adiabatic combinational logics simultaneously again, a kind of design of two grades of excitation adiabatic cmos sequence circuits of reality is completed：Two grades excitation adiabatic cmos decimal subtraction counting circuits and two grades excitation the system counting circuits of adiabatic cmos 31, the present invention can also application be three-level encourage adiabatic cmos sequence circuit implementation method.In order that having more close corresponding relation between the further advantage and feature of the present invention, other advantages and the specific function compared with the prior art produced will be described in the description of related circuit.

Brief description of the drawings：

The schematic diagram that Fig. 1 are constituted for the adiabatic phase inverter kernel of three pipes in the present invention；

Fig. 2 are one of the adiabatic latch of present invention circuit diagram；

Fig. 3 are the nearly sine three phase clock cp for providing two grades of excitation adiabatic circuits energy₀、cp₁And cp₂Oscillogram；

Fig. 4 are one of the adiabatic latch of the present invention course of work shape ripple figure of circuit diagram 2；

One of Fig. 5 thermal insulation latch effective power curve of circuit diagram 2；

Fig. 6 are two circuit diagrams of the adiabatic latch of the present invention；

Fig. 7 are the symbol of one of the adiabatic latch of present invention circuit；

Fig. 8 are the symbol of two circuits of the adiabatic latch of the present invention；

Fig. 9 are one of the main adiabatic latch of present invention circuit diagram；

Figure 10 are two circuit diagrams of the main adiabatic latch of the present invention；

Figure 11 are one of the main adiabatic latch of present invention circuit symbol；

Figure 12 are two circuit symbols of the main adiabatic latch of the present invention；

Figure 13 are one of the main adiabatic latch of the present invention course of work shape ripple figure of circuit diagram 9；

Figure 14 are Adiabatic logic Flip-flop circuit schematic symbol of the present invention；

Figure 15 are Adiabatic logic Flip-flop circuit diagram Figure 14 of the present invention symbol；

Figure 16 are the two grades of the invention adiabatic decimal subtraction counting circuitrys encouraged；

Figure 17 are adiabatic decimal subtraction counting circuit Figure 16 of two grades of excitations of present invention computer simulation oscillogram；

Figure 18 are adiabatic decimal subtraction counting circuit Figure 16 of two grades of excitations of present invention clock cp₂、cp₁And cp₀Computer simulation power consumption profile figure；

Figure 19 are the two grades of the invention system counting circuitrys of thermal insulation 31 encouraged；

Figure 20 are system counting circuit Figure 19 of thermal insulation 31 of two grades of excitations of present invention computer simulation oscillogram；

Figure 21 are system counting circuit Figure 19 of thermal insulation 31 of two grades of excitations of present invention clock cp₂、cp₁And cp₀Computer simulation power consumption profile figure；

Figure 22 are the three phase power clock generator circuit figures for the nearly sine for providing two grades of excitation adiabatic circuits energy；

Figure 23 are the three phase power clock generator circuit Figure 22 course of work shape ripple figures for the nearly sine for providing two grades of excitation adiabatic circuits energy；

Figure 24 are the three phase power clock generator circuit Figure 22 computer simulation power consumption profile figures for the nearly sine for providing two grades of excitation adiabatic circuits energy；

Figure 25 are the three phase power clock generator circuit figures for the nearly trapezoidal wave for providing two grades of excitation adiabatic circuits energy；

Figure 26 are the three phase power clock generator circuit Figure 25 course of work shape ripple figures for the nearly trapezoidal wave for providing two grades of excitation adiabatic circuits energy；

Figure 27 are the three phase power clock generator circuit Figure 25 computer simulation power consumption profile figures for the nearly trapezoidal wave for providing two grades of excitation adiabatic circuits energy；

Figure 28 are the system counting circuit Figure 19 course of work shape ripple figures of thermal insulation 31 of two grades of excitations of the three phase power clock for the nearly trapezoidal wave for providing two grades of excitation adiabatic circuits energy；

Figure 29 are system counting circuit Figure 19 of thermal insulation 31 of two grades of excitations of the three phase power clock for the nearly trapezoidal wave for providing two grades of excitation adiabatic circuits energy clock cp₂、cp₁And cp₀Computer simulation power consumption profile figure；

Figure 30 are the three phase power clock cp for the nearly trapezoidal wave for providing two grades of excitation adiabatic circuits energy₂、cp₁And cp₀Shape ripple figure.

The embodiment of the present invention：

Embodiment 1：

(1) adiabatic latch, a shared adiabatic latch of three-level：Basic thermal insulation latch, the adiabatic latch of secondary excitation and the adiabatic latch of primary excitation, per one-level, adiabatic latch is realized comprising the adiabatic combinational circuit of one-level, described adiabatic latch is made up of the adiabatic phase inverter kernel of three pipes and two control doors, the adiabatic phase inverter kernel of three described pipes：A PMOS p in three pipes₁Source ground be 0 current potential, two NMOS tube n₁And n₂Source electrode connect clock cp i.e. negative potential；p₁Drain electrode and n₁Drain electrode and n₂Grid be connected to Q jointly_rOutput end, p₁Grid and n₁Grid and n₂Drain electrode be connected to jointly

Output end, Q_rWith the indirect control pipe p on ground₃I.e. simplest S controls door, p₃Grid connect control signal

With the indirect control pipe p on ground₂I.e. simplest R controls door, p₂Grid connect control signal

RS=0 is met, that is, meets p₂And p₃Two pipes are not simultaneously turned on, p during S=1₃Pipe is turned on, p during R=1₂Pipe is turned on, generally control pipe p₂And p₃The connection in series-parallel combination of multiple PMOS control pipes is changed to, that is, controls door, p₃It is changed to S control doors, p₂It is changed to R control doors, it is exactly to meet S to control door and R control doors not to simultaneously turn on to meet RS=0, S control doors are each connected by S logical formulas and R logical formulas and R controls the series parallel structure of door, wherein logic add+be connected in parallel connection, logic multiply is to connect series connection, and negated by variable and connect input control signal, i.e., because of PMOS control pipes low level effectively, there is difference for 120 ° of three clock cp₀、cp₁And cp₂, it is primary to encourage adiabatic latch to meet clock cp₀, it is secondary to encourage adiabatic latch to meet clock cp₁, basic thermal insulation latch meets clock cp₂, three-level thermal insulation flip-latch circuit structure is identical, and described control door be the control by adiabatic sequence circuit requirements, described three-level thermal insulation latch：Basic thermal insulation latch, the adiabatic latch of secondary excitation and the adiabatic latch of primary excitation, one be output as Q and

Basic thermal insulation latch L_QIt is a control pipe p using simplest S control doors₃It is a control pipe p with simplest R control doors₂, one is output as Q_bWith

The adiabatic latch L of secondary excitation_QbControl door and general R to control door using general S, work as p₃Grid connect And p₂Grid meet Q_bWhen, by the basic adiabatic latch L_QWith the adiabatic latch L of secondary excitation_QbA main adiabatic latch is merged into, described main adiabatic latch meets described clock cp₁And cp₂, wherein L_QbMeet described clock cp₁, L_QMeet described clock cp₂, usually add a PMOS p₁₀, pipe p₁₀Grid meet Q_b, source electrode and drain electrode connect respectively

And ground.

Adiabatic latch of the present invention shows such as (the n in Fig. 2, including dotted line frame₁、n₂And p₁) the adiabatic phase inverter kernel of three pipes and the side of dotted line frame two two control pipe (p₂And p₃), pipe p₂And p₃Grid connect respectively

With

Meet RS=0 and (meet p₂And p₃Two pipes are not simultaneously turned on).Manage (n in Fig. 1 left sides two₁And p₁) it is each own grid capacitance C of conventional cmos phase inverter, wherein A ends and Y ends_AWith output capacitance C_Y, because of C_ALack adiabatic charging and discharging circuit, so one pipe n of increase₂, by n₂And n₁Each realize to C_AAnd C_YAdiabatic discharge and recharge, thus thinking conventional two pipe CMOS inverters are changed into the adiabatic phase inverter kernel of three pipes.Consider the convenience of power clock Generator Design and application, by the source ground (0 current potential) of three PMOSs, and the source electrode of two NMOS tubes meets clock cp (negative potential), normal power clock cp is nearly sine and nearly trapezoidal wave, show such as Fig. 3 and Figure 30, three clock cp in figure₀、cp₁And cp₂Difference is all 120 °, respectively automatically supplies the adiabatic latch of three classes：The adiabatic latch of primary excitation, the adiabatic latch of secondary excitation and basic adiabatic latch.

Embodiment 2：

Adiabatic latch Fig. 2 courses of work：Referring to Fig. 4, the most upper the first rows of Fig. 4 are the cp of nearly sine₂, cp₂Crest be 0V (), trough is -3V, i.e. the nearly 0V of clock high level (1 level), low level (0 level) nearly -3V, cp₂Connect latch clock end, cp₂Latch work (the adiabatic nearly 3V of phase inverter core power voltage), cp at nearly trough₂Latch stops (the adiabatic nearly 0V of phase inverter core power voltage) at nearly crest；Second row and the third line are respectively

With

Input waveform, the third line and fourth line are respectively

And Q_rWork wave.It can be seen from Fig. 4 that

1. met in interval a $\stackrel{\‾}{R}=1$ With $\stackrel{\‾}{S}=0,$ That is R=0 and S=1, now p₃Conducting and p₂Cut-off, works as cp₂During decline, n₂Conducting and n₁Cut-off, With cp₂Change, Q_rClamper exports (cp to ground (1 level) when being worked by latch₂At nearly trough), draw $\stackrel{\‾}{Q_r}=0$ And Q_r=1.

2. met in interval c $\stackrel{\‾}{R}=0$ With $\stackrel{\‾}{S}=1,$ That is R=1 and S=0, now p₂Conducting and p₃Cut-off, works as cp₂During decline, n₁Conducting and n₂Cut-off, Q_rWith cp₂Change,

Clamper is to ground (1 level), by cp₂At nearly trough, draw $\stackrel{\‾}{Q_r}=1$ And Q_r=0.

3. met in interval b $\stackrel{\‾}{R}=1$ With $\stackrel{\‾}{S}=1,$ That is R=0 and S=0, now p₂And p₃It is turned off, draws $\stackrel{\‾}{Q_r}=0$ And Q_r=1, that is, keep interval a to deposit state.

4. met in interval d $\stackrel{\‾}{R}=1$ With $\stackrel{\‾}{S}=1,$ That is R=0 and S=0, now p₂And p₃It is turned off, draws $\stackrel{\‾}{Q_r}=1$ And Q_r=0, that is, keep interval c to deposit state.

As can be seen here, adiabatic latch meets RS type characteristic equations：

$Q^{+}=S+\stackrel{\‾}{R}Q$ (constraints RS=0) (1)

Fig. 5 is the adiabatic effective power curves of latch Fig. 2, is found out by the most right flat of Fig. 5 curves, and now the adiabatic latch effective power consumption is expressed as P=0.15 μ W.

Two control pipes (simplest control door) on the side of Fig. 2 dotted line frames two are changed to multiple control pipe connection in series-parallel combinations (general control door), then draw Fig. 6.P on the right of Fig. 6₃With p₅After parallel connection, then and p₆Series connection (i.e. S controls door), is expressed as S=(A+B) C.Note：Logic add during connection+and for parallel connection, logic multiply is series connection, and negates connection input signal by variable, i.e. S control doors connect

With

Fig. 6 left sides p₂With p₄Series connection (i.e. R controls door), is expressed as R=DE, and connection variations per hour is negated, i.e. R control doors connect

With

The symbol of Fig. 2 and Fig. 6 latch shows such as Fig. 7 and Fig. 8 respectively.

There need to be three clock cp that difference is 120 °₀、cp₁And cp₂, it is primary to encourage adiabatic latch to meet clock cp₀, it is secondary to encourage adiabatic latch to meet clock cp₁, basic thermal insulation latch meets clock cp₂.If basic thermal insulation latch and the adiabatic latch of secondary excitation all use Fig. 2 forms, two adiabatic latch are combined, Fig. 9 is drawn.If the secondary adiabatic latch of excitation all uses Fig. 6 forms instead in Fig. 9 again, Figure 10, wherein S=AB (S control gate logics formula) and R=C (D+E) (R control gate logics formula) are drawn.Fig. 9 and Figure 10 are referred to as main adiabatic latch, and main adiabatic latch symbol shows such as Figure 11 and Figure 12 respectively.The adiabatic latch of primary excitation uses Fig. 6 or Fig. 2 form.The pipe p for usually adding a dotted line to represent in figure 9 and in figure 10₁₀, pipe p₁₀Grid meet Q_b, source electrode and drain electrode connect respectively And ground, to reduce parasitic capacitance coupling to this grade of circuitInfluence when end is in 1 level state is (because of Q_b=0, then p₁₀Conducting, makes clamper near-earth, i.e. clamper in 1 level).

Main adiabatic latch Fig. 9 courses of work：Referring to the Computer simulation results shown in Figure 13, the most upper the first rows of Figure 13 are the cp of nearly sine₂, cp₂Crest be 0V (), trough is -3V, main two clocks termination cp of adiabatic latch₁And cp₂；Second row and the third line are respectively

With

Input waveform, the third line and fourth line are respectively

With Q work waves, fifth line and the 6th row are respectively

And Q_bWork wave.It can be seen from Fig. 13 that

1. met in interval a $\stackrel{\‾}{R}=1$ With $\stackrel{\‾}{S}=0,$ That is R=0 and S=1, now p₆Conducting and p₅Cut-off, works as cp₁During decline, n₄Conducting and n₃Cut-off,

With cp₁Change, Q_bClamper is to ground (1 level), by cp₁At nearly trough, draw $\stackrel{\‾}{Q_b}=0$ And Q_b=1；Then

And Q_bMake p₃Conducting and p₂Cut-off, works as cp₂During decline, n₂Conducting and n₁Cut-off, With cp₁Change, Q clampers are to ground (1 level), by cp₂At nearly trough, draw $\stackrel{\‾}{Q}=0$ And Q=1.

2. met in interval c $\stackrel{\‾}{R}=0$ With $\stackrel{\‾}{S}=1,$ That is R=1 and S=0, now p₅Conducting and p₆Cut-off, works as cp₁During decline, n₃Conducting and n₄Cut-off, Q_bWith cp₁Change,

Clamper is to ground (1 level), by cp₁At nearly trough, draw $\stackrel{\‾}{Q_b}=1$ And Q_b=0；Then

And Q_bMake p₂Conducting and p₃Cut-off, works as cp₂During decline, n₁Conducting and n₂Cut-off, Q is with cp₂Change,

Clamper is to ground (1 level), by cp₂At nearly trough, draw $\stackrel{\‾}{Q}=1$ And Q=0.3. met in interval b $\stackrel{\‾}{R}=1$ With $\stackrel{\‾}{S}=1,$ That is R=0 and S=0, now p₅And p₆It is turned off, draws $\stackrel{\‾}{Q_b}=0$ And Q_b=1, that is, keep interval a to deposit state；Then

And Q_bMake p₃Conducting and p₂Cut-off, works as cp₂During decline, n₂Conducting and n₁Cut-off,

With cp₂Change, Q clampers are to ground (1 level), by cp₂At nearly trough, draw $\stackrel{\‾}{Q}=0$ And Q=1.

4. met in interval d $\stackrel{\‾}{R}=1$ With $\stackrel{\‾}{S}=1,$ That is R=0 and S=0, now p₅And p₆It is turned off, draws $\stackrel{\‾}{Q_b}=1$ And Q_b=0, that is, keep interval c to deposit state；Then

And Q_bMake p₂Conducting and p₃Cut-off, works as cp₂During decline, n₁Conducting and n₂Cut-off, Q is with cp₂Change,

Clamper is to ground (1 level), by cp₂At nearly trough, draw $\stackrel{\‾}{Q}=1$ And Q=0.

As can be seen here, main adiabatic latch meets RS type characteristic equations： $Q^{+}=S+\stackrel{\‾}{R}Q$ (constraints RS=0)

Embodiment 3：

The implementation method of two grades of excitation adiabatic cmos sequence circuits.

In traditional synchronizing sequential circuit that dc source is powered, traditional flip-flop is edging trigger (rising edge clock or trailing edge triggering), if clock falling edge is triggered, then traditional flip-flop receives input signal (J in the clock falling edge time first, K, D, T etc.), then the information that result storage is determined is received by signal, signal reception work during the information is saved in the clock falling edge in next cycle always is completed, and traditional flip-flop has ' reception ' and ' storage ' two-stage.The memory cell of synchronizing sequential circuit is trigger, and synchronizing sequential circuit is regarded as to be constituted by combinational circuit and storage circuit two are most of, and storage circuit is made up of N number of trigger, and combinational circuit is made up of some gate circuits, and two major parts are spatially alienable.

Adiabatic circuits are powered with the power clock of alternation, under power clock power supply function, it is necessary to by ' reception ', ' storage ', ' recovery ' and ' stopping ' four-stage (correspond to the forward position of clock pulses, the duration, after edge and stand-down).Adiabatic latch and adiabatic combinational circuit all have to pass through this four-stage, as can be seen here, meet conventional component circuits definition " the stable output of t depends only on the input of t; and it is unrelated with the input state before t " adiabatic combinational circuit be non-existent, i.e. adiabatic combinational circuit also has ' storage ', is best selection in adiabatic storage circuit by the fusion of adiabatic combinational circuit.If the method for traditional sequence circuit of imitation DC energy source, first design Adiabatic logic Flip-flop, an Adiabatic logic Flip-flop must be constituted by several adiabatic latch, such as Figure 14 constitutes an Adiabatic logic Flip-flops with three adiabatic latch (Figure 15 is its symbol), this is suitable for the implementation method that one-level encourages adiabatic cmos sequence circuit, wherein combinational circuit part can only realize one-level incentive combination function, such composite function can not be very complicated, variable number particularly with item can not be a lot, many variable numbers with item to that should there are many control pipes to be in series, many pipes, which are connected, make it that conducting resistance is increased, influence control ability, even make control failure, cisco unity malfunction.In addition, the very complicated control pipe combination of very complicated composite function correspondence, increase parasitic capacitance produces the possibility of detrimental effect.

The implementation method of two grade excitation adiabatic cmos sequence circuit of the present invention by two grades of adiabatic combinational circuit fusions in adiabatic storage circuit, the implementation method of its not now conventional sequence circuit based on Adiabatic logic Flip-flop, but based on the circuit realiration by two grades of adiabatic combinational circuits fusions in adiabatic storage circuit, will adiabatic latch and adiabatic combinational circuit be merged, information storage function and combination logic function is spatially included (indivisible) each other.Using two grades of excitations：Incentive combination function is divided into two grades of forms, primary incentive combination function is realized by the adiabatic latch of primary excitation, produced output is sent to the adiabatic latch of secondary excitation, the output of the adiabatic latch of secondary excitation is sent to basic adiabatic latch, basic thermal insulation latch uses Fig. 2 forms, only two control pipes, control pipe control ability is strong, the first two grade of adiabatic latch of basic adiabatic latch can be seen as two grades of adiabatic combinational circuits.If basic thermal insulation latch is equal (being set to N) with the number of the adiabatic latch of secondary excitation, each basic adiabatic latch and the adiabatic latch of secondary excitation are combined, N number of main adiabatic latch shown such as Figure 10 is constituted；The number of the adiabatic latch of primary excitation is equal (being set to M), there is three kinds of possibility in adiabatic cmos sequence circuit：M ＞ N, M ＜ N and M=N.As ' M=N ' and ' main adiabatic latch only has two control pipes ', then the adiabatic cmos sequence circuit is converted into the adiabatic sequence circuit being made up of N number of Adiabatic logic Flip-flop, in other words, the adiabatic sequence circuit being made up of N number of Adiabatic logic Flip-flop is the special case of two grades of excitation adiabatic cmos sequence circuits.Most k pipes are allowed to connect according to the adiabatic sequence circuit control door of Adiabatic logic Flip-flop, then the adiabatic sequence circuit of two grades of excitations can be by k²Pipe series connection (correspondence k²Variable and item) it is decomposed into two grades and goes realization, wherein every grade of at most only k pipes series connection (correspondence k variables and item), two grades are combined and realize k²Variable and item.The present invention can also be extended to the implementation method that three-level encourages adiabatic cmos sequence circuit, wherein use basic adiabatic latch instead Fig. 6 forms, there are multiple control pipes, this is that one kind merges the adiabatic combinational circuit of three-level in adiabatic storage circuit, adiabatic sequence circuit can be seen as to be made up of the adiabatic combinational circuit (latch) of three-level, because three adiabatic latch are to be combined by three-level combinational circuit.In three-level excitation adiabatic cmos sequence circuit, the number of the adiabatic latch of primary excitation is M, and the number of the adiabatic latch of secondary excitation is N, and the number of the adiabatic latch of final stage excitation is each unequal for L, wherein M, N and L, can also part it is equal or complete equal.If typically allowing most k pipes to connect using the adiabatic sequence circuit of Adiabatic logic Flip-flop, the adiabatic sequence circuit of three-level excitation can be by k³Pipe series connection (correspondence k³Variable and item) it is converted into three-level and goes realization, every grade of k pipe series connection (correspondence k variables and item).Above-mentioned two grades of excitations adiabatic cmos sequence circuit is the special case that three-level encourages adiabatic cmos sequence circuit.

Embodiment 4：

Two grades of described excitation adiabatic cmos sequence circuit modular designs：

The adiabatic decimal subtraction counting circuit of (1) two grade of excitation.

8421BCD code decimal subtraction counting circuits Q₃Q₂Q₁Q₀State change be：1001 → 1000 → 0111 → 0110 → 0101 → 0100 → 0011 → 0010 → 0001 → 0000 → 1001 ..., carry out successively as follows：

1. routinely drawn first using the method for designing of the sequence circuit of rest-set flip-flop：

${\mathrm{<figure-callout\; id="3"\; label="S"\; filenames="A20061013908900311.png,A20061013908900341.png"\; state="\{\{state\}\}">S</figure-callout>}}_3=\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="A20061013908900311.png,A20061013908900341.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="A20061013908900271.png,A20061013908900301.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2}\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}\stackrel{\&OverBar;}{Q_0},$ ${\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="A20061013908900311.png,A20061013908900341.png"\; state="\{\{state\}\}">R</figure-callout>}}_3=({\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="A20061013908900311.png,A20061013908900341.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3+Q_2)\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}\stackrel{\&OverBar;}{Q_0}---\left(2a\right)$

${\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="A20061013908900271.png,A20061013908900301.png"\; state="\{\{state\}\}">S</figure-callout>}}_2=Q_3\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}\stackrel{\&OverBar;}{Q_0},$ ${\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="A20061013908900271.png,A20061013908900301.png"\; state="\{\{state\}\}">R</figure-callout>}}_2=\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="A20061013908900311.png,A20061013908900341.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}\stackrel{\&OverBar;}{Q_0}---\left(2b\right)$

${\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">S</figure-callout>}}_1=({\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1+Q_2)\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}\stackrel{\&OverBar;}{Q_0},$ ${\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">R</figure-callout>}}_1=Q_1\stackrel{\&OverBar;}{Q_0}---\left(2c\right)$

$S_0=\stackrel{\&OverBar;}{Q_0},$ R₀=Q₀    (2d)

2. then write out secondary excitation function.Public item is chosen to formula (2) $Q_{2y}=\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="A20061013908900311.png,A20061013908900341.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="A20061013908900271.png,A20061013908900301.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2},$ $Q_{1y}=\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}\stackrel{\&OverBar;}{Q_0}$ (two variable functions postpone 120 °) and Q_3a=Q₃, Q_0a=Q₀(single argument postpones 120 °), carries out abbreviation and conversion, draws secondary excitation function S₃、R₃、S₂、R₂、S₁、R₁、S₀、R₀It is Q_1y、Q_2yAnd Q_3a、Q_0aAnd its non-function,

S₃=Q_2yQ_1y, ${\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="A20061013908900311.png,A20061013908900341.png"\; state="\{\{state\}\}">R</figure-callout>}}_3=\stackrel{\&OverBar;}{Q_{2y}}{Q}_{1y}---\left(3a\right)$

S₂=Q_3aQ_1y, ${\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="A20061013908900271.png,A20061013908900301.png"\; state="\{\{state\}\}">R</figure-callout>}}_2=\stackrel{\&OverBar;}{Q_{3a}}{Q}_{1y}---\left(3b\right)$

${\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">S</figure-callout>}}_1=\stackrel{\&OverBar;}{Q_{2y}}{Q}_{1y},$ ${\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">R</figure-callout>}}_1=\stackrel{\&OverBar;}{Q_{1y}}\stackrel{\&OverBar;}{Q_{0a}}---\left(3c\right)$

$S_0=\stackrel{\&OverBar;}{Q_{0a}},$ R₀=Q_0a    (3d)

3. write out primary excitation function.Consider $Q_{2y}=\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="A20061013908900311.png,A20061013908900341.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="A20061013908900271.png,A20061013908900301.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2},$ $Q_{1y}=\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}\stackrel{\&OverBar;}{Q_0}$ And Q_3a=Q₃, Q_0a=Q₀, convert them to primary excitation function S_3a、R_3a、S_2a、R_2a、S_0a、R_0a、S_1y、R_1y, they are Q₃、Q₂、Q₁And Q₀And its non-function, draw,

S_3a=Q₃, $R_{3a}=\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="A20061013908900311.png,A20061013908900341.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}---\left(4a\right)$

$S_{2y}=\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="A20061013908900271.png,A20061013908900301.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2}\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="A20061013908900311.png,A20061013908900341.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3},$ $R_{2y}=\stackrel{\&OverBar;}{S_{2y}}={\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="A20061013908900271.png,A20061013908900301.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2+Q_3---\left(4b\right)$

$S_{1y}=\stackrel{\&OverBar;}{Q_0}\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1},$ $R_{1y}=\stackrel{\&OverBar;}{S_{1y}}=Q_0+Q_1---\left(4c\right)$

S_0a=Q₀, $R_{0a}=\stackrel{\&OverBar;}{Q_0}---\left(4d\right)$

(clock is cp to the adiabatic latch of primary excitation₀) input meet Q according to formula (4)₃、Q₂、Q₁And Q₀And its it is non-, it is output as Q_3a、Q_2y、Q_1yAnd Q_0aAnd its it is non-, they are connected to main adiabatic latch according still further to formula (3), and (clock is cp₁And cp₂) each R and S input circuits in, main adiabatic latch is output as Q₃、Q₂、Q₁And Q₀And its it is non-.Q can be drawn by above formula (3) according to formula (1b)₃ ⁺、Q₂ ⁺、Q₁ ⁺And Q₀ ⁺, note：Q₃ ⁺、Q₂ ⁺、Q₁ ⁺And Q₀ ⁺It is main adiabatic latch output Q₃、Q₂、Q₁And Q₀Lower moment value, namely they carry out autonomous adiabatic same output ends of latch.The interior output for including the adiabatic latch of secondary excitation inside main adiabatic latch is designated as Q_3b、Q_2b、Q_1bAnd Q_0b。

4. drawing the adiabatic decimal subtraction counting circuit of two grades of excitations according to formula (3) and (4), show as schemed (16), the primary adiabatic latch number of excitation and main adiabatic latch number are by chance equal in figure, typically not necessarily equal.According to Adiabatic logic Flip-flop, then connected by formula (2), four pipes series connection (four variables of correspondence and item) must occur.And scheme (16) and eliminate four pipes series connection (four variables of correspondence and item), at most only two pipes series connection (two variables of correspondence and item), circuit a total of tubes is less slightly.If typically allowing most k pipes to connect using the adiabatic sequence circuit of Adiabatic logic Flip-flop, two grades are encouraged adiabatic sequence circuit by k²Pipe series connection (correspondence k²Variable and item) it is converted into k pipes series connection (corresponding k variables and item).

Figure 17 is Figure 16 Pspice computer simulation waveforms, and most upper one group is Q₃、Q₂、Q₁And Q₀Waveform, it is therefore seen that meeting decimal subtraction counting circuit relation；Second group is Q_3a、Q_2y、Q_1yAnd Q_0aWaveform, meets $Q_{2y}=\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="A20061013908900311.png,A20061013908900341.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="A20061013908900271.png,A20061013908900301.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2},$ $Q_{1y}=\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}\stackrel{\&OverBar;}{Q_0}$ And Q_3a=Q₃, Q_0a=Q₀(note：Numerical value is equal, but 120 ° of difference), the 3rd group is Q_3b、Q_2b、Q_1bAnd Q_0b(with Q₃、Q₂、Q₁And Q₀Waveform it is identical), the 3rd group is clock cp₂、cp₁And cp₀Waveform (sine wave), it is consistent with expected results.Figure 18 is clock cp₂、cp₁And cp₀Power consumption profile, is found out, clock cp by the most right flat of curve₂、cp₁And cp₀The effective power consumption for being output to decimal subtraction counting circuit is respectively 8.75 μ W, 10.75 μ W and 6.5 μ W, namely decade counter circuit effective power consumption is 8.75+10.75+6.5=26 μ W

The system counting circuit of thermal insulation 31 of (2) two grades of excitations.

31 system counting circuit Q₄Q₃Q₂Q₁Q₀State change be：00000 → 00001 → 00010 → 00011 → 00100 → 00101 → 00110 → 00111 → 01000 → 01001 → 01010 → 01011 → 01100 → 01101 → 01110 → 01111 → 10000 → 10001 → 10010 → 10011 → 10100 → 10101 → 10110 → 10111 → 11000 → 11001 → 11010 → 11011 → 11100 → 11101 → 11110 → 00000 ..., carry out successively as follows：

1. routinely drawn first using the method for designing of the sequence circuit of rest-set flip-flop：

S₄=Q₃Q₂Q₁Q₀, ${\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="A20061013908900241.png,A20061013908900331.png"\; state="\{\{state\}\}">R</figure-callout>}}_4=Q_3{Q}_2{Q}_1\stackrel{\&OverBar;}{Q_0}---\left(5a\right)$

${\mathrm{<figure-callout\; id="3"\; label="S"\; filenames="A20061013908900311.png,A20061013908900341.png"\; state="\{\{state\}\}">S</figure-callout>}}_3=\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="A20061013908900311.png,A20061013908900341.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}{Q}_2{Q}_1{Q}_0,$ R₃=Q₃Q₂Q₁(Q₄+Q₀)      (5b)

${\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="A20061013908900271.png,A20061013908900301.png"\; state="\{\{state\}\}">S</figure-callout>}}_2=\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="A20061013908900271.png,A20061013908900301.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2}{Q}_1{Q}_0,$ R₂=Q₂Q₁Q₀+Q₄Q₃Q₂Q₁    (5c)

${\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">S</figure-callout>}}_1=\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}{Q}_0,$ R₁=Q₁Q₀+Q₄Q₃Q₂Q₁      (5d)

$S_0=\stackrel{\&OverBar;}{Q_0}(\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="4"\; label="Q"\; filenames="A20061013908900241.png,A20061013908900331.png"\; state="\{\{state\}\}">Q</figure-callout>}}_4}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="A20061013908900311.png,A20061013908900341.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="A20061013908900271.png,A20061013908900301.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}),$ R₀=Q₀                 (5e)

2. then write out primary excitation function.Public item Q is chosen to formula (5)_3y=Q₃Q₂Q₁, Q_1y=Q₁Q₀(two variables and three-variable function postpone 120 °) and Q_4a=Q₄, Q_2a=Q₂, Q_0a=Q₀(single argument postpones 120 °), carries out abbreviation and conversion, draws secondary excitation function S₃、R₃、S₂、R₂、S₁、R₁、S₀、R₀It is Q_1y、Q_3yAnd Q_4a、Q_2a、Q_0aAnd its non-function, eliminate single argument Q with public item_3aAnd Q_a1Draw：

S₄=Q_3yQ_0a, ${\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="A20061013908900241.png,A20061013908900331.png"\; state="\{\{state\}\}">R</figure-callout>}}_4=Q_{3y}\stackrel{\&OverBar;}{Q_{0a}}---\left(6a\right)$

${\mathrm{<figure-callout\; id="3"\; label="S"\; filenames="A20061013908900311.png,A20061013908900341.png"\; state="\{\{state\}\}">S</figure-callout>}}_3=\stackrel{\&OverBar;}{Q_{3y}}{\mathrm{<figure-callout\; id="2a"\; label="Q"\; filenames="A20061013908900281.png"\; state="\{\{state\}\}">Q</figure-callout>}}_{2a}{Q}_{1y},$ R₃=Q_3y(Q_0a+Q_4a)   (6b)

${\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="A20061013908900271.png,A20061013908900301.png"\; state="\{\{state\}\}">S</figure-callout>}}_2=\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2a"\; label="Q"\; filenames="A20061013908900281.png"\; state="\{\{state\}\}">Q</figure-callout>}}_{2a}}{Q}_{1y},$ R₂=Q_2aQ_1y+Q_4aQ_3y  (6c)

${\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">S</figure-callout>}}_1=\stackrel{\&OverBar;}{Q_{1y}}{Q}_{0a},$ R₁=Q_1y+Q_4aQ_3y     (6d)

$S_0=\stackrel{\&OverBar;}{Q_{0a}}(\stackrel{\&OverBar;}{Q_{4a}}+\stackrel{\&OverBar;}{Q_{3y}}),$ R₀=Q_0a            (6e)

3. primary excitation function is write out again.Consider Q_3y=Q₃Q₂Q₁, Q_1y=Q₁Q₀And Q_4a=Q₄, Q_2a=Q₂, Q_0a=Q₀, convert them to primary excitation function S_4a、R_4a、S_2a、R_2a、S_0a、R_0aAnd S_3y、R_3y、S_1y、R_1y, be Q₄、Q₃、Q₂、Q₁And Q₀And its non-function, draw,

S_4a=Q₃, $R_{4a}=\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="A20061013908900311.png,A20061013908900341.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}---\left(7a\right)$

S_3y=Q₃Q₂Q₁, $R_{3y}=\stackrel{\&OverBar;}{S_{3{\mathrm{<figure-callout\; id="1"\; label="y"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">y</figure-callout>}}_1}}=(\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="A20061013908900311.png,A20061013908900341.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="A20061013908900271.png,A20061013908900301.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1})---\left(7b\right)$

S_2a=Q₂, ${\mathrm{<figure-callout\; id="2a"\; label="R"\; filenames="A20061013908900281.png"\; state="\{\{state\}\}">R</figure-callout>}}_{2a}=\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="A20061013908900271.png,A20061013908900301.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2}---\left(7c\right)$

S_1y=Q₁Q₀, $R_{1y}=\stackrel{\&OverBar;}{S_{1y}}=(\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="A20061013908900241.png,A20061013908900311.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}+\stackrel{\&OverBar;}{Q_0})---\left(7d\right)$

S_0a=Q₀, $R_{0a}=\stackrel{\&OverBar;}{Q_0}---\left(7e\right)$

Formula (6) and the variable of (7) subtractive (5) four and item (corresponding four pipe is connected), only ternary and item (corresponding three pipe is connected) and two variables and item (two pipes of correspondence connects), the primary input for encouraging thermal insulation latch meet Q₄、Q₃、Q₂、Q₁And Q₀And its it is non-, it is output as Q_4a、Q_3y、Q_2a、Q_1yAnd Q_0aAnd its it is non-, they are connected in R the and S input circuits of main adiabatic latch.Q can be drawn by above formula according to formula (1b)₄ ⁺、Q₃ ⁺、Q₂ ⁺、Q₁ ⁺And Q₀ ⁺, note：Q₄ ⁺、Q₃ ⁺、Q₂ ⁺、Q₁ ⁺And Q₀ ⁺It is main adiabatic latch output Q₄、Q₃、Q₂、Q₁And Q₀Lower moment value, namely they carry out autonomous adiabatic same output ends of latch.The output of the adiabatic latch of secondary excitation included in main adiabatic latch is designated as Q_4b、Q_3b、Q_2b、Q_b1And Q_0b。

4. drawing the system counting circuit of thermal insulation 31 of two grades of excitations according to formula (6) and (7), show as schemed (19), the primary adiabatic latch number of excitation and main adiabatic latch number are by chance equal in figure, typically not necessarily equal.Scheme (19) and eliminate four pipes series connection (four variables of correspondence and item), circuit a total of tubes is less slightly

Figure 20 is Figure 19 Pspice computer simulation waveforms, and most upper first group is Q₄、Q₃、Q₂、Q₁And Q₀Waveform, it is therefore seen that meet 31 system counting circuit relations；Second group is Q_4a、Q_3y、Q_2a、Q_1yAnd Q_0aWaveform, meets Q_3y=Q₃Q₂Q₁, Q_1y=Q₁Q₀, Q_4a=Q₄, Q_2a=Q₂, Q_0a=Q₀(note：Both members numerical value is equal, but 120 ° of difference), the 3rd group is Q_4b、Q_3b、Q_2b、Q_b1And Q_0b(with Q₄、Q₃、Q₂、Q₁And Q₀Waveform it is identical), the 3rd group is clock cp₂、cp₁And cp₀Waveform (nearly sine wave), it is completely the same with expected results.Figure 21 is clock cp₀、cp₁And cp₂Power consumption profile, is found out, clock cp by the most right flat of curve₀、cp₁And cp₂The effective power consumption for being output to 31 system counting circuits is respectively 8 μ W, 12.5 μ W and 10 μ W, namely 31 system counting circuit effective power consumptions are 8+12.5+10=30.5 μ W.

Embodiment 5：

The controllable three phase power clock generator circuit of the nearly sine of the adiabatic sequence circuit energy and the controllable three phase power clock generator circuit of nearly trapezoidal wave are provided, it is a kind of three-phase alternating current energy that the adiabatic sequence circuit is provided, its frequency can be controlled, by the clock pulses cp for being derived from crystal oscillator₄Determine.

(1) the three phase power clock generator circuit of nearly sine.

It is power clock cp to scheme (22)₂、cp₁And cp₀Generator circuit figure, the first half of figure is three-phase square-wave generator, including 6 NMOS tube (n₁、n₂、n₃、n₄、n₅、n₆) and 6 PMOS (p₁、p₂、p₃、p₄、p₅、p₆), wherein n₁And p₁, n₂And p₂, n₃And p₃Each three CMOS inverters of composition, and end to end by the form of circulation oscillator, but the source electrode of NMOS tube and PMOS each meets 6 control pipe n in three CMOS inverters₄And p₄, n₅And p₅, n₆And p₆Drain electrode, the grid of 6 control pipes all meets square wave cp₄, thus cp₄The frequency of control three phase power clock generator clock generator, and cp₄The square wave exported from quartz oscillator.The lower half of figure is waveform conversion and output circuit, by 3 PMOS (p₇、p₈、p₉), 3 transistor (Q_s0、Q_s1、Q_s2), 3 shunt-resonant circuit (L₀C₀、L₁C₁、L₂C₂) and 3 resistance (R₀、R₁、R₂) composition, square wave is converted to the power clock cp of nearly sine₂、cp₁And cp₀, and by three phase clock cp₂、cp₁And cp₀It is output to two grades of excitation adiabatic cmos sequence circuits.V in three-phase square-wave generator_C=-1.5V, V_CC=-3.0V, the nearly -1.5V of high level (1 level), the nearly -3.0V of low level (0 level).

The three-phase square-wave generator course of work：In square wave cp₄In the presence of, in addition to zero-time non-steady state, 3 output (Q_saQ_sbQ_sc) it is unlikely to be complete 1 (i.e. 111) and full 0 (i.e. 000).Work as cp₄When=1,3 NMOS tube (n₄、n₅、n₆) conducting, Q_saQ_sbQ_scFor 3 NMOS tube (n₁、n₂、n₃) grid, 3 pipe (n₁、n₂、n₃) can not there are two to simultaneously turn on, so Q_saQ_sbQ_sc≠ 111, actually work as cp₄Q when=1_saQ_sbQ_scThere can only be one 1.Work as cp₄When=0,3 PMOS (p₄、p₅、p₆) conducting, Q_saQ_sbQ_scFor 3 NMOS tube (p₁、p₂、p₃) grid, 3 pipe (p₁、p ₂、p₃) can not there are two to simultaneously turn on, so Q_saQ_sbQ_sc≠ 000, actually work as cp₄Q when=0_saQ_sbQ_scThere can only be one 0.

If present cp₄=0, Q_saQ_sbQ_sc=011, then change to cp₄=1, because of pipe n₃Grid Q_sb=1, pipe n₃Conducting, makes Q_sc=0, and make pipe n₁Cut-off, keeps Q_saQ_sb=01, namely Q_saQ_sbQ_scBy 011 → 010.Followed by it is changed into cp₄=1, because of pipe p₁Grid Q_sc=0, pipe p₁Conducting, makes Q_sa=1, and make pipe p₂Cut-off, keeps Q_sbQ_sc=10, namely Q_saQ_sbQ_scBy 010 → 110.Similar fashion analysis shows changing rule is：By Q from the point of view of from left to right circulating_saQ_sbQ_sc, 1. to cp₄=0, Q_saQ_sbQ_scThere are two 1, work as cp₄During by 0 → 1, Q_saQ_sbQ_scIn second 1 drop to 0, remaining is constant.2. cp is worked as₄When=1, Q_saQ_sbQ_scThere are two 0, cp₄During by 1 → 0, Q_saQ_sbQ_scIn second 0 be raised to 1, remaining is constant.Thus draw：With cp₄Change Q_saQ_sbQ_scBy 011 → 010 → 110 → 100 → 101 → 001 → 011, Q_sa、Q_sbAnd Q_scOutput is square wave, and their phase difference is 120 °.

Figure (23) is the computer simulation waveform of figure (22), and most upper first group is Q_sa、Q_sbAnd Q_scWaveform, second group is clock cp₂、cp₁And cp₀Waveform, the 3rd is clock cp₄Waveform, it is therefore seen that whenever cp₄Edge comes then, Q_saQ_sbQ_scChange, meets Q_saQ_sbQ_scBy 011 → 010 → 110 → 100 → 101 → 001 → 011 cyclically-varying rule, Q_sa、Q_sbAnd Q_scOutput is square wave, and their phase difference is 120 °.

Waveform changes the course of work with output circuit：Q_scThe square wave of output meets p₉Grid, control p₉Conducting and cut-off, subsequent controlling transistor Q_s0Base flow, Q_s0Colelctor electrode meet shunt-resonant circuit (L₂ C₂), the resonant frequency of the resonant tank is adjusted, makes itself and Q_scThe fundamental frequency of the square wave of output is approached, due to the effect of resonant tank, filters off harmonic components, retains fundamental wave component, as a result in Q_s0Colelctor electrode produce the output cp of nearly sinusoidal₀, export cp₀Peak-to-peak value be 3V (- 3V → 0V).V_C=-1.5V, V_CC=-3.0V, it is 1.5V to show direct-current working volts, obtains output of the amplitude for the three phase clock of 3.0V nearly sine.Similar mode is drawn：In Q_s1Colelctor electrode produce the output cp of nearly sinusoidal₁；In Q_s2Colelctor electrode produce the output cp of nearly sine₂, their phase difference is 120 °, and their cycle is cp₄Three times.

Find out from the Pspice computer simulation waveforms of figure (23), second group of clock cp₂、cp₁And cp₀Waveform be nearly sinusoidal, their phase difference is 120 °, and their cycle is cp₄Three times, meet expected require.Figure (24) is the power consumption profile of figure (22), and the first half of figure is the power consumption profile of three-phase square-wave generator；The lower half of figure (24) is the power consumption profile of waveform conversion and output circuit.Found out by scheming the most right flat of (24) curve, the effective power consumption of three-phase square-wave generator shown in the first half is 9 μ W, waveform shown in lower half changes the effective power consumption with output circuit into 860 μ W, namely the effective power consumption of the controllable three phase power clock generator circuit of nearly sinusoidal is 869 μ W.

(2) the controllable three phase power clock generator circuit of nearly trapezoidal wave.

Figure (25) is the controllable three phase power clock cp of nearly trapezoidal wave₂、cp₁And cp₀Generator circuit figure, the first half of figure is three-phase square-wave generator, including 6 NMOS tube (n₁、n₂、n₃、n₄、n₅、n₆) and 6 PMOS (p₁、p₂、p₃、p₄、p₅、p₆), its circuit is identical with the first half of figure (22)；The lower half of figure is waveform conversion and output circuit, by 3 PMOS (p₇、p₈、p₉), 3 NMOS tube (n₇、n₈、n₉) and 3 shunt-resonant circuit (L₀ C₀、L₁ C₁、L₂ C₂) composition, square wave is converted to the power clock cp of nearly trapezoidal wave₂、cp₁And cp₀, and the nearly three phase clock cp of trapezoidal wave₂、cp₁And cp₀It is output to two grades of excitation adiabatic cmos sequence circuits.Note：L₀、L₁And L₂It is larger, V in three-phase square-wave generator_C=-1.5V, V_CC=-3.0V, the nearly -1.5V of high level (1 level), the nearly -3.0V of low level (0 level).

The three-phase square-wave generator course of work is identical with the three-phase square-wave generator course of work shown in above-mentioned figure (22) first half, Q_sa、Q_sbAnd Q_scOutput is square wave, and their phase difference is 120 °.

Waveform changes the course of work with output circuit：Q_scThe square wave of output meets n₉Grid, control n₉Conducting and cut-off, n₉Drain electrode meet shunt-resonant circuit (L₂C₂), adjust L₂Make the resonant frequency of the resonant tank, make it below Q_scThe fundamental wave of the square wave of output, resonant frequency is close to a quarter fundamental frequency, in addition, there is 1 PMOS p₉Source electrode meet n₉Drain electrode, p₉Drain and gate meet V_C=-1.5V, due to the effect of resonant tank, in n₉Drain electrode produce the output cp of nearly trapezoidal wave₀.Similar mode is drawn：In n₈Drain electrode produce the output cp of nearly trapezoidal wave₁；In n₇Drain electrode produce the output cp of nearly trapezoidal wave₂.Export cp₂、cp₁And cp₀Peak-to-peak value be 3V (- 3V → 0V), their phase difference is 120 °, and their cycle is cp₄Three times.V_C=-1.5V, V_CC=-3.0V, it is 1.5V to show direct-current working volts, obtains output of the amplitude for the three phase clock of 3.0V nearly trapezoidal wave.

Find out from the Pspice computer simulation waveforms shown in figure (26), second group of clock cp₂、cp₁And cp₀Waveform be nearly trapezoidal wave, their phase difference is 120 °, and their cycle is cp₄Three times, meet expected require.Figure (27) is the power consumption profile of figure (25), and the lower half of figure is the power consumption profile of three-phase square-wave generator；The first half of figure (27) is the power consumption profile of waveform conversion and output circuit.Found out by scheming the most right flat of (27) curve, waveform shown in the first half changes the effective power consumption with output circuit into 387 μ W, the effective power consumption of controllable three-phase square-wave generator shown in lower half is 9 μ W, namely the effective power consumption of the controllable three phase power clock generator circuit of nearly trapezoidal wave is 396 μ W.

By the output cp of Figure 25 nearly trapezoidal waves produced₂、cp₁And cp₀Three clock ends of the system counting circuit of thermal insulation 31 for two grades of excitations being connected to shown in Figure 19, carry out Pspice computer simulations, draw the computer simulation waveform shown in Figure 28, most upper first group of Figure 28 is Q₄、Q₃、Q₂、Q₁And Q₀Waveform, it is therefore seen that, meet 31 system counting circuit relations；Second group is Q_4b、Q_3b、Q_2b、Q_b1And Q_0b(with Q₄、Q₃、Q₂、Q₁And Q₀Waveform it is identical), the 3rd group is Q_4a、Q_3y、Q_2a、Q_1yAnd Q_0aWaveform, meets Q_3y=Q₃Q₂Q₁, Q_1y=Q₁Q₀, Q_4a=Q₄, Q_2a=Q₂, Q_0a=Q₀(note：Both members numerical value is equal, but 120 ° of difference), the 4th group is clock cp₂、cp₁And cp₀Waveform (nearly trapezoidal wave), it is consistent with expected results.Figure 29 is clock cp₀、cp₁And cp₂Power consumption profile, is found out, clock cp by the most right flat of curve₀、cp₁And cp₂The effective power consumption for being output to 31 system counting circuits is respectively 11.5 μ W, 16.5 μ W and 16.25 μ W, namely 31 system counting circuit effective power consumptions are 11.5+16.5+16.25=45 μ W.

Embodiment 6：

One, three phase power clocks in adiabatic sequence circuit are best selections.

Adiabatic latch and adiabatic combinational circuit are powered with the power clock of multiple alternations in adiabatic sequence circuit, if the absolute value delta V of the voltages of clock pulses cp relatively_cpBe 0 () arrive V_mBetween change, under cp impulse actions, whether positive pulse or negative pulse, it is necessary to by ' reception ', ' storage ', ' recovery ' and ' stopping ' four-stage (' forward position ', ' duration ', ' after edge ' and ' stand-down ' that corresponds to cp pulses).This four-stage is also all had to pass through to the power clock cp of the nonideal alternation of waveform：1. ' rest stage ' refers to the absolute value delta V of the voltages of cp relatively_cpClose to 0, the operating voltage of i.e. this grade adiabatic circuits (including corresponding MOS controls door) is close to 0, because control door exports current potential close to 0, the change that prime is connected to control door input will not make control door output larger jump in potential occur, (if control door is a metal-oxide-semiconductor, the then drain electrode of pipe and source electrode potential V_DSClose to 0, grid voltage V_GChange will not cause control pipe V_DSJump in potential or saltus step are minimum；And other stage V_DSKeep off 0, V_GChange will likely cause V_DSThe larger saltus step of current potential, increases nonadiabatic power consumption).Stop time is designated as t_s.2. ' memory phase ' refers to Δ V_cpClose to V_m, adiabatic circuits (including corresponding MOS controls door) are under normal working voltage, the information stability stored, and can externally produce stable output, and interference-free influence.Storage time is designated as t_h.3. ' receive the stage ' and refer to Δ V_cpBy nearly 0 to nearly V_m, namely Δ V_cpAscending increase process, adiabatic circuits from ' stopping ' to ' storage ' transition, any information stored and depends on control door input voltage (control pipe gate input voltage) for adiabatic circuits after the completion of transition.The reception time is designated as t_c.4. ' Restoration stage ' refers to Δ V_cpBy nearly V_mTo nearly 0, namely Δ V_cpDescending decline process, adiabatic circuits from ' storage ' to ' stopping ' transition.Recovery time is designated as t_r.Clock cycle T=t_c+t_h+t_r+t_s。

If adiabatic memory circuit has multiple clock cp₀、cp₁、cp₂…cp_kEffect, is applied to 0 grade of adiabatic circuits, 1 grade of adiabatic circuits, 2 grades of adiabatic circuits ..., k grades of adiabatic circuits respectively.0 grade of adiabatic circuits output termination, 1 grade of adiabatic circuits control door, 1 grade of adiabatic circuits output termination, 2 grades of adiabatic circuits control doors ..., 0 grade of adiabatic circuits control door of k grades of adiabatic circuits output terminations.Arbitrary number of level adiabatic circuits will meet adiabatic condition in ' reception ', ' storage ', ' recovery ' of this grade and ' stopping ' four stage, also meet stability condition.Adiabatic condition requires the voltage nearly 0 of the interpolar of source and drain two during metal-oxide-semiconductor conducting, and no jump in potential or saltus step are minimum, so that metal-oxide-semiconductor micro power consumption (nearly 0)；If conversely, not nearly 0 (or larger) of the voltage of the interpolar of metal-oxide-semiconductor source and drain two, metal-oxide-semiconductor conducting resistance will produce larger nonadiabatic power consumption.

1. adiabatic condition requirement：If this grade of adiabatic circuits (such as 1 grade adiabatic circuits) is in ' receiving the stage ', it is required that subordinate's adiabatic circuits (such as 2 grades adiabatic circuits) are in ' rest stage '.Because at this moment the operating voltage of subordinate's adiabatic circuits is close to 0 (corresponding MOS controls door operating voltage close to 0), this grade of adiabatic circuits will not make subordinate's adiabatic circuits control door output larger jump in potential (minimum i.e. without jump in potential or saltus step, so that metal-oxide-semiconductor micro power consumption) occur in ' receiving the stage ' output end voltage change.

2. stability condition requirement：If this grade of adiabatic circuits (such as 1 grade adiabatic circuits) is in ' receiving the stage ', it is required that prime adiabatic circuits (such as 0 grade adiabatic circuits) are in ' memory phase '.Because the input of this grade of adiabatic circuits control door is exported from prime adiabatic circuits, the information stability that only prime adiabatic circuits are stored, and can externally produce stable output, interference-free influence just can guarantee that the reliable receive information of this grade of adiabatic circuits.

The doubleclocking of theorem 1. thermal insulation memory circuit is unsatisfactory for adiabatic condition and stability condition requirement.Three clocks thermal insulation memory circuit is a best selection.

Card：If doubleclocking is cp₀And cp₁, cp₀Connect 0 grade of adiabatic circuits, cp₁Connect 1 grade of adiabatic circuits.Required according to stability condition：If 1 grade of adiabatic circuits is in ' receiving the stage ', it is required that 0 grade of adiabatic circuits is in ' memory phase '.Further according to adiabatic condition requirement：If 1 grade of adiabatic circuits is in ' receiving the stage ', it is required that 0 grade of adiabatic circuits is in ' rest stage ' (because subordinate's level adiabatic circuits of 1 grade of adiabatic circuits are exactly 0 grade of adiabatic circuits).It is disjoint to 0 grade of adiabatic circuits ' memory phase ' and ' rest stage ', ' receiving the stage ' of 1 grade of adiabatic circuits can not possibly be in ' memory phase ' of 0 grade of adiabatic circuits, ' rest stage ' of 0 grade of adiabatic circuits is in again, so the requirement of adiabatic condition and stability condition can not be met simultaneously.

As can be seen here, the adiabatic memory circuit of doubleclocking is not a good selection；Clock number >=3 of the requirement of adiabatic condition and stability condition can be met simultaneously.Three clocks thermal insulation memory circuit is a best selection, can meet the requirement of adiabatic condition and stability condition simultaneously if Figure 30.Though four clocks thermal insulation memory circuit can meet the requirement of adiabatic condition and stability condition, clock number ＞ 3, corresponding adiabatic circuits and many one-levels simultaneously, not as the adiabatic memory circuit of three clocks.

Effectively dissipation power P in the two, present invention_effCalculate and simulation test.For bipolar circuitry and MOS circuits, there is nonlinear parameter in semiconductor devices (device resistance and capacitance are the functions of voltage or electric current), Laplace transformation, principle of stacking and Dai Weinan principles have failed, integrated circuit dissipation power computing formula is difficult to release, both release is made, there is also very big approximate.It can be released according to blanket law of conservation of energy, law of conservation of energy is all set up under any circumstance, not by by non-linear effects.The micropower for being sent to circuit by power supply in infinitely small time interval dt is V (t) I (t) dt, V (t) is power output end voltage, I (t) is electric power outputting current, and I (t) ＞ 0 represent that instantaneous power is sent to circuit by power supply in dt, I (t) ＜ 0 represent that instantaneous power returns to power supply by circuit in dt, thus releases effective dissipation power P_effComputing formula is expressed as follows：

$P_{\mathrm{eff}}=\frac{1}{\mathrm{KT}}{\&Integral;}_0^{\mathrm{KT}}V\left(t\right)I\left(t\right)\mathrm{dt}---\left(9\right)$

Formula (9) has broad applicability, it is not necessary to program, and is directly measured with function AVG ().Generally there is larger starting power consumption, to make the influence of starting power consumption close to 0 (or reaching in the error range that reading allows), can use very big t=KT, curve is most right to tend to be flat, very convenient in flat reading.

Claims (5)

1. a kind of adiabatic latch, a shared adiabatic latch of three-level：Basic thermal insulation latch, the adiabatic latch of secondary excitation and the adiabatic latch of primary excitation, it is characterized in that：Per one-level, adiabatic latch is realized comprising the adiabatic combinational circuit of one-level, and described adiabatic latch is made up of the adiabatic phase inverter kernel of three pipes and two control doors；The adiabatic phase inverter kernel of three described pipes：A PMOS p in three pipes₁Source ground be 0 current potential, two NMOS tube n₁And n₂Source electrode meet clock cp and bear alternation current potential, p₁Drain electrode and n₁Drain electrode and n₂Grid be connected to Q jointly_rOutput end, p₁Grid and n₁Grid and n₂Drain electrode be connected to jointly Output end, Q_rWith the indirect control pipe p on ground₃I.e. simplest S controls door, p₃Grid connect control signal

With the indirect control pipe p on ground₂I.e. simplest R controls door, p₂Grid connect control signal RS=0 is met, that is, meets p₂And p₃Two pipes are not simultaneously turned on, p during S=1₃Pipe is turned on, p during R=1₂Pipe is turned on, generally control pipe p₂And p₃The connection in series-parallel combination of multiple PMOS control pipes is changed to, that is, is changed to control door, p₃It is changed to S control doors, p₂It is changed to R control doors, it is exactly to meet S to control door and R control doors not to simultaneously turn on to meet RS=0, S control doors are each connected by S logical formulas and R logical formulas and R controls the series parallel structure of door, wherein logic add+be connected in parallel connection, logic multiply is to connect series connection, and negated by variable and connect input control signal, i.e., because of PMOS control pipes low level effectively, there is difference for 120 ° of three clock cp₀、cp₁And cp₂, it is primary to encourage adiabatic latch to meet clock cp₀, it is secondary to encourage adiabatic latch to meet clock cp₁, basic thermal insulation latch meets clock cp₂, three-level thermal insulation flip-latch circuit structure is identical, and described control door be the control by adiabatic sequence circuit requirement.

2. adiabatic latch according to claim 1, it is characterized in that：The adiabatic latch of described three-level：Basic thermal insulation latch, the adiabatic latch of secondary excitation and the adiabatic latch of primary excitation, one be output as Q andBasic thermal insulation latch L_QIt is a control pipe p using simplest S control doors₃It is a control pipe p with simplest R control doors₂；One is output as Q_bWith

The adiabatic latch L of secondary excitation_QbControl door and general R to control door using general S, work as p₃Grid connect

And p₂Grid meet Q_bWhen, by the basic adiabatic latch L_QWith the adiabatic latch L of secondary excitation_QbA main adiabatic latch is merged into, described main adiabatic latch meets described clock cp₁And cp₂, wherein L_QbMeet described clock cp₁, L_QMeet described clock cp₂, usually add a PMOS p₁₀, pipe p₁₀Grid meet Q_b, source electrode and drain electrode connect respectively

And ground.

3. a kind of application of above-mentioned adiabatic latch in the adiabatic cmos sequence circuit without insulated door.

4. application of the adiabatic latch according to claim 3 in the adiabatic cmos sequence circuit without insulated door, it is characterized in that：The adiabatic decimal subtraction counting circuit of two grades of excitations is constituted with described adiabatic latch entirely, in addition to adiabatic latch, without any insulated door, 4 primary adiabatic latch control door S of excitation_3a、R_3a、S_2y、R_2y、S_1y、R_1y、S_0a、R_0aInput meet main adiabatic latch output Q₃、Q₂、Q₁And Q₀And its it is non-, but corresponding PMOS grid is connected afterwards by "+for parallel connection, for series connection, variable negates "；S_3aIt is single tube to control door, and grid connects

R_3aIt is single tube to control door, and grid meets Q₃；S_0aIt is single tube to control door, and grid connects

R_0aIt is single tube to control door, and grid meets Q₀；S_2yDoor is controlled to be connected for 2 pipes, 2 tube grids meet Q respectively₂And Q₃；R_2yControl door in parallel for 2 pipes, 2 tube grids connect respectively

With

S_1yDoor is controlled to be connected for 2 pipes, 2 tube grids meet Q respectively₀And Q₁；R_1yControl door in parallel for 2 pipes, 2 tube grids connect respectively With

4 main adiabatic latch control door S₃、R₃、S₂、R₂、S₁、R₁、S₀、R₀Input meet the adiabatic latch output Q of primary excitation_3a、Q_2y、Q_1yAnd Q_0aAnd its it is non-, but to be negated by variable and be followed by corresponding PMOS grid：S₃Door is controlled to be connected for 2 pipes, 2 tube grids connect respectively

With

R₃Door is controlled to be connected for 2 pipes, 2 tube grids meet Q respectively_2yWith

S₀It is single tube to control door, and grid meets Q_0a；R₀It is single tube to control door, and grid connects

S₂Door is controlled to be connected for 2 pipes, 2 tube grids connect respectively

With

R₂Door is controlled to be connected for 2 pipes, 2 tube grids meet Q respectively_3aWith

S₁Door is controlled to be connected for 2 pipes, 2 tube grids meet Q respectively_2yWith

R₁Control door in parallel for 2 pipes, 2 tube grids meet Q respectively_1yAnd Q_0a。

5. application of the adiabatic latch according to claim 3 in the adiabatic cmos sequence circuit without insulated door, it is characterized in that：The system counting circuit of thermal insulation 31 of two grades of excitations is constituted with described adiabatic latch entirely, in addition to adiabatic latch, without any insulated door, 5 primary adiabatic latch control door S of excitation_4a、R_4a、S_3y、R_3y、S_2a、R_2a、S_1y、R_1y、S_0a、R_0aInput meet main adiabatic latch output Q₄、Q₃、Q₂、Q₁And Q₀And its it is non-, but to connect corresponding PMOS by "+for parallel connection, for series connection, variable negates " mode：S_4aIt is single tube to control door, and grid connects

R_4aIt is single tube to control door, and grid meets Q₃；S_2aIt is single tube to control door, and grid connects

R_2aIt is single tube to control door, and grid meets Q₂；S_0aIt is single tube to control door, and grid connects

R_0aIt is single tube to control door, and grid meets Q₀；S_3yDoor is controlled to be connected for 3 pipes, 3 tube grids connect respectively

With

R_3yControl door in parallel for 3 pipes, 3 tube grids meet Q respectively₃、Q₂And Q₁；S_1yDoor is controlled to be connected for 2 pipes, 2 tube grids connect respectively

With R_1yControl door in parallel for 2 pipes, 2 tube grids meet Q respectively₀And Q₁；5 main adiabatic latch control door S₄、R₄、S₃、R₃、S₂、R₂、S₁、R₁、S₀、R₀Input meet the adiabatic latch output Q of primary excitation_4a、Q_3y、Q_2a、Q_1yAnd Q_0aAnd its it is non-, but to be negated by variable and be followed by corresponding PMOS grid：S₄Door is controlled to be connected for 2 pipes, 2 tube grids connect respectively With

R₄Door is controlled to be connected for 2 pipes, 2 tube grids connect respectively And Q_0a；S₃Door is controlled to be connected for 3 pipes, 3 tube grids meet Q respectively_3y,

With

R₃Control door to be connected again with single tube after the parallel connection of 2 pipes, 2 tube grids in parallel connect respectively With

Series Sheet tube grid connects S₂Door is controlled to be connected for 2 pipes, 2 tube grids meet Q respectively_2aWith

R₂It is the series connection of simultaneously 2 pipes of di- to control door, and the grid of 2 pipes of series connection connects respectively

With

The grid of another 2 pipe of series connection connects respectively With

S₁Door is controlled to be connected for 2 pipes, 2 tube grids meet Q respectively_1yWith

R₁Door is controlled for, again with single tube parallel connection, 2 tube grids of connecting connect respectively after the series connection of 2 pipes With

Single tube grid connects

S₀Control door to be connected again with single tube after the parallel connection of 2 pipes, 2 tube grids in parallel meet Q respectively_4aAnd Q_3y, Series Sheet tube grid meets Q_0a；R₀It is single tube to control door, and grid connects

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