CN101071404A - Small-capacity FIFO storage device data-moving trigger and method - Google Patents
Small-capacity FIFO storage device data-moving trigger and method Download PDFInfo
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Abstract
The invention discloses small-capacity FIFO memory data transfer triggering devices and methods. The device used to generate interrupt source and sent to processors, the interrupt source in the first conditions for the establishment of a trigger interrupt data transfer, for the conditions referred to in the first small-capacity FIFO memory there are at least equivalent period in the small-capacity FIFO memory depth of half of the new data into. The invention of the small-capacity FIFO memory data transfer triggering devices and methods, only small-capacity FIFO memory into the equivalent of at least half of its depth when new data triggered DMA data transfer, so each time the trigger DMA data transfer are effective, and avoid the misuse of existing technologies because of the trigger lead to data errors, improve system stability and reliability, at the same time is simple.
Description
Technical field
The data buffering that the present invention relates to FIFO (First Input First Output, first-in first-out) storer, particularly small-capacity FIFO storage is moved technology.
Background technology
In system for real-time signal processing, use small-capacity FIFO storage, cooperate respective logic, utilize Event triggered DMA (Direct Memory Access, the direct memory storage) mechanism is with (can be outside the sheet or on-chip memory) in the high-speed memory of data-moving in processor subsystem.The small-capacity FIFO storage of mentioning in presents is the small-capacity FIFO storage of capacity less than the size of a full block of data, simultaneously, describes for convenient, in presents, this full block of data is called frame data.
Because the each only moving data block size of processor equals the small-capacity FIFO storage capacity half, therefore frame data need repeatedly be moved realization.
Aforesaid way can be used for terminal and Node B (base station), RNC (Radio NetworkController, radio network controller), CN (Core Network, core net) and the processor data in other systems receives and send the data occasion, also can in SoC (System on a Chip, SOC (system on a chip)) system, realize.
As shown in Figure 1, in the existing DMA data-moving technology based on small-capacity FIFO storage, the capacity of small-capacity FIFO storage 100 is less than the size of frame data, and the each moving data block size of processor equals half of small-capacity FIFO storage capacity.
As shown in Figure 1, wherein, fifo_wdata, fifo_wen (effectively high), fifo_wclk are respectively writing data bus, writing and enable and write clock of small-capacity FIFO storage 100, write data by data source 200 controls; Fifo_rdata, fifo_ren (effectively high), fifo_rclk be respectively small-capacity FIFO storage 100 read data bus, read to enable and read clock, by processor 300 control sense datas; Reset is a systematic reset signal; Fifo_hf is the half-full sign of small-capacity FIFO storage 100, effectively low, be the interrupt source that sends to the triggering DMA data-moving of processor, it is effective to be configured to negative edge, when storage in the small-capacity FIFO storage 100 is equal to or greater than the data of half degree of depth, be in effective status, trigger the DMA data-moving that data block size of processor startup equals half capacity of small-capacity FIFO storage.
Yet the priority of DMA data-moving is lower, and the process of moving may be interrupted, and with follow-up biography.Therefore there is this possibility: in DMA data-moving process, at next block size of data source is that the data of half capacity of small-capacity FIFO storage are not also moved when finishing, the half-full sign of small-capacity FIFO storage becomes low level effective status by the disarmed state of high level, therefore cause the false triggering of a DMA data-moving, cause error in data.
Above-mentioned shortcoming can clearly see that the degree of depth of supposition small-capacity FIFO storage is 32 among Fig. 2 from the simulation waveform of Fig. 2, and fifo_read_counter counts each processor DMA data-moving.Under the triggering of the fifo_hf negative edge first time, processor starts DMA and begins to move 16 data (half of the small-capacity FIFO storage degree of depth).In the processor moving data, data source still has data to write.Interval in the middle of DMA, half-full situation has appearred equaling or exceeding in small-capacity FIFO storage, and promptly negative edge has for the second time appearred in fifo_hf.At this moment, the new data that do not equal or exceed half depth number of small-capacity FIFO storage write, and therefore the DMA data-moving that triggers this moment interrupts and will lead to errors.Show that really the moment that the new data that equal half depth number of small-capacity FIFO storage write should be the 3rd negative edge of fifo_hf.
Summary of the invention
The object of the present invention is to provide a kind of device data-moving trigger and method of small-capacity FIFO storage, the data-moving that makes small-capacity FIFO storage has only write at small-capacity FIFO storage and has just carried out the DMA data-moving when being equivalent to half new data of its degree of depth at least, the error in data of avoiding false triggering of the prior art to cause, the stability and the reliability of raising system.
To achieve these goals, the invention provides a kind of device data-moving trigger of small-capacity FIFO storage, be used to produce interrupt source and send to processor, wherein, described interrupt source is used for producing the interruption that trigger data is moved when first condition is set up, and described first condition is to have at least the new data of half degree of depth that is equivalent to described small-capacity FIFO storage to write in the described small-capacity FIFO storage.
Above-mentioned device, wherein, described data-moving is a direct memory storage data-moving.
Above-mentioned device wherein, specifically comprises:
Write the data judgment means, be used to judge whether first condition is set up;
Interrupt generation device, be used to produce described interrupt source and send to described processor, described interrupt source is used for producing described interruption when said write data judgment means is judged described first condition and set up.
Above-mentioned device, wherein, said write data judgment means is a counter, described counter possesses half the state of cycling jump that number is the depth value of described small-capacity FIFO storage, when an effective small-capacity FIFO storage number of write access operations, described counter jumps to next state, and described counter is judged described first condition establishment when last state jumps to first state.
Above-mentioned device, wherein, when second condition and the 3rd condition were set up simultaneously, described first condition was set up; Described second condition is: after the system reset, described processor is reading of data from described small-capacity FIFO storage not, or last trigger finish after, described processor has read half data of the described small-capacity FIFO storage degree of depth from described small-capacity FIFO storage, described the 3rd condition is that the half-full sign of described small-capacity FIFO storage is effective.
Above-mentioned device wherein, comprising:
The reading and writing data judgment means is used to judge whether second condition and the 3rd condition are set up simultaneously;
Interrupt generation device, be used to produce described interrupt source and send to described processor, described interrupt source is used for judging in described reading and writing data judgment means and produces described interruption when described second condition and the 3rd condition are set up simultaneously.
Above-mentioned device, wherein, described reading and writing data judgment means comprises a counter, described counter possesses half the state of cycling jump that number is the depth value of described small-capacity FIFO storage, when an effective small-capacity FIFO storage read access is operated, described counter jumps to next state, judges described second condition establishment when described counter is in first state.
In order better to realize above-mentioned purpose, the present invention also provides a kind of data-moving triggering method of small-capacity FIFO storage, device data-moving trigger by small-capacity FIFO storage produces interrupt source and sends to processor, wherein, described interrupt source produces the interruption that trigger data is moved when first condition is set up, described first condition is to have at least the new data of half degree of depth that is equivalent to described small-capacity FIFO storage to write in the described small-capacity FIFO storage.
Above-mentioned method, wherein, described data-moving is a direct memory storage data-moving.
Above-mentioned method, wherein, the device data-moving trigger of described small-capacity FIFO storage comprises a counter, described counter possesses half the state of cycling jump that number is the depth value of described small-capacity FIFO storage, when an effective small-capacity FIFO storage read access is operated, described counter jumps to next state, judges described second condition establishment when described counter is in first state.
Above-mentioned method, wherein, described processor has read half of the described small-capacity FIFO storage degree of depth or 0 times data from described small-capacity FIFO storage, and the half-full sign of described small-capacity FIFO storage is when effective, and described first condition is set up.
Above-mentioned method, wherein, when second condition and the 3rd condition were set up simultaneously, described first condition was set up; Described second condition is: after the system reset, described processor is reading of data from described small-capacity FIFO storage not, or last trigger finish after, described processor has read half data of the described small-capacity FIFO storage degree of depth from described small-capacity FIFO storage, described the 3rd condition is that the half-full sign of described small-capacity FIFO storage is effective.
Above-mentioned method, wherein, the device data-moving trigger of described small-capacity FIFO storage comprises a counter, described counter possesses half the state of cycling jump that number is the depth value of described small-capacity FIFO storage, when an effective small-capacity FIFO storage read access is operated, described counter jumps to next state, judges described second condition establishment when described counter is in first state.
The device data-moving trigger of small-capacity FIFO storage of the present invention and method, by condition is set, only write and just triggered the DMA data-moving when being equivalent to half new data of its degree of depth at least at small-capacity FIFO storage, therefore, the triggering of each DMA data-moving all is effectively, has avoided in the prior art because the error in data that false triggering causes, the stability and the reliability of system have been improved, simultaneously, amount of logic is very little, realizes simple.
Description of drawings
Fig. 1 is the synoptic diagram of small-capacity FIFO storage;
The emulation synoptic diagram that Fig. 2 makes mistakes for the DMA data-moving of existing small-capacity FIFO storage;
Fig. 3 is the synoptic diagram of first embodiment of DMA device data-moving trigger of the present invention;
Fig. 4 is the synoptic diagram of second embodiment of DMA device data-moving trigger of the present invention;
Fig. 5 is the emulation synoptic diagram that utilizes the DMA data-moving of the FIFO storer behind the present invention.
Embodiment
In the DMA device data-moving trigger and method of small-capacity FIFO storage of the present invention, only in small-capacity FIFO storage, have at least half new data of the degree of depth that is equivalent to small-capacity FIFO storage to write the fashionable DMA data-moving that just triggers.
First embodiment of the DMA device data-moving trigger of small-capacity FIFO storage of the present invention as shown in Figure 3, small-capacity FIFO storage 100 is as the metadata cache between data source 200 and the processor 300, and the data that DMA device data-moving trigger 400 is used for writing according to data source produce the interruption that triggers the DMA data-moving.
In the first embodiment of the present invention, DMA device data-moving trigger 400 comprises that one writes a data judgment means and an interruption generation device, wherein:
Write the data judgment means, half the new data that is used to judge whether to be equivalent to the degree of depth of small-capacity FIFO storage writes small-capacity FIFO storage;
Interrupt generation device, be used to produce interrupt source and send to processor, this interrupt source can produce the interruption that triggers the DMA data-moving when writing the data judgment means and judge half new data of the degree of depth that is equivalent to small-capacity FIFO storage and write small-capacity FIFO storage;
As shown in Figure 3, in the first embodiment of the present invention, DMA device data-moving trigger 400 be input as fifo_wclk, fifo_wen and reset, be output as the interrupt source Int2processor that sends to processor 300, when this interrupt source Int2processor writes small-capacity FIFO storage at half the new data that the degree of depth that is equivalent to small-capacity FIFO storage is arranged, can produce the interruption that triggers the DMA data-moving.
The small-capacity FIFO storage data-moving triggering method of the foregoing description correspondence comprises the steps:
Step 11, system reset, small-capacity FIFO storage begins to receive the data that data source sends;
Step 12 writes half the new data that the data judgment means judges whether to be equivalent to the degree of depth of small-capacity FIFO storage and writes, if enter step 13, continues to judge otherwise return step 12;
Step 13 is interrupted generation device and is produced the interruption that triggers the DMA data-moving, and sends to processor, returns step 12.
Because processor 300 will interrupt the interruption that the interruption of generation device generation is set at the DMA data-moving of Event triggered, therefore in receiving this, have no progeny and trigger the DMA data-moving, move the data that are equivalent to small-capacity FIFO storage 100 half degree of depth from small-capacity FIFO storage.
As shown in Figure 3, fifo_wdata, fifo_wen (effectively high), fifo_wclk are respectively writing data bus, writing and enable and write clock of small-capacity FIFO storage 100, write data by data source 200 controls; Fifo_rdata, fifo_ren (effectively high), fifo_rclk be respectively small-capacity FIFO storage 100 read data bus, read to enable and read clock, by processor 300 control sense datas; Reset is a systematic reset signal; Int2processor is the interrupt source of interruption that sends to the triggering DMA data-moving of processor 300.
The above-mentioned data judgment means that writes can be a counter, and it possesses half the state of cycling jump that number is the degree of depth of small-capacity FIFO storage 100, is 2 as the degree of depth of small-capacity FIFO storage
N+1, then counter possesses 2
NThe state of individual cycling jump is first state as the counter current state, and next redirect status indication is second state, and the rest may be inferred, state to the last, promptly the 2nd
NIndividual state;
Simultaneously, when systematic reset signal is effective, this counter is first state, when reset mode is invalid, next redirect status indication is second state, this reset mode is a unique state, different with other states, this counter is according to fifo_wclk, ffo_wen judges whether that new data write, at the rising edge of fifo_wclk, if fifo_wen is the high level effective status, show effective small-capacity FIFO storage 100 number of write access operations are arranged, counter jumps to next state, and when receiving the new data that is equivalent to small-capacity FIFO storage 100 half degree of depth in the small-capacity FIFO storage 100, counter is from the 2nd
NIndividual state jumps to first state;
Interrupt generation device at counter from the 2nd
NProduce the interruption that triggers the DMA data-moving when individual state jumps to first state, and send to processor 300.
Because processor 300 will interrupt the interruption that the interruption of generation device generation is set at the DMA data-moving of Event triggered, therefore in receiving this, have no progeny and trigger the DMA data-moving, move the data that are equivalent to small-capacity FIFO storage 100 half degree of depth from small-capacity FIFO storage.
As shown in Figure 3, this interruption generation device produces an Int2processor, and this Int2processor and if only if counter is from the 2nd simultaneously
NWhen individual state variation arrived first state, Int2processor was " 1 ", and under other situations, Int2processor is " 0 ".Simultaneously Int2processor is set to interrupt source in the processor configuration, and it is effective to set rising edge simultaneously, therefore whenever counter from the 2nd
NWhen individual state variation arrives first state, Int2processor jumps to " 1 " from " 0 ", produce and interrupt, so the corresponding triggering DMA data-moving of processor meeting, move the data that are equivalent to small-capacity FIFO storage 100 half degree of depth from small-capacity FIFO storage.
Certainly, Int2processor also can be that and if only if counter is during from 2N state variation to first state, and Int2processor is " 0 ", under other situations, Int2processor is " 1 ", but should be that negative edge is effective this moment in the processor configuration.
Second embodiment of the DMA device data-moving trigger of small-capacity FIFO storage of the present invention as shown in Figure 4, small-capacity FIFO storage 100 is as the metadata cache between data source 200 and the processor 300, and data and fifo_hf that DMA device data-moving trigger 400 ' is used for reading according to processor produce the interruption that triggers the DMA data-moving.
As shown in Figure 4, in the second embodiment of the present invention, DMA device data-moving trigger 400 ' be input as fifo_rclk, fifo_ren, fifo_hf and reset, be output as and send to the interrupt source Int2processor that processor 300 triggers the DMA data-movings.
In the second embodiment of the present invention, DMA device data-moving trigger 400 ' comprises a reading and writing data judgment means and an interruption generation device, wherein:
The reading of data judgment means is used to judge whether following two kinds of situations are set up:
After the system reset, processor is reading of data from small-capacity FIFO storage not, and fifo_hf is effective simultaneously;
Last once trigger finish after, processor has read the data for half of the small-capacity FIFO storage degree of depth from small-capacity FIFO storage, fifo_hf is effective simultaneously.
Interrupt generation device, be used to produce interrupt source and send to processor, this interrupt source can produce the interruption that triggers the DMA data-moving when the reading of data judgment means has been judged any situation and set up.
After system reset, small-capacity FIFO storage 100 is in full dummy status, data source begins to send data than slow rate (with respect to the frequency of operation of processor), when fifo_hf is effective, but processor does not have reading of data, show half the new data that has the degree of depth that is equivalent to small-capacity FIFO storage in the small-capacity FIFO storage at least, need to generate an interruption and trigger the DMA data-movings for processor 300;
Last once trigger finish after, if processor 300 has read half data of the degree of depth that is equivalent to small-capacity FIFO storage 100 from small-capacity FIFO storage 100 after, fifo_hf is also effective, also show half the new data that has the degree of depth that is equivalent to small-capacity FIFO storage 100 in the small-capacity FIFO storage at least, therefore also need to generate an interruption this moment and trigger the DMA data-movings for processor 300.
As shown in Figure 4, in the second embodiment of the present invention, DMA device data-moving trigger 400 ' be input as fifo_ren, fifo_rclk, fifo_hf and reset, be output as the interrupt source Int2processor that sends to processor 300, this interrupt source Int2processor judges in the reading of data judgment means and produces the interruption that triggers the DMA data-moving when following situation is set up:
After the system reset, processor has read from small-capacity FIFO storage and has been 0 times data of the small-capacity FIFO storage degree of depth, and fifo_hf is effective simultaneously;
Last once trigger finish after, processor has read the data for half of the small-capacity FIFO storage degree of depth from small-capacity FIFO storage, fifo_hf is effective simultaneously.
The data-moving triggering method of the small-capacity FIFO storage of the device data-moving trigger correspondence of the correspondence of second embodiment comprises the steps:
Step 21, system reset, small-capacity FIFO storage begins to receive the data that data source sends;
Step 22, reading of data judgment means judge whether any generation in two kinds of situations above-mentioned, if enter step 23, otherwise return step 22;
Step 23 is interrupted generation device and is produced the interruption that triggers the DMA data-moving, and sends to processor, returns step 22.
As shown in Figure 4, fifo_wdata, fifo_wen (effectively high), fifo_wclk are respectively writing data bus, writing and enable and write clock of small-capacity FIFO storage 100, write data by data source 200 controls; Fifo_rdata, fifo_ren (effectively high), fifo_rclk be respectively small-capacity FIFO storage 100 read data bus, read to enable and read clock, by processor 300 control sense datas; Fifo_hf is the half-full sign of small-capacity FIFO storage 100; Reset is a systematic reset signal; Int2processor is the interrupt source of interruption that sends to the triggering DMA data-moving of processor 300, and Int2processor is set to DMA data-moving interrupt source in processor, and rising edge is effective.
Above-mentioned reading of data judgment means can be a counter, and it possesses half the state of cycling jump that number is the degree of depth of small-capacity FIFO storage 100, is 2 as the degree of depth of small-capacity FIFO storage
N+1, then counter possesses 2
NThe state of individual cycling jump is first state as the counter current state, and next redirect status indication is second state, and the rest may be inferred, state to the last, promptly the 2nd
NIndividual state;
When systematic reset signal is effective, this counter is first state, when reset mode is invalid, next redirect status indication is second state, this reset mode is a unique state, different with other states, this counter is according to fifo_rclk, fifo_ren has judged whether an effective small-capacity FIFO storage read access operation, rising edge at fifo_rclk, if fifo_ren is the high level effective status, show an effective small-capacity FIFO storage read access operation is arranged, counter jumps to NextState, when processor read the data that are equivalent to small-capacity FIFO storage 100 half degree of depth from small-capacity FIFO storage 100, counter was from the 2nd
NIndividual state jumps to first state;
Interrupt generation device and only be in first state, and fifo_hf indicates and produces the interruption that triggers the DMA data-moving, and send to processor 300 when effective at counter.
Because processor 300 will interrupt the interrupt source that the interruption of generation device generation is set at the DMA data-moving of Event triggered, therefore in receiving this, have no progeny and trigger the DMA data-moving, move the data that are equivalent to small-capacity FIFO storage 100 half degree of depth from small-capacity FIFO storage.
As shown in Figure 4, this interruption generation device produces an Int2processor, and and if only if that counter is in first state for this Int2processor simultaneously, and when fifo_hf is effective, Int2processor is " 1 ", and under other situations, Int2processor is " 0 ".Int2processor is set to interrupt source in the processor configuration simultaneously, it is effective to set rising edge simultaneously, therefore whenever counter is in first state, and when fifo_hf is effective, Int2processor jumps to " 1 " from " 0 ", produce and interrupt, so the corresponding triggering DMA data-moving of processor meeting, move the data that are equivalent to small-capacity FIFO storage 100 half degree of depth from small-capacity FIFO storage.
Certainly, int2process also can be that and if only if, and counter is in first state, and fifo_hf is when effective, and Int2processor is " 0 ", and under other situations, Int2processor is " 1 ", but should be that negative edge is effective this moment in the processor configuration.
Fig. 5 is the emulation synoptic diagram of the data-moving of second embodiment of the invention, as shown in Figure 5, fifo_hf has negative edge 3 times among the figure, by existing method, all can trigger the DMA data-moving at 3 negative edges, but have only fifo_hf the first time negative edge and for the third time negative edge moment of taking place be the moment that real expectation can trigger processor DMA data-moving, and negative edge is the interrupt source that needs the falseness of shielding for the second time.As shown in Figure 5, in the present invention, device data-moving trigger utilizes steering logic effectively to shield false interruption, and Int2processor is in the correct moment, and the interruption as processor DMA data-moving of twice rising edge is provided.
The above embodiments all send data instance with data source to processor and describe, but after the FIFO reading-writing port is exchanged, also can be applied to processor and send, or be applied to the sight of first data source of other types to second data source transmission data to the data of data source.
Said apparatus can use discrete device to realize, also can realize in FPGA (Field ProgrammableGate Array, field programmable gate array) or ASIC (application specific integrated circuit, special IC).
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (14)
1. the device data-moving trigger of a small-capacity FIFO storage, be used to produce interrupt source and send to processor, it is characterized in that, described interrupt source is used for producing the interruption that trigger data is moved when first condition is set up, and described first condition is to have at least the new data of half degree of depth that is equivalent to described small-capacity FIFO storage to write in the described small-capacity FIFO storage.
2. device according to claim 1 is characterized in that, described data-moving is a direct memory storage data-moving.
3. device according to claim 1 and 2 is characterized in that, specifically comprises:
Write the data judgment means, be used to judge whether first condition is set up;
Interrupt generation device, be used to produce described interrupt source and send to described processor, described interrupt source is used for producing described interruption when said write data judgment means is judged described first condition and set up.
4. device according to claim 3, it is characterized in that, said write data judgment means is a counter, described counter possesses half the state of cycling jump that number is the depth value of described small-capacity FIFO storage, when an effective small-capacity FIFO storage number of write access operations, described counter jumps to next state, and described counter is judged described first condition establishment when last state jumps to first state.
5. device according to claim 4 is characterized in that, described counter enables and writes clock and judge effective small-capacity FIFO storage number of write access operations according to writing.
6. device according to claim 1 and 2 is characterized in that, when second condition and the 3rd condition were set up simultaneously, described first condition was set up; Described second condition is: after the system reset, described processor is reading of data from described small-capacity FIFO storage not, or last trigger finish after, described processor has read half data of the described small-capacity FIFO storage degree of depth from described small-capacity FIFO storage, described the 3rd condition is that the half-full sign of described small-capacity FIFO storage is effective.
7. device according to claim 6 is characterized in that, comprising:
The reading and writing data judgment means is used to judge whether second condition and the 3rd condition are set up simultaneously;
Interrupt generation device, be used to produce described interrupt source and send to described processor, described interrupt source is used for judging in described reading and writing data judgment means and produces described interruption when described second condition and the 3rd condition are set up simultaneously.
8. device according to claim 7, it is characterized in that, described reading and writing data judgment means comprises a counter, described counter possesses half the state of cycling jump that number is the depth value of described small-capacity FIFO storage, when an effective small-capacity FIFO storage read access is operated, described counter jumps to next state, judges described second condition establishment when described counter is in first state.
9. device according to claim 8 is characterized in that, described counter is judged effective small-capacity FIFO storage read access operation according to reading to enable and read clock.
10. the data-moving triggering method of a small-capacity FIFO storage, device data-moving trigger by small-capacity FIFO storage produces interrupt source and sends to processor, it is characterized in that, described interrupt source produces the interruption that trigger data is moved when first condition is set up, described first condition is to have at least the new data of half degree of depth that is equivalent to described small-capacity FIFO storage to write in the described small-capacity FIFO storage.
11. method according to claim 10 is characterized in that, described data-moving is a direct memory storage data-moving.
12. according to claim 10 or 11 described methods, it is characterized in that, the device data-moving trigger of described small-capacity FIFO storage comprises a counter, described counter possesses half the state of cycling jump that number is the depth value of described small-capacity FIFO storage, when an effective small-capacity FIFO storage number of write access operations, described counter jumps to next state, and described counter is judged described first condition establishment when last state jumps to first state.
13., it is characterized in that when second condition and the 3rd condition were set up simultaneously, described first condition was set up according to claim 10 or 11 described methods; Described second condition is: after the system reset, described processor is reading of data from described small-capacity FIFO storage not, or last trigger finish after, described processor has read half data of the described small-capacity FIFO storage degree of depth from described small-capacity FIFO storage, described the 3rd condition is that the half-full sign of described small-capacity FIFO storage is effective.
14. method according to claim 13, it is characterized in that, the device data-moving trigger of described small-capacity FIFO storage comprises a counter, described counter possesses half the state of cycling jump that number is the depth value of described small-capacity FIFO storage, when an effective small-capacity FIFO storage read access is operated, described counter jumps to next state, judges described second condition establishment when described counter is in first state.
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| CN103345377A (en) * | 2013-07-23 | 2013-10-09 | 盛科网络（苏州）有限公司 | FIFO storer control method and device |
| CN104503928A (en) * | 2014-12-05 | 2015-04-08 | 中国航空工业集团公司第六三一研究所 | Random memory circuit based on queue management |
| CN108399915A (en) * | 2017-02-08 | 2018-08-14 | 英特尔公司 | Low-power key phrase detects |
| CN108399915B (en) * | 2017-02-08 | 2024-05-07 | 英特尔公司 | Low power key phrase detection |
| CN111294116A (en) * | 2019-11-26 | 2020-06-16 | 北京航天长征飞行器研究所 | Linear frequency modulation signal processing method, device and equipment |
| CN111294117A (en) * | 2019-11-26 | 2020-06-16 | 北京航天长征飞行器研究所 | Phase coding signal processing method, device and equipment |
| CN111294116B (en) * | 2019-11-26 | 2022-04-12 | 北京航天长征飞行器研究所 | Linear frequency modulation signal processing method, device and equipment |
| CN113064847A (en) * | 2021-03-25 | 2021-07-02 | 浙江清华柔性电子技术研究院 | Data transmission method, system, processor and DMA controller |
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