CN104503928A - Random memory circuit based on queue management - Google Patents

Abstract

The invention provides a random memory circuit suitable for an FPGA logic circuit. A queue marker register is additionally arranged based on the conventional FIFO buffering interaction mode, and is used for realizing state description of a buffering unit; assurance of data submitting order is realized through the FIFO circuit; software can use buffering dynamically according to actual requirements; sending order management mechanism can be realized by operating the FIFO. Under conventional random access and queue access information interaction modes, the random memory circuit effectively combines the two modes, meets the management mode that random access is adopted at one end while queue dispatching is adopted at the other end, and effectively satisfies system application.

Description

A kind of based on queue management can memory circuit at random

Technical field:

The invention belongs to design of computer hardware field, relate to a kind of be applicable to fpga logic circuit can memory circuit at random.

Background technology:

When design height communication network board, need data-interface at a high speed to realize data interaction access between main frame and board, and interaction mechanism is simple and reliable, to meet the requirement of system for communication efficiency and application model.

Traditional interactive mode generally comprises the following two kinds from using forestland:

Whether one is random access mode, and in this mode, host side can random access buffer cell, by management buffer cell flag notification logical circuit, have data to need mutual by the state recognition of logical circuit judgement symbol.Shortcoming is complex management, None-identified data submission order, and for the complex management indicated, advantage is that main frame uses dirigibility high.

Another is the pattern based on queue, in this mode, host side and logical circuit are by safeguarding that queue pointer's mode realizes queue management, it adopts mechanism for FIFO (first in first out), host side and logical circuit must be merely able to sequential storage data, advantage is that structure is simple, and be easy to realize, shortcoming is that supported application model is single.

Above two kinds of modes, no matter which kind of, the equal Shortcomings when meeting following application model:

Host side Random Access Data, but require that hardware processes according to the order submitted to, and after processing is completed, corresponding buffer zone can be discharged according to virtual condition data.

Summary of the invention:

The object of this invention is to provide one can memory circuit at random, to meet above-mentioned application model, can either ensure that hardware circuit is ensureing the situation dispatching data of sequencing according to queue mode, also can meet the requirement that data random access and buffer zone discharge at random simultaneously.

Technical scheme of the present invention is as follows:

Based on queue management can a memory circuit at random, its special character is: comprise

N buffer cell, and set up data interaction between main frame;

The degree of depth is the FIFO memory of n, and the buffering corresponding to each buffer cell that host side sends is numbered by this FIFO memory sequence delivery to scheduler;

Width is the buffer cell Status Flag register of n bits, and each bit wherein, for describing the state of corresponding buffer cell, is responsible for set and clearing respectively by described host side and scheduler; And

Described scheduler, in order to read the content of described FIFO memory and buffer cell and to judge bit clearing specific in buffer cell Status Flag register.

Above-mentioned can the access implementation method of memory circuit at random, comprise the following steps:

1) host side distributing buffer unit, and in buffer cell Status Flag register, fill in buffering service marking according to arranging to the use of buffer cell, by FIFO memory transmission buffering numbering;

2) dispatch scheduler inquiry FIFO memory state, read buffering numbering, carry out digital independent and process;

3), after scheduler completes process, reset buffering service marking, buffer release unit, completes a data interaction.

The present invention by increase flag register, as the mark of buffering using state, and in conjunction with the use of FIFO, both can adapt to the requirement of traditional page management approach, also can meet the requirement of system random access concurrent processing.Specifically there is following advantage:

Be simple and easy to use: effectively can simplify amortization management method when fpga logic designs, save logical resource, host software can realize random access capabilities in a straightforward manner simultaneously;

Versatility is good: can meet queue application mode, also can meet random administration mode, and only need revise software can adapt to, and the versatility of hardware improves;

High efficient and flexible: the mutual dispatch deal of high speed that can realize data with less software and hardware expense, can meet the data coupling requirement of high-speed data communication.

Accompanying drawing explanation

Fig. 1 is circuit diagram of the present invention.

Embodiment

Embodiments of the invention as shown in Figure 1, under the buffering interactive mode of tradition based on FIFO, increase a queue flag register, for realizing the state description of buffer cell, the guarantee of data submission order is realized by fifo circuit, software can use buffering according to actual needs dynamically, and realizes the sequence management mechanism of transmission by operation FIFO simultaneously.Both, under the information interaction pattern of traditional random access and queue access, effectively combine, meet one end random access by the present invention, and the way to manage of one end employings degree row scheduling, the system that effectively meets is applied.

1. logic circuit unit:

1) degree of depth be the fifo circuit of n 1., mutual for the queuing realizing available buffer;

2) width be the buffer status register of n bits 2., each bit is for describing the state of corresponding buffer cell;

3) pool of buffer unit 3., user interactive data, can be the descriptor of buffer cell, also can be physically actual storage block; Following treatment scheme is described for descriptor.

4) scheduler 4., realizes FIFO content and read scheduling and buffering Single Component Management.

2. treatment scheme:

A. after powering on or resetting, be 1. dummy status, 2., the value of all positions is " 0 ", and represent that corresponding buffering is idle, descriptor is 3. invalid, represents that buffering does not configure, 4. detects empty full scale will 1..

B. host software performs buffering batch operation, upgrades descriptor 3., for identifying each address cushioned;

C. host software selects a buffering preparing to use, and writes data, after write, the respective flag of buffering in is 2. set to " 1 ", and the sequence number of buffering is write 1.;

D. 4. detect 1. for after " non-NULL " state, from FIFO, read queue sequence number, and according to the serial number read, from correspondence buffering, extract data process;

E. 4. after data processing completes, according to buffer cell serial number, the value of corresponding bit in is 2. set to " 0 " by scheduler again, discharges this buffering, completes an interactive operation of this element data.

The present invention can realize the FIFO management of data interaction, and supports phase of depositing the at random processing capacity of main frame and logic, effectively can simplify Logic Circuit Design simultaneously.

Claims (2)

1. based on queue management can a memory circuit at random, it is characterized in that: comprise

N buffer cell, and set up data interaction between main frame;

The degree of depth is the FIFO memory of n, and the buffering corresponding to each buffer cell that host side sends is numbered by this FIFO memory sequence delivery to scheduler;

Width is the buffer cell Status Flag register of n bits, and each bit wherein, for describing the state of corresponding buffer cell, is responsible for set and clearing respectively by described host side and scheduler; And

Described scheduler, in order to read the content of described FIFO memory and buffer cell and to judge bit clearing specific in buffer cell Status Flag register.

2. can the access implementation method of memory circuit at random described in claim 1, comprise the following steps:

1) host side distributing buffer unit, and in buffer cell Status Flag register, fill in buffering service marking according to arranging to the use of buffer cell, by FIFO memory transmission buffering numbering;

2) dispatch scheduler inquiry FIFO memory state, read buffering numbering, carry out digital independent and process;

3), after scheduler completes process, reset buffering service marking, buffer release unit, completes a data interaction.