KR0176096B1 - Data transfer apparatus between synchronous buses - Google Patents

Abstract

A high speed data transfer apparatus between a synchronous bus that matches a memory map between an active CPU system and a standby CPU system in a redundant CPU system constituting a fault tolerant type is disclosed.

According to the present invention, only a write operation among a variety of CPU transaction operations occurring in a synchronous local bus may monitor a specific area or an entire memory area, and when writing occurs, store the data in a data storage FIFO and then use a standby side local through a backplane bus. By creating the same write transaction on the bus, the memory maps of the active and standby blocks are matched.

According to the present invention, FIFO overflow can be prevented by reducing the write transaction traffic in hardware without any additional software additional action and without increasing the FIFO capacity for data storage.

Description

High speed data transfer device between synchronous buses

1 is a block diagram of a fault tolerant redundant CPU system for explaining an application example of a high-speed data transmission apparatus according to the present invention.

2 is a functional block diagram of a high speed data transmission apparatus according to the present invention.

FIG. 3 is a block diagram showing details of an active block in FIG.

FIG. 4 is a detailed block diagram of the standby block in FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory transfer device between two CPU systems that transfers memory of one CPU system to a memory of an opposite CPU system through a backplane bus. In particular, the present invention relates to an active CPU system in a redundant CPU system constituting a fault tolerance type. A high speed data transfer device between synchronous buses that matches a memory map between standby side CPU systems.

The problem with the conventional high speed data transfer apparatus is that in addition to the memory write operation on the active side in order to match the data in a specific memory section of the active area and the standby area, the standby side memory write is performed in software using an address map of an extended concept. There is a problem of poor performance.

In addition, even with simultaneous writes, the standby side memory must be completely written to receive a response signal, thereby reducing overall system performance. In addition, this conventional scheme can be implemented in an asynchronous local bus, but has a problem in that it is not suitable for data transmission between synchronous local buses.

In addition to the above-described problems, the high-speed data transmission apparatus has a problem in that a full storage of data in First Out First Out (FIFO) occurs due to a large amount of write transactions occurring instantaneously. This phenomenon saves a lot of time before the data to be moved is written to the memory of the active bus directly to the data FIFO, moved it to the dual-port memory of the standby block, and then again takes the standby bus right and stores it in the local memory of the standby block. Because it takes. This FIFO overflow can be somewhat prevented by increasing the data storage FIFO size for buffering, but it is not a fundamental solution.

Accordingly, the present invention has been made to solve the above-described problems, and its object is to reduce the write transaction traffic in hardware without additional software additional action and without increasing the FIFO capacity, thereby preventing FIFO overflow. It is to provide a high speed data transmission device between synchronous buses.

The present invention for achieving the above object is a high-speed data transfer device between the synchronous bus of two CPU system divided into active block and standby block, information storage FIFO for storing the size and error information of each transaction stored in the data storage FIFO Active local bus matching means for performing a matching function of an active local bus, detecting a corresponding write transaction, and storing the same in the data storage FIFO, using a programmable full signal of the data storage FIFO. When data is loaded into the data storage FIFO, a bus ticket of the active local bus is acquired to force the bus ticket to monitor the FIFO for reducing traffic of light transactions on the active local bus. A single piece of data Transaction transfer means for reading from the chapter FIFO and moving to the dual port memory of the standby block and retransmitting back to the dual port memory without losing information even if an error occurs when performing a write transaction to the local memory of the standby bus. And a standby local bus matching unit for matching individual transactions to the standby local bus.

The present invention is a transfer device which is copied to the same memory area in the standby local memory by simply writing to the local memory of the active bus without a separate software operation for memory write of the standby local bus. Suitable for

According to the present invention, when a write transaction occurs such that the data storage FIFO overflows instantaneously even before being transferred to the standby block local memory, the bus storage is requested to the active local bus regardless of the software operation so that the data storage FIFO reaches a certain level. You don't actually do anything until it's empty, but by catching the bus fakely, you dynamically control the FIFO overflow regardless of software behavior.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 is a diagram for explaining an application example of a high speed data transfer apparatus according to the present invention, and shows a block diagram of a fault tolerant redundant CPU system. First, assuming that the CPU A module 101 is an active processor and the CPU B module 103 is a standby processor, when the CPU A module 101 performs a write transaction to its own local memory 102, high-speed data The monitoring apparatus 200 monitors this and moves to the local memory 104 of the CPU B module 103 at high speed in real time. The data movement direction of the high speed data transmission apparatus 200 is moved from active to standby, and the data path may be interrupted or changed according to a setting.

2 is a block diagram illustrating a high-speed data transmission apparatus according to the present invention by function, and is divided into an active block and a standby block, which are divided into separate blocks that operate according to active or standby.

The active block is an active bus ticket acquiring unit that catches a bus ticket immediately before data overflows to the active local bus matching unit 201, the information storage FIFO 203, the data storage FIFO 204, and the data storage FIFO 204. 202, the standby block includes a dual port memory 207, a transaction moving unit 206, and a standby local bus matching unit 205.

Looking at the operation of the data transmission device having the above configuration for each block as follows.

First, when a write operation occurs in the memory area of the original local area on the active local bus (bus A), the active local bus matching unit 201 latches and stores the write transaction information in the data storage FIFO 204 as it is. . The size and error information of the corresponding transaction are stored in the information storage FIFO 203.

At this time, in order to prevent the FIFO from being full due to a failure to quickly get the write transaction data in the data storage FIFO 204 in the standby block, the active bus ticket acquisition unit 202 may be configured to execute the data storage FIFO 204. When it receives a programmable full signal and detects this signal, it forcibly requests the bus ticket from the active bus to reduce the load of the write transaction on the active local bus. During this period, the overflow block may be prevented by taking data stored in the data storage FIFO 204 in the standby block. If data below a certain level remains in the data storage FIFO 204, the bus ticket is released and a write transaction is generated again.

On the other hand, in the standby block, if one or more transactions are contained in the information storage FIFO 203, the transaction moving unit 206 sends the information of the transaction to the information storage FIFO 203 of the active block in several sizes. It reads whether it is in the storage FIFO 204 and if the transaction is in error. With this information, one write transaction is read from the data storage FIFO 204 and stored in the dual port memory 207, and then one standby transaction is prepared in the dual port memory 207. 205). After obtaining the bus ticket, the standby local bus matching unit 205 reads one transaction stored in the dual port memory 207 and stores it in the local memory of the standby system. If an error cycle occurs when a write operation is performed on the standby bus (Bus B), the value is read from the dual port memory 207 again, and then the write transaction is performed again. When the write transaction is normally terminated on the standby bus (bus B), the transaction moving unit 206 is informed that the termination has been completed. The transaction moving unit 206 checks again whether there is a transaction remaining in the information storage FIFO 203, and if so, reads the information for one transaction and then reads the data of the transaction from the data storage FIFO 204 to double-port. It stores in the memory 207, notifies the standby local bus matching unit 205 of the start signal, and the standby local bus matching unit 205 takes the bus right again and starts data movement. Repeat this operation over and over.

FIG. 3 is an enlarged view of the active block of the above-described high speed data transmission apparatus, and the operation of the active block, in particular, the operation of the active bus acquirer, will be described in detail with reference to the drawing. The active local bus matching unit 201 stores the write transaction in the memory area desired by the active local bus matching unit 201 in the data storage FIFO 203. At this time, information on whether there is an error of the corresponding transaction and how many the corresponding transaction is configured is stored in the information storage FIFO 204. When storing the write data in the data storage FIFO 203, the start bit is set by extending the bits separately for distinguishing each transaction. This start bit is later used as a transaction alignment error on the standby bus. This operation is continued regardless of the standby block.

If there is a possibility that the data stored in the data storage FIFO 203 may not be taken quickly due to the transmission rate difference in the standby block, and a FIFO full may occur, a programmable overflow signal indicating the overflow information immediately before overflow occurs. It detects through the active bus ticket acquisition unit 202. Upon receiving this signal, the active bus ticket acquiring unit 202 requests a bus ticket from the active local bus, and upon receiving the bus ticket permission, immediately grabs the bus ticket and makes the bus busy so that no further writes are made to the active local bus. Do not let the action take place. At this time, if the amount of data stored in the data storage FIFO 203 falls below a certain level, the bus busy (busy) is released and the write operation is continued on the active side again. As a result, the FIFO overflow can be prevented even when the memory transfer rates of the active block and the standby block do not match.

4 is an enlarged view of a standby block of a high-speed data transmission apparatus, in which a dual port memory 207 in which one transaction is stored and one or more transactions in the active block information storage FIFO 204 are provided. The transaction moving unit 206 reads data from the FIFO 203 and transfers one transaction to the dual port memory 207, and the one transaction moved to the dual port memory 207 stores the local memory of the standby local system bus. It consists of a standby local bus matching unit 205 to be stored in.

Referring to FIG. 4 having such a configuration, the operation thereof will be described. First, the transaction moving unit 206 always monitors the information storage FIFO 204, if there is more than one data, reads whether there is an error in the transaction, the size of the transaction, and stores the information as many as the number of transactions. Move to. At this time, if the transaction is an errored transaction, the data storage FIFO 203 simply performs a read operation as much as the size information. Transferring a transaction to the dual port memory 207 informs the standby local bus matching unit 205 that the dual port memory 207 has a valid data ready. When the standby local bus matching unit 205 receives the start signal from the transaction moving unit 206, the standby local bus matching unit 205 immediately requests the standby bus to hold the bus, reads data from the dual port memory 207, and performs a write transaction. When reading data from the dual port memory 207, if the transaction start bit is not correct, it informs the active locale matching that a transmission error has occurred. The active local bus matching unit 201 interrupts this information and notifies the upper active CPU block. On the other hand, if a local writing error occurs in the standby local bus by reading data from the dual port memory 207, starting from the beginning in the dual port memory 207 again and ending the transaction normally, the transaction moving unit 206 ends. Give a signal.

As described above, in the present invention, only a write operation among various CPU transaction operations occurring in a synchronous local bus, while monitoring a specific area or an entire memory area and storing the data in a data storage FIFO after writing, Matching the memory maps of active and standby blocks by generating the same write transaction on the standby local bus.

As described above, according to the present invention, the FIFO overflow can be prevented by reducing the write transaction traffic in hardware without a separate software additional action and without increasing the FIFO capacity for data storage.

Claims (1)

A high speed data transfer device between a synchronous bus of two CPU systems divided into an active block and a standby block, comprising: an information storage FIFO for storing size and error information of each transaction stored in a data storage FIFO; Active local bus matching means for performing a matching function of an active local bus, detecting a corresponding write transaction, and storing the write transaction in the data storage FIFO; By using a programmable full signal of the data storage FIFO, when more than a certain amount of data is filled into the data storage FIFO, the bus ticket of the active local bus is acquired to force the bus ticket to reduce the write transaction traffic on the active local bus. FIFO full monitoring and active bus ticket acquisition means; The data of one write transaction occurring in the active bus is read from the data storage FIFO and moved to the dual port memory of the standby block, and the data is retransmitted back to the dual port memory without losing information even if an error occurs when the write transaction is performed in the local memory of the standby bus. Transaction moving means; And a standby local bus matching unit for matching one transaction stored in the dual port memory to a standby local bus.