CN101056105B - Compound MOS capacitor and phase-locked loop - Google Patents
Compound MOS capacitor and phase-locked loop Download PDFInfo
- Publication number
- CN101056105B CN101056105B CN2007100965052A CN200710096505A CN101056105B CN 101056105 B CN101056105 B CN 101056105B CN 2007100965052 A CN2007100965052 A CN 2007100965052A CN 200710096505 A CN200710096505 A CN 200710096505A CN 101056105 B CN101056105 B CN 101056105B
- Authority
- CN
- China
- Prior art keywords
- voltage
- mos capacitor
- type mos
- low
- high voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The present invention provides a combined type Metal Oxide Semiconductor (MOS) capacitor and a phase locked loop of using the same. In the phase locked loop, the combined type MOS capacitor used by a loop filter belongs to a high voltage assembly, and a voltage controlled oscillator belongs to a low voltage assembly. The combined type MOS capacitor includes a HV PMOS capacitor and a HV NMOS capacitor. The base electrode of the HV PMOS capacitor is coupled with a power supply end of a low voltage source. The base electrode of the HV NMOS capacitor is coupled with the ground end of the low voltage source. The grid of the HV PMOS capacitor is connected with the grid of the HV NMOS capacitor to receive a control voltage. The capacitance value of the combined type MOS capacitor is constant and does not vary with the control voltage.
Description
Technical field
The present invention relates to a kind of MOS capacitor (MOS capacitor), be particularly to use this kind mos capacitance phase-locked loop (Phase-Locked Loop, PLL).
Background technology
In the field of less radio-frequency,, must research and develop phase-locked loop at a high speed to produce clock (clock) at a high speed in order to promote the speed of reflector (transceiver), receiver (receiver).Therefore, the making of phase-locked loop must be adopted advanced IC technology.0.15 the following technology of micron is used thin grid oxic horizon (thin-oxide) usually, can produce serious leakage phenomenon (current leakage).Be operating as example with discharging and recharging of electric capacity, the leakage phenomenon of electric capacity can cause the time that discharges and recharges of electric capacity asymmetric.Therefore present phase-locked loop is many realizes electric capacity in the loop filter with thick grid oxic horizon (thick-oxide).Because the assembly made from thin grid oxide layer uses lower voltage source usually, so be referred to as low-voltage assembly (LV device), the assembly made from thick grid oxic horizon uses the high voltage source usually, so be referred to as high-voltage assembly (HV device).
Fig. 1 is phase-locked loop 100 schematic diagrames commonly used at present.In order to allow phase-locked loop can be operated in high frequency, voltage controlled oscillator 104 adopts a low-voltage assembly, to produce high frequency clock.Because voltage-controlled oscillator (VCO) 104 is a low-voltage assembly, its leakage phenomenon is quite serious, so loop filter 102 employings one high-voltage assembly, to overcome leakage phenomenon.Thus, phase-locked loop 100 uses two kinds of voltage sources at least, and a kind of (magnitude of voltage is V for high voltage source
DDH), it is a kind of that (magnitude of voltage is V for low-voltage source
DDL), use for this high-voltage assembly and this low-voltage assembly respectively.In must be operated between given zone, the grid of mos capacitance just can have the capacitance of deciding.Between the grid operating space of HV NMOS electric capacity greater than V
Thn_HVWhen the base voltage of PMOS electric capacity is V
DDThe time, between the grid operating space of HV PMOS electric capacity less than (V
DD-| V
Thp-HV|).If mos capacitance is applied in the loop filter 102, also can be between the operating space of mos capacitance by voltage controlled oscillator 104 employed low-voltage source V
DDLLimit.With V
DDL=1.2V, V
DDH=2.5V, HV nmos pass transistor and the transistorized critical voltage value of HV PMOS are V
Thn_HV=| V
Thp_HV|=0.8V illustrates it.If what loop filter 102 used is HV NMOS electric capacity, then can be subjected to V between the operating space of HV NMOS electric capacity
DDLRestriction is limited in suitable narrow region, 0.8V (V
Thn_HV) to 1.2V (V
DDL).If what loop filter 102 used is HV PMOS electric capacity, because (V
DDH-| V
Thp_HV|)＞V
DDL, the upper limit between the operating space of HV PMOS electric capacity can be subjected to V
DDLRestriction is 0V to 1.2V (V between the operating space of HV PMOS electric capacity
DDL).With respect to HV NMOS electric capacity, HV PMOS electric capacity has had between enough operating spaces, but is to use HV PMOS electric capacity to realize that the phase-locked loop 100 of loop filter 102 still can face other problem.Because loop filter 102 uses different voltage sources with voltage controlled oscillator 104, the voltage control signal that loop filter 102 offers voltage controlled oscillator 104 can cause the disturbance effect (jitter performance) of the voltage controlled oscillator 104 that uses low-voltage source to worsen along with the high voltage source disturbance of loop oscillator 102.
Therefore, how in phase-locked loop 100, use single low-voltage source and solve the leakage phenomenon of electric capacity simultaneously, and improve disturbance effect between the operating space of diffused mos electric capacity simultaneously, the target of being badly in need of reaching for phase-locked loop apparatus at present.
Summary of the invention
The invention provides a kind of novel mos capacitance, be called combined type MOS capacitor.The present invention and utilize this combined type MOS capacitor to make a kind of phase-locked loop apparatus, can produce high frequency clock, reduce loop filter leakage current effects, expansion voltage controlled oscillator control signal opereating specification and improve disturbance effect.
Comprise a phase-frequency detector, a charge pump, a loop filter and a voltage controlled oscillator in the phase-locked loop that the present invention proposes.This phase-frequency detector measures the phase difference and the difference on the frequency of a reference signal and a feedback signal.This charge pump comprises a charging circuit and a discharge circuit, and switches this charging circuit and this discharge circuit according to the phase difference and the difference on the frequency of this reference signal and this feedback signal.This loop filter has at least one combined type MOS capacitor.This charge pump can discharge and recharge voltage with the output of adjusting this loop filter to this combined type MOS capacitor.This voltage controlled oscillator is exported an oscillator signal, and adjusts the frequency of this oscillator signal according to the voltage of the output of this loop filter.
Assembly in this phase-locked loop can be categorized into high-voltage assembly and low-voltage assembly, the thickness of grid oxide layer of this high-voltage assembly is greater than the thickness of grid oxide layer of this low-voltage assembly, the combined type MOS capacitor of this loop filter belongs to this high-voltage assembly, and this voltage controlled oscillator belongs to this low-voltage assembly.This phase-locked loop only uses a low-voltage source, and (magnitude of voltage is V
DDL).This low-voltage source i.e. employed this voltage source of this combined type MOS capacitor, and this voltage controlled oscillator also uses this low-voltage source.
Comprise HV PMOS electric capacity and a HV NMOS electric capacity in this combined type MOS capacitor.The base stage of this HV PMOS electric capacity couples the power end of this low-voltage bias generator.The base stage of this HV NMOS electric capacity couples the ground end of this low-voltage bias generator.The magnitude of voltage of the employed low-voltage source of this combined type MOS capacitor is V
DDLThe critical voltage value of this HV PMOS electric capacity is | V
Thp_HV|.The critical voltage value V of this HV NMOS electric capacity
Thn_HVAn approximate critical value (V
DDL-| V
Thp_HV|).The grid of the grid of this HV PMOS electric capacity and this HV NMOS electric capacity links together, to receive a control voltage.The capacitance of this combined type MOS capacitor is definite value and does not change with this control voltage.
This HV PMOS electric capacity and this HV NMOS electric capacity can have same passage length.
This loop filter more comprises a resistance, one first combined type MOS capacitor and one second combined type MOS capacitor.First end of this resistance couples the output of this loop filter.The control end of this first combined type MOS capacitor couples second end of this resistance.The control end of this second combined type MOS capacitor couples the output of this loop filter.
Description of drawings
Fig. 1 is conventional phase locked loops 100 schematic diagrames;
Fig. 2 is the schematic diagram of phase-locked loop 200 provided by the present invention;
Fig. 3 is the diagram of combined type MOS capacitor 300 of the present invention;
Fig. 4 A, 4B, 4C narration control voltage V
cRelation with capacitance; And
Fig. 5 A, 5B are all and adjust the capacitance that different PN ratio value K simulates out.。
The reference numeral explanation
The 100-conventional phase locked loops;
102-loop filter (high-voltage assembly);
104-voltage controlled oscillator (low-voltage assembly);
200-phase-locked loop of the present invention;
202-loop filter (high-voltage assembly, contain combined type MOS capacitor);
204-voltage controlled oscillator (low-voltage assembly);
The 206-phase-frequency detector; The 208-charge pump;
The 210-feedback signal;
V
DDHThe voltage end of-high voltage source;
V
DDLThe voltage end of-low-voltage source;
The 300-combined type MOS capacitor; 302-HV PMOS electric capacity;
304-HV NMOS electric capacity;
The capacitance of 402-HV PMOS electric capacity 302;
The capacitance of 404-HV NMOS electric capacity 304;
The capacitance of 406-combined type MOS capacitor 300.
Embodiment
Fig. 2 is the schematic diagram of phase-locked loop 200 provided by the present invention.Phase-locked loop 200 comprises a phase-frequency detector 206, a charge pump 208, a loop filter 202 and a voltage controlled oscillator 204.Loop filter 202 more comprises a resistance R
1, one first combined type MOS capacitor is (by M
N1With M
P1Form) and one second combined type MOS capacitor (by M
N2With M
P2Form).Resistance R
1First end couple the output V of loop filter 202
ControlThe control end of this first combined type MOS capacitor couples resistance R
1Second end.The control end of this second combined type MOS capacitor couples the output V of loop filter 202
Control
Phase-frequency detector 206 measures a reference signal CK
RefAnd the phase difference of a feedback signal 210 and difference on the frequency.Charge pump 208 comprises a charging circuit and a discharge circuit, switches this charging circuit and this discharge circuit according to the phase difference and the difference on the frequency of this reference signal and this feedback signal.The combined type MOS capacitor of 208 pairs of loop filters 202 of charge pump discharges and recharges the voltage V with the output of adjusting this loop filter 202
ControlVoltage controlled oscillator 204 outputs one oscillator signal CK
Vco, and according to voltage V
ControlAdjust oscillator signal CK
VcoFrequency.
Fig. 3 is the diagram of combined type MOS capacitor 300 of the present invention.Combined type MOS capacitor 300 comprises HV PMOS electric capacity 302 and a HV NMOS electric capacity 304.The base stage of HV PMOS electric capacity 302, drain electrode, all couple a low-voltage bias voltage V with source electrode
Bias(V in the present embodiment,
BiasCan directly be biased in the power end V of low-voltage source
DDL, so just need not seek bias point again).The base stage of HV NMOS electric capacity 304, drain electrode, all couple the ground end V of this low-voltage source with source electrode
SSThe grid of HV PMOS electric capacity 302 and the grid of this HVNMOS electric capacity 304 link together, in order to receive a control voltage V
c| V
Thp_HV| with V
Thn_HVBe respectively the critical voltage value of HV PMOS electric capacity 302 and HV NMOS electric capacity 304, and V
Thn_HVBe similar to (V
Bias(=V
DDL)-| V
Thp_HV|).In addition, at control voltage V
cBut opereating specification in, the variation of the capacitance of combined type MOS capacitor 300 can be considered as definite value electric capacity with combined type MOS capacitor 300 below ± 10%.
Fig. 4 narrates control voltage V
cWith the relation of capacitance, the magnitude of voltage of the low-voltage source that the employed technology of assembly is the Fujitsu0.09 micron, adopted is V
DDLCurve 402, curve 404 and curve 406 are represented the capacitance of HV PMOS electric capacity 302, HV NMOS electric capacity 304 and combined type MOS capacitor 300 respectively.| V
Thp_HV| with V
Thn_HVBe respectively the critical voltage value of HV PMOS electric capacity 302 and HV NMOS electric capacity 304.In order to make combined type MOS capacitor 300 have definite value electric capacity, V
DDL, | V
Thp_HV| with V
Thn_HVMust satisfy V
Thn-HVBe similar to (V
DDL-| V
Thp_HV|).Cooperate suitable V
DDL, the critical voltage of the HV PMOS of 0.09 micron technology manufacturing of Fujitsu and HV NMOS electric capacity by chance can satisfy V
Thn_HVBe similar to (V
DDL-| V
Thp_HV|), and the variable quantity of capacitance that by chance can make combined type MOS capacitor 300 is below ± 10%, and combined type MOS capacitor 300 can be regarded as having the capacitance of deciding.With V
Thn_HV=| V
Thp_HV|=0.6-0.8 is an example, works as V
DDLWhen being respectively 1.2V, 1V, 0.8V, the variation of curve 402, curve 404 and curve 406 is shown in Fig. 4 A, 4B, 4C, the variable quantity of the capacitance of combined type MOS capacitor 300 is all below ± 10%, and so combined type MOS capacitor 300 can be regarded as having the capacitance of deciding.In other technology, also can utilize ion to implant and adjust | V
Thp_HV| with V
Thn_HV, to satisfy V
Thn_HVBe similar to (V
Bias-| V
Thp_HV|), and make combined type MOS capacitor have the capacitance of deciding.
In the another kind of embodiment of combined type MOS capacitor 300, HV PMOS electric capacity 302 has same passage length, different channel widths, i.e. W with HV NMOS electric capacity 304
p=K*W
n, L
p=L
n, wherein, parameter K is a PN ratio value (P/N ratio).In order to realize combined type MOS capacitor 300, K*W
n* L
p* C
Oxp(V
c)+W
n* L
n* C
Oxn(V
c) be definite value, wherein C
Oxp(V
c) and C
Oxn(V
c) be respectively and control voltage V
cFunction.Aforesaid equation also can only be adjusted the technology of HV PMOS electric capacity and be reached by the fixing technology of HV NMOS electric capacity 304.Fixedly the technology of HV PMOS electric capacity 302 is only adjusted the technology of HV NMOS electric capacity and also can be reached aforesaid equation.
Below be by the specific capacitance W that keeps HV NMOS for example
n* L
n* C
Oxn(V
c) constant, adjust the specific capacitance K*W of HVPMOS
n* L
p* C
Oxp(V
c), to look for best PN ratio value K, make the capacitance of combined type MOS capacitor 300 can have maximum linear opereating specification (widest linear operatingrange).When looking for best PN ratio value K, set L
p=L
n, W
p=W
n, L
p=L
nCan avoid mos capacitance that different frequency responses is arranged.
Fig. 5 A, 5B are all and adjust the capacitance that different PN ratio value K simulates out.Present embodiment also is the simulation of all being done with 0.09 micron technology of Fujitsu.Fig. 5 A is by the specific capacitance W that keeps HV NMOS
n* L
n* C
Oxn(V
c) constant, adjust the specific capacitance K*W of HV PMOS
n* L
p* C
Oxp(V
c), to look for best PN ratio value K.In Fig. 5 A, PN ratio value K is respectively 1,0.97.It is 1.03 that Fig. 5 B presents best PN ratio value K.Adjust PN ratio value K according to said method, can necessarily can obtain different PN ratio value K in different technology and different bias voltage (bias voltage of HV PMOS), make that the optimum value of K is slightly different with capacitance curve, also make the maximum linear opereating specification of combined type MOS capacitor 300 be able to effective extension simultaneously.
The assembly of the phase-locked loop 200 of Fig. 2 can be categorized into high-voltage assembly and low-voltage assembly.The thickness of grid oxide layer of this high-voltage assembly is greater than the thickness of grid oxide layer of this low-voltage assembly.The combined type MOS capacitor of loop filter 202 can belong to this high-voltage assembly.Voltage controlled oscillator 204 can belong to this low-voltage assembly.Can also exist other assembly to belong to this high-voltage assembly, as charge pump 208.In Fig. 2, phase-locked loop 200 employed voltage sources are that (magnitude of voltage is V to a single low-voltage source
DDL).The combined type MOS capacitor of loop filter 202 and voltage controlled oscillator 204 all use this low-voltage source, not only make combined type MOS capacitor have definite value electric capacity in the maximum linear opereating specification, have more reduced the disturbance effect of voltage controlled oscillator 204.
According to the above description, the present invention can allow whole phase-locked loop only use a low-voltage source, need not re-use any high voltage source, therefore solved the problem of original high and low voltage transitions, also reduced on the signal path between the high and low voltage source because of having added the disturbance effect that noise produces simultaneously.In addition, utilize again this combined type MOS capacitor allow whole phase-locked loop produce high frequency clock, reduce loop filter leakage current effects, expansion voltage controlled oscillator control signal opereating specification and improve disturbance effect.In addition, in different technology,, can make combined type MOS capacitor in the maximum linear opereating specification, have definite value electric capacity as long as select suitable low-voltage source and design suitable substance P N ratio value K for use, and parameter that needn't adjusting process can not increase spent cost on the technology yet.
Combined type MOS capacitor provided by the present invention can use in office what is the need for to want to be not limited only to the loop filter of phase-locked loop in the application of definite value electric capacity.The mos capacitance of any claim according to the invention all belongs to the scope that this specification institute desire is protected.
Above embodiment is several Xiang Shizuo method of the present invention, only with helping understand the present invention, is not to be used for limiting content of the present invention.As long as any change type of being derived according to the disclosed technology of the present patent application claim is for can all belonging to the scope of this specification institute desire protection by the present invention person of obtaining through association.
Claims (8)
1. compound MOS capacitor, comprising:
One high voltage P-type MOS capacitor, the base stage of this high voltage P-type MOS capacitor couples the power end of a low-voltage bias generator; And
One high voltage N-type MOS capacitor, the base stage of this high voltage N-type MOS capacitor couple the ground end of this low-voltage bias generator;
Wherein, the difference of the critical voltage value of the magnitude of voltage of low-voltage bias generator and this high voltage P-type MOS capacitor is similar to the critical voltage value of this high voltage N-type MOS capacitor,
The grid of the grid of this high voltage P-type MOS capacitor and this high voltage N-type MOS capacitor links together, in order to receive a control voltage.
2. compound MOS capacitor as claimed in claim 1, wherein, this high voltage P-type MOS capacitor and this high voltage N-type MOS capacitor have same passage length, tool proportionate relationship between the width of this high voltage P-type MOS capacitor and this high voltage N-type MOS capacitor.
3. compound MOS capacitor as claimed in claim 1, wherein, this compound MOS capacitor is used in the chip, this chip has a low-voltage source, assembly in this chip can be categorized into high-voltage assembly and low-voltage assembly, the thickness of grid oxide layer of this high-voltage assembly is greater than the thickness of grid oxide layer of this low-voltage assembly, and this compound MOS capacitor belongs to this high-voltage assembly, and this low-voltage bias generator is this low-voltage source.
4. phase-locked loop, comprising:
One phase-frequency detector measures the phase difference and the difference on the frequency of a reference signal and a feedback signal;
One charge pump comprises a charging circuit and a discharge circuit, switches this charging circuit and this discharge circuit according to the phase difference and the difference on the frequency of this reference signal and this feedback signal;
One loop filter has at least one compound MOS capacitor, and this charge pump discharges and recharges voltage with the output of adjusting this loop filter to this compound MOS capacitor; And
One voltage controlled oscillator is exported an oscillator signal, adjusts the frequency of this oscillator signal according to the voltage of the output of this loop filter;
Wherein, this compound MOS capacitor comprises:
One high voltage P-type MOS capacitor, the base stage of this high voltage P-type MOS capacitor couples the power end of a low-voltage bias generator; And
One high voltage N-type MOS capacitor, the base stage of this high voltage N-type MOS capacitor couple the ground end of this low-voltage bias generator;
Wherein, the difference of the critical voltage value of the magnitude of voltage of low-voltage bias generator and this high voltage P-type MOS capacitor equals the critical voltage value of this high voltage N-type MOS capacitor,
The grid of the grid of this high voltage P-type MOS capacitor and this high voltage N-type MOS capacitor links together, in order to receive a control voltage.
5. phase-locked loop as claimed in claim 4, assembly in this phase-locked loop can be categorized into high-voltage assembly and low-voltage assembly, the thickness of grid oxide layer of this high-voltage assembly is greater than the thickness of grid oxide layer of this low-voltage assembly, the compound MOS capacitor of this loop filter belongs to this high-voltage assembly, and this voltage controlled oscillator belongs to this low-voltage assembly.
6. phase-locked loop as claimed in claim 5 more comprises a low-voltage source, and this low-voltage source i.e. employed this low-voltage bias generator of this compound MOS capacitor, and this voltage controlled oscillator also uses this low-voltage source.
7. phase-locked loop as claimed in claim 4, wherein, the high voltage P-type MOS capacitor and the high voltage N-type MOS capacitor of this compound MOS capacitor have same passage length, have proportionate relationship between the high voltage P-type MOS capacitor of this compound MOS capacitor and the width of high voltage N-type MOS capacitor.
8. phase-locked loop as claimed in claim 4, wherein, this loop filter more comprises:
One resistance, first end of this resistance couples the output of this loop filter;
One first compound MOS capacitor, the control end of this first compound MOS capacitor couple second end of this resistance; And
One second compound MOS capacitor, the control end of this second compound MOS capacitor couples the output of this loop filter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100965052A CN101056105B (en) | 2007-04-11 | 2007-04-11 | Compound MOS capacitor and phase-locked loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100965052A CN101056105B (en) | 2007-04-11 | 2007-04-11 | Compound MOS capacitor and phase-locked loop |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101056105A CN101056105A (en) | 2007-10-17 |
| CN101056105B true CN101056105B (en) | 2011-05-11 |
Family
ID=38795757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007100965052A Active CN101056105B (en) | 2007-04-11 | 2007-04-11 | Compound MOS capacitor and phase-locked loop |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101056105B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101888242B (en) * | 2009-05-12 | 2012-12-19 | 上海时序电子科技有限公司 | Phase-locked loop circuit and operation method thereof |
| TWI465046B (en) * | 2011-04-07 | 2014-12-11 | Etron Technology Inc | Delay lock loop with a charge pump, loop filter, and method of phase locking of a delay lock loop |
| CN104201880B (en) * | 2014-07-15 | 2016-08-24 | 浙江大学 | The low current mismatch charge pump circuit of anti-process fluctuation under phaselocked loop low-voltage |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1540867A (en) * | 2003-04-25 | 2004-10-27 | 松下电器产业株式会社 | Low pass filter circuit, feedback system and semiconductor integrated circuit |
| US6828654B2 (en) * | 2001-12-27 | 2004-12-07 | Broadcom Corporation | Thick oxide P-gate NMOS capacitor for use in a phase-locked loop circuit and method of making same |
| US6867629B2 (en) * | 2001-08-29 | 2005-03-15 | Sun Microsystems, Inc. | Integrated circuit and method of adjusting capacitance of a node of an integrated circuit |
-
2007
- 2007-04-11 CN CN2007100965052A patent/CN101056105B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6867629B2 (en) * | 2001-08-29 | 2005-03-15 | Sun Microsystems, Inc. | Integrated circuit and method of adjusting capacitance of a node of an integrated circuit |
| US6828654B2 (en) * | 2001-12-27 | 2004-12-07 | Broadcom Corporation | Thick oxide P-gate NMOS capacitor for use in a phase-locked loop circuit and method of making same |
| CN1540867A (en) * | 2003-04-25 | 2004-10-27 | 松下电器产业株式会社 | Low pass filter circuit, feedback system and semiconductor integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101056105A (en) | 2007-10-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5139536B2 (en) | High speed switching low noise charge pump | |
| CN102136840B (en) | Self-biased phase-locked loop | |
| US8232822B2 (en) | Charge pump and phase-detecting apparatus, phase-locked loop and delay-locked loop using the same | |
| US8487677B1 (en) | Phase locked loop with adaptive biasing | |
| CN104201880A (en) | Low current mismatch charge pump circuit for resisting process fluctuation under low voltage of phase lock loop | |
| CN109921790B (en) | Quick start circuit, self-adaptive phase-locked loop and quick start method | |
| CN105141309A (en) | Phase-locked loop rapid locking circuit used for frequency hopping communication and operation method thereof | |
| CN101056105B (en) | Compound MOS capacitor and phase-locked loop | |
| JP4091576B2 (en) | Semiconductor integrated circuit and frequency modulation device | |
| JP2010135956A (en) | Pll circuit and method of controlling the same | |
| CN104641560B (en) | RF logic frequency dividers | |
| Shepherd et al. | 500 kHz–5 MHz phase-locked loops in high-temperature silicon carbide CMOS | |
| KR102101836B1 (en) | Delay cell and delay locked loop circuit and phase locked loop circuit adopting the same | |
| CN101753137B (en) | Phase-locked loop with start-up circuit | |
| US7636000B2 (en) | Phase locked loop without a charge pump and integrated circuit having the same | |
| US20080063131A1 (en) | Phase-locked loop circuit | |
| US7176732B2 (en) | Device and method for increasing the operating range of an electrical circuit | |
| US20240178752A1 (en) | Rf circuit with negative voltage generation and a method for rf circuit control | |
| JP3597961B2 (en) | Semiconductor integrated circuit device | |
| JP5179848B2 (en) | Voltage controlled oscillator and PLL circuit | |
| CN114301452A (en) | Phase-locked loop circuit, control method, charge pump and chip | |
| WO2002097994A1 (en) | Differential cmos controlled delay unit | |
| CN101938265A (en) | Current control ring oscillator and control method thereof | |
| US7609108B2 (en) | Phase-locked loop and compound MOS capacitor thereof | |
| JP2004235688A (en) | Semiconductor integrated circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |