CN101025720A - External memory controller timing configuration device and method - Google Patents
External memory controller timing configuration device and method Download PDFInfo
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- CN101025720A CN101025720A CN 200710079470 CN200710079470A CN101025720A CN 101025720 A CN101025720 A CN 101025720A CN 200710079470 CN200710079470 CN 200710079470 CN 200710079470 A CN200710079470 A CN 200710079470A CN 101025720 A CN101025720 A CN 101025720A
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Abstract
The invention relates to the chip field, providing an external memory controller timing configuration device and method, where the device comprises configuration register interface module and timing control module, where the configuration register interface module is used to configure and generate control signal's advanced invalid parameter and control parameter, and chip select signal according to the current memory parameter; the timing control module is used to generate control signal by the chip select signal according to the received control signal's advanced invalid parameter and control parameter; the control signal comprises write enable signal and/or output enable signal. And it can solve the problem of influencing the control on the current memory caused by stable write enable signal or output enable signal, or generation delay of control signal.
Description
Technical field
The present invention relates to electronic technology field, relate in particular to a kind of device and method of external memory controller timing configuration.
Background technology
External memory controller is applicable to the various types of read-write operation that is similar to the various memory devices of asynchronous memory (storer) interface of control as a kind of general memory interface.
When its read-write operation is controlled, normally used control signal has output enable signal (OEN), writes enable signal (WEN) and chip selection signal (CS), generation OEN that provides in the prior art or the controlled variable of WEN mostly are to write and enable delay parameter or output enable delay parameter, wherein, write and enable delay parameter for writing the effective start time of enable signal with respect to the effective time delay of CS, the output enable delay parameter is that the effective start time of output enable signal is with respect to the effective time delay of CS; To not limiting the ineffective time of writing enable signal or output enable signal, because different memory is to the requirement difference in time sequential routine, as may be before the CS invalidating signal OEN signal should to shift to an earlier date some cycles invalid, may cause like this time sequential routine of external memory storage is not met system requirements, feasible basis is write the write enable signal or output enable jitter or control signal (comprise and write enable signal or output enable signal) that enable delay parameter or the generation of output enable delay parameter and is generated time-delay, and influence is to the control of current storage;
In addition,, make sequential configuration underaction, cause the control of writing enable signal or output enable signal singlely, as write enable signal always latchs the output clock with respect to CS negative edge output because configurable parameter area is too little.
Have again,, can not control, make storer can not cooperate display screen effectively to work, for the operation of control store brings certain difficulty display screen module (as color LCD control module) according to the prior art scheme.
It can be seen from the above, and there is following defective in the prior art scheme:
Not comprehensive to effective control of writing enable signal or output enable signal, cause the time sequential routine of external memory storage is not satisfied the sequential requirement, cause the generation time-delay of writing enable signal or output enable jitter or control signal (comprise and write enable signal or output enable signal), influence is to the control of current storage;
Sequential configuration underaction is single to the control of writing enable signal or output enable signal;
Storer can not cooperate the proprietary module work of display screen, for the operation of control store brings difficulty.
Summary of the invention
Embodiments of the invention provide a kind of device and method of external memory controller timing configuration, it is not comprehensive to have solved the effective control to writing enable signal or output enable signal that exists in the prior art, cause the time sequential routine of external memory storage is not satisfied the sequential requirement, and sequential configuration underaction, to writing the single defective of control of enable signal or output enable signal.
Embodiments of the invention are to be achieved through the following technical solutions:
A kind of device of external memory controller timing configuration comprises:
The configuration register interface module is used for the parameter according to current storage, and configuration generates the Invalid parameter and the controlled variable in advance of control signal, and chip selection signal;
Time-sequence control module is used for Invalid parameter and controlled variable in advance according to described control signal, is that benchmark generates control signal with the chip selection signal; Described control signal comprises writes enable signal and/or output enable signal.
A kind of method of external memory controller timing configuration comprises:
According to the parameter of current storage, generate the Invalid parameter and the controlled variable in advance of control signal, and chip selection signal;
According to the Invalid parameter and the controlled variable in advance of described control signal, be that benchmark generates control signal with the chip selection signal; Described control signal comprises writes enable signal and/or output enable signal.
The technical scheme that is provided by the embodiment of the invention described above as can be seen, embodiments of the invention provide a kind of device and method of external memory controller timing configuration, avoided not comprehensive to effective control of writing enable signal or output enable signal, and the sequential of external memory storage requires not meet system requirements, cause and write enable signal or output enable jitter or control signal (comprise and write enable signal or output enable signal) generation time-delay, influence is to the problem of the control of current storage, thereby reach the flexible configuration external memory controller timing, control the generation of control signal flexibly.
Description of drawings
The structural representation of the device that the external memory controller timing that Fig. 1 provides for embodiments of the invention disposes;
The structural representation block diagram of the external memory controller that Fig. 2 provides for the embodiment of the invention;
The time-sequence control module that Fig. 3 provides for the embodiment of the invention generates the sequential synoptic diagram of output enable control signal;
The time-sequence control module that Fig. 4 provides for the embodiment of the invention generates writes the sequential synoptic diagram that enables control signal;
The time-sequence control module that Fig. 5 provides for the embodiment of the invention generates the sequential synoptic diagram of screen display control signal.
Embodiment
Embodiments of the invention provide a kind of device of external memory controller timing configuration, its structural representation as shown in Figure 1, the structural representation of the device that the external memory controller timing that Fig. 1 provides for embodiments of the invention disposes comprises configuration register interface module and time-sequence control module;
Described configuration register interface module is used for the parameter according to current storage, and configuration generates the Invalid parameter and the controlled variable in advance of control signal, and the CS signal;
Described time-sequence control module is used for Invalid parameter and controlled variable in advance according to the control signal that receives, is that benchmark generates control signal with the CS signal; Described control signal comprises writes enable signal and/or output enable signal.
Described configuration register interface module comprises Invalid parameter generation module, controlled variable generation module and chip selection signal generation module in advance, wherein:
The Invalid parameter generation module is used for the parameter according to current storage in advance, and configuration generates the Invalid parameter in advance of control signal;
The controlled variable generation module is used for the parameter according to current storage, and configuration generates the controlled variable of control signal; Described controlled variable comprises effective delay parameter and edge controlled variable at least;
The chip selection signal generation module is used to generate CS (sheet choosing) signal; Can by configuration CS signal effective time window length and the time interval between adjacent two CS signal windows effective time, and according to the CS signal effective time window length and the time interval between adjacent two CS signal windows effective time, generate the CS signal.
Described time-sequence control module comprises writes enable signal generation module, output enable signal generation module, wherein,
The described enable signal generation module of writing is used for according to described effective delay parameter, described edge controlled variable and described Invalid parameter in advance, is that enable signal is write in the benchmark generation with the CS signal;
Described output enable signal generation module is used for according to described effective delay parameter and described Invalid parameter in advance, is that benchmark generates the output enable signal with the CS signal.
Described controlled variable at least also comprises the controlled variable of screen display control signal;
Described time-sequence control module can also comprise screen display control signal module;
Described screen display control signal module is used for the controlled variable according to described screen display control signal, is that benchmark generates the screen display control signal with the CS signal.Described screen display control signal is the control signal that shows the data of current storage on display.
Here need to prove that the Invalid parameter in advance of described control signal (comprise the output enable signal and/or write enable signal) can obtain by the software arrangements hardware parameter, the controlled variable of control signal also can obtain by the software arrangements hardware parameter; The effective delay parameter of the control signal in the foregoing can also can be the hysteresis actual parameter of control signal for the actual parameter in advance of control signal.
For the ease of understanding the technical scheme that embodiments of the invention provide, the technical scheme that embodiments of the invention provide is described below in conjunction with specific embodiments, its structural representation block diagram as shown in Figure 2:
In this embodiment, device of the present invention (being the EMI module) comprises configuration register interface module (AHB_REG_IF) and time-sequence control module (Delay timer);
The configuration register interface module is used for the parameter according to current storage, generate the needed delay parameter of sequential control, described delay parameter comprises the controlled variable of control signal, the Invalid parameter and the CS signal in advance of control signal, described controlled variable comprises the effective delay parameter and the edge controlled variable of control signal at least, and described controlled variable can also comprise the controlled variable of screen display control signal; Described control signal comprises writes enable signal and/or output enable signal, and the controlled variable of described screen display control signal comprises screen display control signal rising delay parameter and screen display control signal fall delay parameter; Transmit described delay parameter to time-sequence control module;
In this embodiment, by the configuration sheet select the CS signal effective time window length and the time interval between adjacent two CS signal windows effective time, and according to the CS signal effective time window length and the time interval between adjacent two CS signal windows effective time, generate the CS signal.
Time-sequence control module is used for according to the delay parameter of configuration register interface module to its transmission, generation is write enable signal (WEN) and/or output enable signal (OEN) to what current storage was controlled, also can generate the screen display control signal simultaneously according to the delay parameter of configuration register interface module transmission.
Time-sequence control module comprises writes enable signal generation module, output enable signal generation module and screen display control signal generation module;
Write the enable signal generation module, be used for the Invalid parameter in advance of writing enable signal that receives according to it, write the actual parameter in advance of enable signal and the edge controlled variable of writing enable signal, with the CS signal is that enable signal is write in benchmark (is to write the starting point of enable signal as the starting point with CS window effective time) generation, the described Invalid parameter in advance of writing enable signal is generated by the Invalid parameter generation module in advance in the configuration register module, the described actual parameter in advance of writing enable signal is generated by the controlled variable generation module in the configuration register module, and the described edge controlled variable of writing enable signal is also generated by the controlled variable generation module in the configuration register module; Write the enable signal generation module and enable signal is write in its generation directly exported to pin (PAD or Pin), use for external memory storage;
Output enable signal generation module is used for the Invalid parameter in advance of the output enable signal that receives according to it and the actual parameter in advance of output enable signal, with the CS signal is that benchmark (is the starting point of output enable signal as the starting point with CS window effective time) generates the output enable signal, the Invalid parameter in advance of described output enable signal is generated by the Invalid parameter generation module in advance in the configuration register module, and the actual parameter in advance of described output enable signal is generated by the controlled variable generation module in the configuration register module; Output enable signal generation module generates the output enable signal with it and directly exports pin (PAD or Pin) to, uses for external memory storage;
The controlled variable that screen display control signal generation module is used for the screen display control signal that receives according to it generates the screen display control signal, among this embodiment, the controlled variable of described screen display control signal comprises screen control signal rising delay parameter and screen display control signal fall delay parameter, and system can will expand to the control of external memory storage by the screen display control signal and show control; Screen display control signal generation module directly exports the screen display control signal of its generation to pin (PAD or Pin), uses for external memory storage.
Embodiments of the invention also provide a kind of method of external memory controller timing configuration, and the technical scheme of described method comprises:
According to the parameter of current storage, generate the Invalid parameter and the controlled variable in advance of control signal, and the CS signal; Described controlled variable comprises the effective delay parameter and the edge controlled variable of control signal at least; Can by configuration CS signal effective time window length and the time interval between adjacent two CS signal windows effective time, and according to the CS signal effective time window length and the time interval between adjacent two CS signal windows effective time, generate the CS signal.
According to the Invalid parameter and the controlled variable in advance of the control signal that receives, be that benchmark generates control signal with the CS signal; Described control signal comprises the output enable signal and/or writes enable signal.According to described effective delay parameter, edge controlled variable and Invalid parameter in advance, being that benchmark generates and writes enable signal with the CS signal; According to described effective delay parameter and described Invalid parameter in advance, be that benchmark generates the output enable signal with the CS signal.Described controlled variable at least also comprises the controlled variable of screen display control signal; According to the controlled variable of described screen display control signal, be that benchmark generates the screen display control signal with the CS signal.
Next the concrete steps that generate the output enable signal according to described method, write enable signal and screen display control signal are described:
At first, in conjunction with Fig. 3 the sequential that generates output enable control signal OEN is described; What HCLK represented among Fig. 3 is bus clock signal, what EMI-CS represented is the chip selection signal of EMI, what EMI-OEN represented is the output enable signal of EMI output, what Tcycle represented is bus clock cycle, what Tcsvr represented is the time of bus read access latent period, what Tturnaround represented is the time of external memory storage operation Tturnaround, what Tcsrd represented is that EMI-CS effectively arrives effective time delay of EMI-OEN, what Trdcs represented is invalid pre-set time of the invalid EMI-CS of arriving of EMI-OEN, what Toed represented is that this begins EMI-OEN constantly effectively until Toeid from Toed, Toeid represents be from Toeid this to begin EMI-OEN constantly invalid until next Toed constantly;
When the EMI-CS negative edge arrived, EMI-CS was effective, and through Tcsrd, it is effective that rising edge of clock signal triggers EMI-OEN, effective when promptly the EMI-OEN negative edge arrives; In the Trdcs moment before the rising edge of EMI-CS arrives, it is invalid that rising edge of clock signal triggers EMI-OEN, invalid when promptly the EMI-OEN rising edge arrives;
Hence one can see that, EMI-OEN generates according to EMI-CS, Tcsrd and Trdcs, because the accurate control of these two parameters of Tcsrd and Trdcs is arranged, and Tcsrd and these two parameters of Trdcs can be configured at any time as required, not only can generate EMI-OEN exactly, simultaneously also improve the sequential configuration flexibility, increased the dirigibility that generates EMI-OEN; Here need to prove Tcsrd and Trdcs also can be by EMI-OEN effectively with respect to the invalid time parameter of EMI-CS or EMI-OEN is invalid replaces with respect to the effective time parameter of EMI-CS, can play the effect identical equally with Tcsrd and Trdcs.
Next, the sequential of enable signal WEN being write in generation in conjunction with Fig. 4 describes; What HCLK represented among Fig. 4 is bus clock signal, what EMI-CS represented is the chip selection signal of EMI, what EMI-WEN represented is the enable signal of writing of EMI output, what Tcycle represented is bus clock cycle, what Tcsvw represented is that (cycle of saying here refers to bus clock cycle to bus write access latent period, be Tcycle) number, what Tcd represented is the effective output delay time of EMI-CS, what Tcid represented is the invalid output delay time of EMI-CS, what Tcswr represented is that EMI-CS effectively arrives effective time delay of EMI-WEN, what Twrcs represented is invalid pre-set time of the invalid EMI-CS of arriving of EMI-WEN, what Twd represented is that this begins EMI-WEN constantly effectively until Twid from Twd, Twid represents be from Twid this to begin EMI-WEN constantly invalid until next Twd constantly;
When the EMI-CS negative edge arrived, EMI-CS was effective, and through Tcswr, it is effective that the negative edge of clock signal triggers EMI-WEN, and EMI-WEN was effective when promptly the negative edge of EMI-WEN signal arrived; In the Twrcs moment before the rising edge of EMI-CS arrives, it is invalid that the negative edge of clock signal triggers EMI-WEN, and EMI-WEN was invalid when promptly the rising edge of EMI-WEN signal arrived;
Hence one can see that, EMI-WEN generates according to EMI-CS, Tcswr and Twrcs, because the accurate control of Tcswr and these parameters of Twrcs is arranged, and Tcswr and these two parameters of Twrcs can be configured at any time as required, not only can generate EMI-WEN exactly, simultaneously also improve the sequential configuration flexibility, increased the dirigibility that generates EMI-WEN; Here need to prove Tcswr and Twrcs also can be by EMI-WEN effectively with respect to the invalid time parameter of EMI-CS or EMI-WEN is invalid replaces with respect to the effective time parameter of EMI-CS, can play the effect identical equally with Tcswr and Twrcs.
At last, in conjunction with Fig. 5 the sequential that generates screen display control signal Strobe is described; What HCLK represented among Fig. 5 is bus clock signal, what EMI-CS represented is the chip selection signal of EMI, what EMI-PRB-EN represented is the screen display control signal of EMI output, what Tcycle represented is bus clock cycle, what Tcsvw represented is that (cycle of saying here refers to bus clock cycle to bus write access latent period, be Tcycle) number, what Tsd represented is the effective output delay time of EMI-PRB-EN, what Tsid represented is the invalid output delay time of EMI-PRB-EN, Tsh represents be EMI-PRB-EN effectively with respect to EMI-CS effective time delay, Tsl represents is that EMI-PRB-EN is invalid with respect to EMI-CS effective time delay;
When the EMI-CS negative edge arrived, EMI-CS was effective, and through Tsh, it is effective that rising edge of clock signal triggers EMI-PRB-EN, and EMI-PRB-EN was effective when promptly the rising edge of EMI-PRB-EN signal arrived; In the Tsl moment after the negative edge of EMI-CS arrives, it is invalid that rising edge of clock signal triggers EMI-PRB-EN, and EMI-PRB-EN was invalid when promptly the negative edge of EMI-PRB-EN signal arrived;
Hence one can see that, EMI-PRB-EN generates according to EMI-CS, Tsh and Tsl, because the accurate control of Tsh and Tsl is arranged, and Tsh and Tsl can be configured at any time as required, not only can generate EMI-PRB-EN exactly, simultaneously also improve the sequential configuration flexibility, increased the dirigibility that generates EMI-PRB-EN;
Here need to prove that Tsh and/or Tsl also can be by invalid parameter substitutions pre-set time invalid with respect to EMI-CS of EMI-PRB-EN, can play equally be similar to Tsh and/effect of Tsl.
Comprehensively above-mentioned, embodiments of the invention provide a kind of device and method of external memory controller timing configuration, avoided effective control not comprehensive of control signal, cause control signal instability or control signal (comprise and write enable signal and/or output enable signal) to generate the problem of time-delay, improved the external memory controller timing configuration flexibility, guarantee the timely output of control signal, also will expand to demonstration control simultaneously the control of external memory storage.
So far; the present invention only is operating as the technical scheme that example has illustrated that the embodiment of the invention provides with reading and writing; but the present invention is not only limited to the generative process of the control signal of mentioning in the embodiment of the invention; all are based on the Invalid parameter in advance according to the control signal that receives; the control lag parameter that cooperates control signal; with the CS signal is the technical scheme that benchmark generates control signal, no matter which kind of form of employing, all within protection scope of the present invention.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the conversion that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claims.
Claims (9)
1, a kind of device of external memory controller timing configuration is characterized in that, comprising:
The configuration register interface module is used for the parameter according to current storage, and configuration generates the Invalid parameter and the controlled variable in advance of control signal, and chip selection signal;
Time-sequence control module is used for Invalid parameter and controlled variable in advance according to described control signal, is that benchmark generates control signal with the chip selection signal; Described control signal comprises writes enable signal and/or output enable signal.
2, device according to claim 1 is characterized in that, described configuration register interface module comprises:
The Invalid parameter generation module is used for the parameter according to current storage in advance, and configuration generates the Invalid parameter in advance of control signal;
The controlled variable generation module is used for the parameter according to current storage, and configuration generates the controlled variable of control signal; Described controlled variable comprises the effective delay parameter and the edge controlled variable of control signal at least;
The chip selection signal generation module is used to generate chip selection signal.
3, device according to claim 2 is characterized in that, described time-sequence control module comprises writes enable signal generation module and output enable signal generation module;
Writing the enable signal generation module, be used for according to described effective delay parameter, edge controlled variable and Invalid parameter in advance, is that benchmark generates and writes enable signal with the chip selection signal;
Output enable signal generation module is used for according to described effective delay parameter and Invalid parameter in advance, is that benchmark generates the output enable signal with the chip selection signal.
4, device according to claim 3 is characterized in that, described controlled variable also comprises the controlled variable of screen display control signal, and described time-sequence control module further comprises:
Screen display control signal module is used for the controlled variable of the screen display control signal that receives according to it, is that benchmark generates the screen display control signal with the chip selection signal.
5, device according to claim 2, it is characterized in that, described chip selection signal generation module is the first chip selection signal generation module, be used to dispose chip selection signal effective time window length and the time interval between adjacent two chip selection signal windows effective time, and according to chip selection signal effective time window length and the time interval between adjacent two chip selection signal windows effective time, generate chip selection signal.
6, a kind of method of external memory controller timing configuration is characterized in that, comprising:
According to the parameter of current storage, generate the Invalid parameter and the controlled variable in advance of control signal, and chip selection signal;
According to the Invalid parameter and the controlled variable in advance of described control signal, be that benchmark generates control signal with the chip selection signal; Described control signal comprises writes enable signal and/or output enable signal.
7, method according to claim 6 is characterized in that, described controlled variable comprises the effective delay parameter and the edge controlled variable of control signal at least;
According to the in advance Invalid parameter and the controlled variable of described control signal, be that the step that benchmark generates control signal comprises with the chip selection signal:
According to described edge controlled variable, in advance Invalid parameter and effective delay parameter, be that benchmark generates and writes enable signal with the chip selection signal;
According to described Invalid parameter and effective delay parameter in advance, be that benchmark generates the output enable signal with the chip selection signal.
8, method according to claim 7 is characterized in that, described controlled variable also comprises the controlled variable of screen display control signal;
According to the in advance Invalid parameter and the controlled variable of described control signal, be that the step that benchmark generates control signal also comprises with the chip selection signal:
According to the controlled variable of described screen display control signal, be that benchmark generates the screen display control signal with the chip selection signal.
9, method according to claim 6 is characterized in that, the generation step of described chip selection signal is:
The configuration chip selection signal effective time window length and the time interval between adjacent two chip selection signal windows effective time;
According to chip selection signal effective time window length and the time interval between adjacent two chip selection signal windows effective time, generate chip selection signal.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101859289A (en) * | 2010-06-11 | 2010-10-13 | 华中科技大学 | Off-chip memory access controller |
| CN102810053A (en) * | 2011-05-30 | 2012-12-05 | 联咏科技股份有限公司 | Display interface circuit |
| CN103052948A (en) * | 2010-07-07 | 2013-04-17 | 马维尔国际贸易有限公司 | Interface management control systems and methods for non-volatile semiconductor memory |
| CN103593312A (en) * | 2012-08-13 | 2014-02-19 | 炬力集成电路设计有限公司 | Time sequence control method and NAND FLASH controller |
| US9135168B2 (en) | 2010-07-07 | 2015-09-15 | Marvell World Trade Ltd. | Apparatus and method for generating descriptors to reaccess a non-volatile semiconductor memory of a storage drive due to an error |
| US9141538B2 (en) | 2010-07-07 | 2015-09-22 | Marvell World Trade Ltd. | Apparatus and method for generating descriptors to transfer data to and from non-volatile semiconductor memory of a storage drive |
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2007
- 2007-03-28 CN CNB2007100794701A patent/CN100511193C/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101859289A (en) * | 2010-06-11 | 2010-10-13 | 华中科技大学 | Off-chip memory access controller |
| CN103052948A (en) * | 2010-07-07 | 2013-04-17 | 马维尔国际贸易有限公司 | Interface management control systems and methods for non-volatile semiconductor memory |
| US9135168B2 (en) | 2010-07-07 | 2015-09-15 | Marvell World Trade Ltd. | Apparatus and method for generating descriptors to reaccess a non-volatile semiconductor memory of a storage drive due to an error |
| US9141538B2 (en) | 2010-07-07 | 2015-09-22 | Marvell World Trade Ltd. | Apparatus and method for generating descriptors to transfer data to and from non-volatile semiconductor memory of a storage drive |
| US9183141B2 (en) | 2010-07-07 | 2015-11-10 | Marvell World Trade Ltd. | Method and apparatus for parallel transfer of blocks of data between an interface module and a non-volatile semiconductor memory |
| CN103052948B (en) * | 2010-07-07 | 2016-08-17 | 马维尔国际贸易有限公司 | Interface management control system and method for nonvolatile semiconductor memory |
| CN102810053A (en) * | 2011-05-30 | 2012-12-05 | 联咏科技股份有限公司 | Display interface circuit |
| CN103593312A (en) * | 2012-08-13 | 2014-02-19 | 炬力集成电路设计有限公司 | Time sequence control method and NAND FLASH controller |
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| CN100511193C (en) | 2009-07-08 |
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