CN115202438B - Implementation method of full-synchronous eFlash controller based on single clock - Google Patents

Abstract

The invention discloses a method for realizing a full-synchronous eFlash controller based on a single clock, which comprises the following steps: acquiring the configuration information of the system to the clock by using the clock and the reset signal of the bus subsystem, acquiring the ideal working clock frequency at the moment, and using the value of the ideal working clock frequency as the address of a lookup table; the method comprises the steps that a clock frequency detection logic is configured for an eFlash controller, the clock frequency detection logic outputs a clock state signal, and when a clock is unstable, the eFlash controller logic cannot execute any control; taking each operation mode as a primary state machine, taking each IO signal mode in a corresponding time sequence as a secondary state machine, and reserving an entrance condition and an exit condition for each secondary state machine; designing a corresponding lookup table for timing IO state change time periods; synchronizing a bus clock with a logic control clock; the invention solves the problem of realizing the interface time sequence control of the eFlash controller by using a single clock.

Description

Implementation method of full-synchronous eFlash controller based on single clock

Technical Field

The invention relates to the technical field of embedded memories, in particular to a method for realizing a full-synchronous eFlash controller based on a single clock.

Background

Embedded flash memory technology: embedded flash eeflash technology is a flash memory device that can be integrated with chip digital logic, and has the advantages of providing non-volatile storage, high read speed making it XIP (in-memory execution) support, small chip area and low power consumption. The common eFlash device consists of 2-tube storage particles, a charge pump and matched voltage isolation, an address decoder and IP internal control.

The operation mode and interface sequential control required by the eFlash, besides reading, programming, erasing/full erasing supported by a general flash memory, also comprises some special low-power consumption modes, low-voltage modes, special area access and logic control operation in the flash memory, all need to be completed by a user through controlling an IO interface of an eFlash device, and in order to complete the operation, IO needs to be controlled to change for a plurality of times within a strictly specified time range according to a specific value. The device user (hereinafter referred to as user) often needs to construct a set of digital logic by himself to accomplish the above control.

And changing the value of each IO within a strictly specified time range, wherein one satisfying method is to select a clock on a chip, and change the value of the IO according to the condition that the clock period is multiplied by a count value to meet the time requirement as a judgment basis. Many eFlash controllers are designed to provide an unchanging clock for each of programming, erasing, reading and other operations, which are asynchronous to each other, and obviously, such designs require at least 2 clocks.

However, clock sampling which is asynchronous to each other inevitably has the possibility of metastable state propagation, and for asynchronous processing of control signals and data, a lot of asynchronous signal/data processing logic is needed, so that the stability and the real-time performance of the system are reduced, and more randomness and logic resource consumption are introduced.

Disclosure of Invention

In order to solve the problems in the prior art, the invention aims to provide a method for realizing a full-synchronous eFlash controller based on a single clock, and the method solves the problem of realizing the interface time sequence control of the eFlash controller by using the single clock.

In order to achieve the purpose, the invention adopts the technical scheme that: a method for realizing a full synchronous eFlash controller based on a single clock comprises the following steps:

the method comprises the steps that the clock and reset signals of a bus subsystem where a controller is located are used for obtaining configuration information of the system to the clock, namely the eFlash controller is considered to have obtained ideal working clock frequency at the moment, and the value of the ideal working clock frequency is used as an address of a lookup table;

the method comprises the steps that a clock frequency detection logic is equipped for an eFlash controller, a clock of a high-precision crystal oscillator is used for detecting the bus clock frequency used by the eFlash controller, the clock frequency detection logic outputs a clock state signal, and when the clock is unstable, the eFlash controller logic cannot execute any control;

taking each operation mode as a primary state machine, taking each IO signal mode in a time sequence corresponding to each operation mode as a secondary state machine, and reserving an entrance condition and an exit condition for each secondary state machine;

selecting a corresponding maximum timing period divided by a clock period for timing the IO state change time period, and designing a corresponding lookup table;

the bus clock is synchronized with the logic control clock.

As a further improvement of the invention, when the Timer step is selected, if the bit width exceeds the performance allowed by the process, the bit width needs to be split.

As a further improvement of the invention, the method also comprises the following steps:

the register output is set for the IO signal of each eFlash controller, the register output is driven by the main clock and controlled by the clock state signal and the system reset signal, and the register output is used for resetting the IO state of the eFlash controller at the first time when an error occurs in the system so as to prevent the eFlash controller from being damaged due to the continuous error IO state.

The invention has the beneficial effects that:

1. asynchronous signal interaction may have metastable state transmission, which causes system misjudgment of memory state or error control on the memory; the fully synchronous logic design can avoid metastable transmission and reduce the occurrence of random and unknown conditions; namely, the invention can reduce the system failure caused by the failure of the eFlash controller and the damage of the memory caused by the system failure.

2. The invention increases a clock frequency detection logic cooperation mechanism and improves the system safety.

3. The invention saves hardware resources such as counters and synchronous processing logic.

4. In engineering practice, IO of logic control eFlash controllers of different clock domains can seriously increase the complexity of time sequence analysis, and the full synchronous logic design can effectively reduce the complexity of time sequence analysis and time sequence risk, namely the invention can effectively reduce the complexity of complex time sequence convergence in the development process.

5. The invention adapts to more automated controls or configurations.

6. At the end of the memory life, the charge and discharge time can be corrected to compensate for the operation failure caused by the aging of the device to a certain extent.

7. When the program performance is analyzed, the designed clock can keep the same frequency with the CPU, so that the program execution performance can be accurately calculated by the Cycle-by-Cycle, and the execution time has higher consistency when the Cycle is executed.

Drawings

FIG. 1 is a control logic architecture of an eFlash controller in an embodiment of the present invention;

FIG. 2 is a block diagram of a state machine according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating the relationship between the IO state timing and the timing cycle in a certain mode according to an embodiment of the present invention;

FIG. 4 is a timing diagram illustrating an IO timing diagram of an erase operation of an actual eFlash controller according to an embodiment of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Examples

A method for realizing a full synchronous eFlash controller based on a single clock comprises the following steps:

clock design: the clock and the reset signal of the bus subsystem where the controller is located are directly used to obtain the configuration information of the system to the clock, namely, the eFlash controller is considered to have obtained the ideal working clock frequency at the moment, and the value can be used as the address of a lookup table.

Clock frequency detection logic (hereinafter Clock Failure detection, CFD logic): in order to ensure that the clock information of the work of the eFlash controller is the same as or substantially the same as the expected clock frequency, the embodiment provides a clock frequency detection logic for the control logic of the eFlash controller, the CFD logic adopts a conventional method, and uses a measurement clock of a high-precision crystal oscillator, as shown in (1) in fig. 1, the control logic of the eFlash controller detects the bus clock frequency used by the eFlash controller, outputs a clock status signal according to the CFD logic, and cannot perform any control when the clock is unstable.

As shown in FIG. 2, the eFlap ip provider provides the eFlap ip with a list of operating mode states similar to that shown in Table 1, and a timing sequence similar to that shown in the bottom half of FIG. 3, each operating mode being used as a primary state machine, e.g., the respective mode in FIG. 2, and each IO signal mode in the timing sequence corresponding to each operating mode being used as a secondary state machine, e.g., the respective IO state in FIG. 2, each secondary state reserving an entry condition and an exit condition, e.g., (2) and (6) in FIG. 1.

TABLE 1 modes of operation and IO states

Timer: and timing the IO state change time period, and selecting the corresponding maximum timing period divided by the clock period from the Timer step length. If the bit width exceeds the performance allowed by the process, the bit width needs to be split. As shown in fig. 2, the timing period corresponding to each IO state is divided by the value of a certain clock frequency, and a corresponding lookup table is designed, so that for various bus frequencies, even the bus frequency information may be used as an address, corresponding to the multi-row table shown in table 2, only one set of Timer resources is required in this embodiment.

TABLE 2 frequency Point vs. count step number relationship

With the user's knowledge of the risk and the setting method, the number of counting cycles required to complete the timing sequence can be actively changed to promote the high voltage endurance events of programming or erasing, the read access events, etc., as shown in (4) and (5) of fig. 1.

A memory interface: as shown in (3) of fig. 1, the present embodiment sets a register output for each eFlash IO signal, is driven by the master clock, and is controlled by the clock status signal and the system reset signal. When an error occurs in the system, the eFlash IO is reset at the first time to prevent the eFlash device from being damaged due to the continuous state of the error IO.

Control interface (bus interface): the bus clock is synchronous with the logic control clock, and the bus interface design method provided by the embodiment is beneficial to maximizing the programming, erasing and reading modes determined by utilizing the physical structure of the eFlash device.

During programming, a buffer larger than the eFlash row size, a starting address and an ending address can be provided for the input data.

When erasing, a start block address and an end block address which need to be erased are provided.

By using the automatic state switching of the state machine, the CPU can automatically complete the erasing and programming of the target without extra waiting.

During reading, the eFlash controller logic disassembles/splices the data read out once into data matched with the bit width of the bus. The eFlash control logic and the external cache can realize clock synchronization, and the analysis of the data state in the system cache is facilitated.

The above is the method for implementing the whole eFlash controller shown in fig. 1 in this embodiment, except for the clock detection logic, asynchronous processing is not required for all control streams and data streams of the eFlash device.

The following further describes the embodiment by taking a dual AHB Slave interface and a full-synchronous eFlash controller based on an eFlash device as an example:

two AMBA3.0ahb Lite interfaces have completely synchronous clocks and resets and are respectively responsible for configuring eflash control logic or sending instructions (hereinafter, referred to as AHBC) and reading and writing data (hereinafter, referred to as AHBD), wherein the AMBA comprises four different bus standards, which are respectively: AHB, ASB, APB, AXI; the present embodiment uses the AHB lite bus interface version AMBA 3.0.

Clock and reset, directly fetch AHB bus clock and reset HCLK and HRESETN. The configuration of the relevant clock controller to the PLL corresponds one-to-one to the clock frequency: typically the frequency of the OSC is doubled, e.g. 100MHz for a decimal number of 4.

The clock of the clock frequency detection logic directly uses the output clock from the high-precision OSC of the system or other credible precision clocks.

After detection, the stability of HCLK is known, and the output of clock state has the following characteristics:

when the chip is powered on, the OSC does not start oscillation, the clock state is unstable, and the eFlash control logic does not perform any action;

after OSC oscillation starting, PLL is not locked, the clock state is unstable, and the eFlash control logic does not perform any action;

detecting that the HCLK frequency is inconsistent with the configuration, the clock state is unstable, and the eFlash control logic does not perform any action;

when the HCLK is detected to be in the configuration range, the clock state is stable, and the eFlash control logic can work;

for the one-level state machine, in order to ensure system stability and efficiency, the instructions of the AHBC interface should be responded to with a priority of priority power control > read > erase > programming. The entry of the state machine is an operation instruction and the exit is an indication that the operation is complete

For the secondary state machine, the IO timing sequence required by the specification of some eFlash device is analyzed, for example as shown in fig. 4,

in one erasing process, six sections of IO states are required; then 6 states are added accordingly:

TWS (setup time clocking state of CEb signal to ERASE signal rising edge);

TNVS (setup time clocking state of ERASE signal to WEb signal falling edge);

TERASE (low time count state of WEb signal);

TRCV (ERASE times on the rise of the WEb signal);

TWH (hold time clocking state of NVR/ARRDN/NVR _ CFG signal to ERASE signal falling edge);

TRW (hold time clocking state of CEb signal to ERASE signal falling edge);

they switch in sequence, the switching condition being that the count reaches the comparison value.

And after the TRW state, switching the subsequent state along the path of the first-level state machine according to the instruction of the AHBC interface.

For the timer, referring to table 3, bit width is set according to the maximum count value required by the counter to complete timing, CFG is configured for each frequency point in the system corresponding to one clock, and the number of times counted for each IO state is also calculated in the design process and set in the register as the maximum value reference for each IO state timing.

The value can be manually set through an AHBC interface, so that a margin can be reserved conveniently, and longer erasing/programming time is used at the end of the service life of the eFlash device to ensure successful operation.

TABLE 3 frequency point of a practical eflash device versus count value of the required timing for erase operation

Furthermore, the fully synchronous clock design and the state machine inlet and outlet ensure the excellent time sequence design from the eFlash control logic to the eFlash IO interface, each bit of control signal is driven by the synchronous clock, is sensitive to the state of the state machine, and outputs/samples the eFlash IO signal.

The above-mentioned embodiments only express the specific embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.

Claims (3)

1. A method for realizing a full synchronous eFlash controller based on a single clock is characterized by comprising the following steps:

the method comprises the steps that the clock and reset signals of a bus subsystem where a controller is located are used for obtaining configuration information of the system to the clock, namely the eFlash controller is considered to have obtained ideal working clock frequency at the moment, and the value of the ideal working clock frequency is used as an address of a lookup table;

the method comprises the steps that a clock frequency detection logic is configured for an eFlash controller, a clock of a high-precision crystal oscillator is used for detecting the bus clock frequency used by the eFlash controller, the clock frequency detection logic outputs a clock state signal, and when the clock is unstable, the eFlash controller logic cannot execute any control;

taking each operation mode as a primary state machine, taking each IO signal mode in a time sequence corresponding to each operation mode as a secondary state machine, and reserving an entrance condition and an exit condition for each secondary state machine;

selecting a corresponding maximum timing period divided by a clock period for timing the IO state change time period, and designing a corresponding lookup table;

the bus clock is synchronized with the logic control clock.

2. The method for implementing the single-clock-based full synchronous eFlash controller according to claim 1, wherein when the Timer step is selected, if the bit width exceeds the performance allowed by the process, the bit width needs to be split.

3. The implementation method of the single-clock-based fully synchronous eFlash controller as claimed in claim 1 or 2, further comprising:

the register output is set for the IO signal of each eFlash controller, the register output is driven by the main clock and controlled by the clock state signal and the system reset signal, and the register output is used for resetting the IO state of the eFlash controller at the first time when an error occurs in the system so as to prevent the eFlash controller from being damaged due to the continuous error IO state.

Images