CN101017818A - ESD protection circuit for enlarging the valid circulation area of the static current - Google Patents
ESD protection circuit for enlarging the valid circulation area of the static current Download PDFInfo
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- CN101017818A CN101017818A CN 200710067516 CN200710067516A CN101017818A CN 101017818 A CN101017818 A CN 101017818A CN 200710067516 CN200710067516 CN 200710067516 CN 200710067516 A CN200710067516 A CN 200710067516A CN 101017818 A CN101017818 A CN 101017818A
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Abstract
The related static discharge protection circuit comprises: above the trap area, setting a multicrysta silicon layer and a SiO2 layer every with length not less than distance between the N-trap P+ injection area side wall near P-trap and the P-trap N+ injection area side wall near N-trap, and setting throughole on former two layers corresponding to the injection area. Unlike to current thyristor SCR method, this invention increases effective area for fast discharging, and improves the static tolerance capacity for the static discharge circuit.
Description
Technical field
The invention belongs to technical field of integrated circuits, particularly a kind of under the condition that does not change technology, save layout, increase the release electrostatic storage deflection (ESD) protection circuit of effective area of electrostatic induced current.
Background technology
Static discharge is under the situation of an integrated circuit suspension joint, and a large amount of electric charges pours into the instantaneous process of integrated circuit from outside to inside, the about 100ns consuming time of whole process.In addition, can produce the high pressure of hundreds if not thousands of volts when integrated circuit discharges, this can punch the gate oxide of the input stage in the integrated circuit.Along with the size of the metal-oxide-semiconductor in the integrated circuit is more and more littler, the thickness of gate oxide is also more and more thinner, and under this trend, to be without prejudice be very essential with the protection grid oxic horizon for the electric charge of static discharge to use high performance electrostatic discharge protection circuit to release.
The pattern of static discharge phenomenon mainly contains four kinds: human body discharge mode (HBM), mechanical discharge mode (MM), part charging mode (CDM) and electric field induction pattern (FIM).Concerning general integrated circuit (IC) products, generally to pass through human body discharge mode, the test of mechanical discharge mode and part charging mode.In order to bear so high static discharge voltage, integrated circuit (IC) products must be used the electrostatic discharge protector with high-performance, high tolerance usually.
Resist the purpose that static attacks in order to reach the protection chip; at present existing multiple electrostatic protection device is suggested; such as diode, the metal-oxide-semiconductor of grounded-grid generally acknowledges that wherein the reasonable protective device of effect is controllable silicon SCR (silicon controlled rectifier).The concrete structure of this protective device is a well region on the P type substrate 11 as shown in Figure 1, and well region comprises N trap 12 and P trap 16, and two injection regions are all arranged on N trap 12 and the P trap 16, is respectively N+ injection region 14 and P+ injection region 15.Wherein the N+ injection region of N trap 12 is arranged on the end away from P trap 16, and the P+ injection region is arranged on the end near P trap 16; The P+ injection region of P trap 16 is arranged on the end away from N trap 12, and the N+ injection region is arranged on the end near N trap 12.One N+ injection region is arranged on N trap 12 and top, P trap 16 junctions and is connected across between N trap 12 and the P trap 16, is to isolate with shallow trench isolation STI 13 between all injection regions.The N+ injection region and the P+ injection region of N trap 12 meet electrical anode Anode, and the N+ injection region and the P+ injection region of P trap 16 meet electrical cathode Cathode.Fig. 2 is and the corresponding electrical schematic diagram of this SCR structure.Under the normal running of integrated circuit, electrostatic discharge protector is to be in closing state, can not influence the current potential on the integrated circuit input output joint sheet.And static externally pours into integrated circuit and when producing moment high-tension, this device can be opened conducting, promptly emits electrostatic induced current.But the effect of this controllable silicon SCR antistatic under abominable static environment is not very desirable.
Summary of the invention
Purpose of the present invention is exactly at the deficiencies in the prior art, provides a kind of under the prerequisite that does not increase the chip layout area, increases the effective area of current drain in the SCR substrate and effectively improves the electrostatic storage deflection (ESD) protection circuit of protection electrostatic capacity.
Electrostatic storage deflection (ESD) protection circuit of the present invention comprises P type substrate, is well region on the P type substrate, and well region comprises N trap and P trap, is equipped with two injection regions on N trap and the P trap, is respectively N+ injection region and P+ injection region.Wherein the N+ injection region of N trap is arranged on the end away from the P trap, and the P+ injection region is arranged on the end near the P trap; The P+ injection region of P trap is arranged on the end away from the N trap, and the N+ injection region is arranged on the end near the N trap; N+ injection region, center is arranged on N trap and top, P trap junction and is connected across between N trap and the P trap.The well region top is provided with polysilicon layer, between polysilicon layer and the well region SiO is set
2Oxide layer.Described polysilicon layer and SiO
2The length of oxide layer is more than or equal to the distance between the close side of N trap in side and P trap N+ injection region of the close P trap in P+ injection region of N trap; Polysilicon layer and SiO
2Oxide layer has the through hole corresponding with the injection region.
Polysilicon layer and SiO
2The P+ injection region that the length of oxide layer equals the N trap near between the side of P trap and the close side of N trap, P trap N+ injection region apart from the time, polysilicon layer and SiO
2Have on the oxide layer and the corresponding through hole in N+ injection region, center, the position of through hole is identical with N+ injection region, center with shape.
Polysilicon layer and SiO
2The length of oxide layer greater than the P+ injection region of N trap near between the side of P trap and the close side of N trap, P trap N+ injection region apart from the time, the polysilicon layer and the SiO of all N+ injection regions, corresponding center, N+ injection region and position, P+ injection region
2Have through hole on the oxide layer, N+ injection region, center, N+ injection region and P+ injection region are identical with the position and the shape of corresponding through hole.
P type substrate, N trap and P trap among the present invention adopts the structure and the technology of existing controllable silicon SCR correspondence, SiO
2Oxide layer adopts existing general technologies such as deposit to realize.
Polysilicon domain layer of the present invention is a hollow out, can not only make N+ injection region, center can pass through the through hole of polysilicon like this, is connected across between N type trap and the P type trap, at polysilicon layer and SiO
2The length of oxide layer greater than the P+ injection region of N trap near between the side of P trap and the close side of N trap, P trap N+ injection region apart from the time, the through hole that polysilicon can be passed through in corresponding N+injection region in N trap and the P trap and P+ injection region is injected into corresponding well region, so just can improve the effective area that electrostatic induced current is released significantly.So just can additionally not increase under the situation of chip area, the effective area that utilizes the existing processes condition to increase in the SCR substrate makes at electrostatic induced current by in this SCR device, can be more even, more disperse, release quickly, thereby improved the static tolerance of electrostatic storage deflection (ESD) protection circuit, effectively improved the protection electrostatic capacity.
Description of drawings
Fig. 1 is the profile of the controllable silicon SCR electrostatic discharge protection component of prior art;
Fig. 2 is the equivalent electric schematic diagram of Fig. 1;
Fig. 3 is the profile of one embodiment of the invention;
Fig. 4 is the vertical view of Fig. 3;
Fig. 5 is the profile of another embodiment of the present invention;
Fig. 6 is the vertical view of Fig. 5;
Fig. 7 is the profile of further embodiment of this invention;
Fig. 8 is the vertical view of Fig. 7.
Embodiment
The present invention will be further described below in conjunction with Figure of description and embodiment.
Embodiment 1:
As shown in Figure 3 and Figure 4, the ESD protection circuit that increases the electrostatic induced current valid circulation area comprises P type substrate 31, be well region on the P type substrate 31, well region comprises N trap 32 and P trap 39, be equipped with two injection regions on N trap 32 and the P trap 39, be respectively that 35, two injection regions in N+ injection region 33 and P+ injection region isolate by shallow trench isolation STI 34.Wherein the N+ injection region of N trap 32 is arranged on the end away from P trap 39, and the P+ injection region is arranged on the end near P trap 39; The P+ injection region of P trap 39 is arranged on the end away from N trap 32, and the N+ injection region is arranged on the end near N trap 32; N+ injection region, center 36 is arranged on N trap 32 and top, P trap 39 junctions and is connected across between N trap 32 and the P trap 39.The well region top is provided with polysilicon layer 37, between polysilicon layer 37 and the well region SiO is set
2Oxide layer 38.Polysilicon layer 37 and SiO
2The P+ injection region that the length of oxide layer 38 equals N trap 32 is near the distance between the side of P trap 39 and the close side of N trap 32, the N+ injection region of P trap 39.Polysilicon layer 37 and SiO
2Have the through hole 41 corresponding with N+ injection region, center 36 on the oxide layer 38, the position of through hole 41 is identical with N+ injection region 36, center with shape.
Embodiment 2:
As shown in Figure 5 and Figure 6, the ESD protection circuit that increases the electrostatic induced current valid circulation area comprises P type substrate 51, be well region on the P type substrate 51, well region comprises N trap 52 and P trap 59, be equipped with two injection regions on N trap 52 and the P trap 59, be respectively that 55, two injection regions in N+ injection region 53 and P+ injection region isolate by shallow trench isolation STI 54.Wherein the N+ injection region of N trap 52 is arranged on the end away from P trap 59, and the P+ injection region is arranged on the end near P trap 59; The P+ injection region of P trap 59 is arranged on the end away from N trap 52, and the N+ injection region is arranged on the end near N trap 52; N+ injection region, center 56 is arranged on N trap 52 and top, P trap 59 junctions and is connected across between N trap 52 and the P trap 59.The well region top is provided with polysilicon layer 57, between polysilicon layer 57 and the well region SiO is set
2Oxide layer 58.Polysilicon layer 57 and SiO
2The P+ injection region that the length of oxide layer 58 equals N trap 52 away from the N+ injection region of the side of P trap 59 and P trap 59 away from the distance between the side of N trap 52.Polysilicon layer 57 and SiO
2Have the through hole 61 corresponding on the oxide layer 58 with N+ injection region, center 56, and with N trap 52 in N+ injection region corresponding groove 62 in P+ injection region and the P trap 59, the position of through hole 61 is identical with N+ injection region 56, center with shape, and the position of groove 62 is identical with the P+ injection region with corresponding N+ injection region with shape.
Embodiment 3:
As shown in Figure 7 and Figure 8, the ESD protection circuit that increases the electrostatic induced current valid circulation area comprises P type substrate 71, is well region on the P type substrate 71, and well region comprises N trap 72 and P trap 78, being equipped with two injection regions on N trap 72 and the P trap 78, is respectively N+ injection region 73 and P+ injection region 74.Wherein the N+ injection region of N trap 72 is arranged on the end away from P trap 78, and the P+ injection region is arranged on the end near P trap 78; The P+ injection region of P trap 78 is arranged on the end away from N trap 72, and the N+ injection region is arranged on the end near N trap 72; N+ injection region, center 75 is arranged on N trap 72 and top, P trap 78 junctions and is connected across between N trap 72 and the P trap 78.The well region top is provided with polysilicon layer 76, between polysilicon layer 76 and the well region SiO is set
2Oxide layer 77.Polysilicon layer 76 and SiO
2The N+ injection region that the length of oxide layer 77 equals N trap 72 away from the P+ injection region of the side of P trap 78 and P trap 78 away from the distance between the side of N trap 72.Polysilicon layer 76 and SiO
2Have on the oxide layer 77 and the P+ injection region of N+ injection region, center 75, N trap 72 and the corresponding through hole 81 in N+ injection region of P trap 78, and with N trap 72 in P+ injection region corresponding groove 82 in N+ injection region and the P trap 78.The P+ injection region of the position of through hole 81 and shape and N+ injection region, center, N trap is identical with the N+ injection region of P trap, and the position of groove 82 is identical with the P+ injection region with corresponding N+ injection region with shape.
Claims (3)
1, a kind of ESD protection circuit that increases the electrostatic induced current valid circulation area, comprise P type substrate, be well region on the P type substrate, well region comprises N trap and P trap, be equipped with two injection regions on N trap and the P trap, be respectively N+ injection region and P+ injection region, wherein the N+ injection region of N trap is arranged on the end away from the P trap, the P+ injection region is arranged on the end near the P trap, the P+ injection region of P trap is arranged on the end away from the N trap, and the N+ injection region is arranged on the end near the N trap, and N+ injection region, center is arranged on N trap and top, P trap junction and is connected across between N trap and the P trap, it is characterized in that described well region top is provided with polysilicon layer, is provided with SiO between polysilicon layer and the well region
2Oxide layer; Described polysilicon layer and SiO
2The length of oxide layer is more than or equal to the distance between the close side of N trap in side and P trap N+ injection region of the close P trap in P+ injection region of N trap; Polysilicon layer and SiO
2Oxide layer has the through hole corresponding with the injection region.
2, a kind of ESD protection circuit that increases the electrostatic induced current valid circulation area as claimed in claim 1 is characterized in that polysilicon layer and SiO
2The length of oxide layer is identical near the distance between the side of N trap near the side and the P trap N+ injection region of P trap with the P+ injection region of N trap, polysilicon layer and SiO
2Have on the oxide layer and the corresponding through hole in N+ injection region, center, the position of through hole is identical with N+ injection region, center with shape.
3, a kind of ESD protection circuit that increases the electrostatic induced current valid circulation area as claimed in claim 1 is characterized in that polysilicon layer and SiO
2The length of oxide layer is greater than the distance between the close side of N trap in side and P trap N+ injection region of the close P trap in P+ injection region of N trap, the polysilicon layer and the SiO of all N+ injection regions, corresponding center, N+ injection region and position, P+ injection region
2Have through hole on the oxide layer, N+ injection region, center, N+ injection region and P+ injection region are identical with the position and the shape of corresponding through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100675168A CN100470803C (en) | 2007-03-05 | 2007-03-05 | ESD protection circuit for enlarging the valid circulation area of the static current |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100675168A CN100470803C (en) | 2007-03-05 | 2007-03-05 | ESD protection circuit for enlarging the valid circulation area of the static current |
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| CN101017818A true CN101017818A (en) | 2007-08-15 |
| CN100470803C CN100470803C (en) | 2009-03-18 |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101814498A (en) * | 2010-03-10 | 2010-08-25 | 浙江大学 | Structure with built-in NMOS auxiliary trigger controllable silicon |
| CN101834180A (en) * | 2010-04-22 | 2010-09-15 | 上海宏力半导体制造有限公司 | SCR (Silicon Controlled Rectifier) static protective device |
| CN102110686A (en) * | 2010-12-17 | 2011-06-29 | 无锡华润上华半导体有限公司 | SCR (silicon controlled rectifier)-based electrostatic protection device of integrated circuit |
| CN102148242A (en) * | 2010-12-30 | 2011-08-10 | 浙江大学 | Silicon controlled device with double-conduction path |
| CN101211968B (en) * | 2007-12-21 | 2011-09-21 | 上海宏力半导体制造有限公司 | Manufacture method for thyristor for electro-static discharge |
| CN103745976A (en) * | 2014-01-15 | 2014-04-23 | 帝奥微电子有限公司 | Electrostatic discharge protection structure |
| CN108878416A (en) * | 2018-06-28 | 2018-11-23 | 武汉新芯集成电路制造有限公司 | ESD protection circuit |
| CN111725206A (en) * | 2019-07-29 | 2020-09-29 | 中国科学院上海微系统与信息技术研究所 | PMOS-triggered SCR device, manufacturing method of SCR device and SCR electrostatic protection circuit |
| CN114121944A (en) * | 2022-01-27 | 2022-03-01 | 江苏应能微电子有限公司 | Transient voltage suppression protection device with high maintenance voltage and electrostatic discharge circuit |
-
2007
- 2007-03-05 CN CNB2007100675168A patent/CN100470803C/en not_active Expired - Fee Related
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101211968B (en) * | 2007-12-21 | 2011-09-21 | 上海宏力半导体制造有限公司 | Manufacture method for thyristor for electro-static discharge |
| CN101814498A (en) * | 2010-03-10 | 2010-08-25 | 浙江大学 | Structure with built-in NMOS auxiliary trigger controllable silicon |
| CN101834180B (en) * | 2010-04-22 | 2015-12-09 | 上海华虹宏力半导体制造有限公司 | A kind of SCR electrostatic protection device |
| CN101834180A (en) * | 2010-04-22 | 2010-09-15 | 上海宏力半导体制造有限公司 | SCR (Silicon Controlled Rectifier) static protective device |
| CN102110686A (en) * | 2010-12-17 | 2011-06-29 | 无锡华润上华半导体有限公司 | SCR (silicon controlled rectifier)-based electrostatic protection device of integrated circuit |
| CN102110686B (en) * | 2010-12-17 | 2012-11-28 | 无锡华润上华半导体有限公司 | SCR (silicon controlled rectifier)-based electrostatic protection device of integrated circuit |
| CN102148242A (en) * | 2010-12-30 | 2011-08-10 | 浙江大学 | Silicon controlled device with double-conduction path |
| CN103745976A (en) * | 2014-01-15 | 2014-04-23 | 帝奥微电子有限公司 | Electrostatic discharge protection structure |
| CN108878416A (en) * | 2018-06-28 | 2018-11-23 | 武汉新芯集成电路制造有限公司 | ESD protection circuit |
| CN111725206A (en) * | 2019-07-29 | 2020-09-29 | 中国科学院上海微系统与信息技术研究所 | PMOS-triggered SCR device, manufacturing method of SCR device and SCR electrostatic protection circuit |
| CN111725206B (en) * | 2019-07-29 | 2023-11-21 | 中国科学院上海微系统与信息技术研究所 | PMOS triggered SCR device, manufacturing method of SCR device and SCR electrostatic protection circuit |
| CN114121944A (en) * | 2022-01-27 | 2022-03-01 | 江苏应能微电子有限公司 | Transient voltage suppression protection device with high maintenance voltage and electrostatic discharge circuit |
| CN114121944B (en) * | 2022-01-27 | 2022-05-17 | 江苏应能微电子有限公司 | Transient voltage suppression protection device with high maintenance voltage and electrostatic discharge circuit |
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| CN100470803C (en) | 2009-03-18 |
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Granted publication date: 20090318 Termination date: 20120305 |