CN101013407A - System and method for implementing memory mediation of supporting multi-bus multi-type memory device - Google Patents
System and method for implementing memory mediation of supporting multi-bus multi-type memory device Download PDFInfo
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Abstract
The invention discloses a memory arbiter system and implementation method that support multi-bus and multiple types of memory to solve the problem that multiple bus can not access multiple types of memory in existing technology. The invention includes: n bus main modules, the m memories, m arbiters which are connected to m memories correspondingly, the read data processing modules that are connected to n bus main modules, any memory arbiter module of the m memory arbiter modules can receive the memory access request issued by the n bus main modules; the memory arbiter module arbitrates the memory access requests and output the result; write to the memory corresponding to the memory arbiter; the read data processing module receives the arbitration results of m memory arbiter modules, and outputs the read data of corresponding memory to n bus main module according the arbitration result. It makes the multiple buses have access to multiple types of memory.
Description
Technical field
The present invention relates to the internal memory arbitration and realize system and method, relate in particular to the internal memory arbitration of supporting multibus polymorphic type storer and realize system and method.
Background technology
Technical development along with SOC (system on a chip) (SOC) chip, module integrated on one chips (comprises central processor CPU, digital signal processor DSP, and other special hardware circuits etc.) more and more, therefore the demand to storer (comprising internal memory and chip external memory in the sheet) also gets more and more, and comprises the demand of two aspects here: 1, increasing to the capacity requirement of storer; 2, more and more to the type demand of storer.In actual applications, the multiple bus primary module can send read to a plurality of storeies simultaneously, mainly contains following several technology at present and is applied in the internal memory arbitration of storer:
One, bus arbitration technology.Bus arbitration has been meant when a plurality of bus master ask to use bus simultaneously the bus decision by which bus master can be obtained the access control of storer is weighed.So-called " bus master " also claims bus master or master control person, can control bus, and can carry out the module or the equipment of exchanges data with other non-main control module.Correspondingly, module that can not control bus is called from module or slave unit (as bus interface etc.).As shown in Figure 1, n bus master is connected with m storer by a public bus (BUS), when the memory access request of n bus master arrives bus (BUS) together, bus is selected the request of access of one of them bus master by arbitration algorithm, to give this selected bus master to the access control power of storer, according to the request of access of this selection corresponding memory be carried out read again.Wherein, m storer can be a plurality of dissimilar storeies, such as, storer 1 can be RAM (random access memory), and storer 2 can be SRAM (static RAM) ... storer m can be SDRAM (synchronous DRAM) or APB, NOR FLASH etc.This method structurally realizes simply, but synchronization can only be realized storer of a bus master visit, bandwidth is little, when increase of hardware path or bandwidth applications requirement increase, project organization originally may just can not have been used again, need change again.
Two, internal memory arbitration technique.Internal memory arbitration is meant when a plurality of bus master ask same storer conducted interviews simultaneously, by determining which bus master to obtain access control power to this storer by after the internal memory arbitration again.As shown in Figure 2, bus master 1～n is by internal memory arbitration back addressable memory 1, and bus master n+1～n+i is by internal memory arbitration back addressable memory 2, and bus master n+n can reference-to storage m after arbitrating by internal memory.As seen, bus master 1～n can only reference-to storage 1, and can not reference-to storage 2; Bus master n+1～n+i can only reference-to storage 2, and can not reference-to storage 1.The a plurality of bus master of this technical support are selected a storer simultaneously, and bandwidth is big, but a plurality of bus master can not be visited in a plurality of storeies any one, and when increasing storer, all hardware modules all must increase, and its system multiplexing is poor.
Three, the bus arbitration technology combines with the internal memory arbitration technique.The storer not high for some bandwidth requirements can adopt the bus arbitration technology; The storer higher for other bandwidth requirements then adopts the internal memory arbitration technique, but the method that this bus arbitration technology combines with the internal memory arbitration technique, when a bus master is switched different memory accesses, handle complicated, make some clock period can not be used for reference-to storage easily, and when checking, be not easy to authenticate to various situations.
Therefore, how to support this multiple bus visit polymorphic type storer to seem extremely important in actual applications efficiently.
Summary of the invention
At the problem that above-mentioned prior art exists, the objective of the invention is to propose a kind of internal memory arbitration realization system and method for supporting multibus polymorphic type storer.
For achieving the above object, the present invention supports the internal memory arbitration realization system of multibus polymorphic type storer, comprise: n bus master, m storer, also comprise: m the storer arbitration modules that connects one to one with m storer, and a read data processing module that is connected with a described n bus master;
Wherein, each bus master in the described n bus master is connected with each storer arbitration modules in described m the storer arbitration modules;
Described each storer arbitration modules is used to receive the memory access request that n bus master sends, and the memory access request that receives is arbitrated, the output arbitration result, and the storer of correspondence is carried out write operation according to this arbitration result;
Described read data processing module is connected with described m storer arbitration modules, and is connected with a described m storer; Be used to receive the arbitration result of described m storer arbitration modules output, and, export the specified bus master of this arbitration result to according to the read data that the arbitration result storer that this arbitration result is specified is exported;
Wherein, m and n are the natural number greater than 1.
Each storer arbitration modules in above-mentioned m storer arbitration modules includes:
One memory access arbitration module is connected respectively with a described n bus master, is used for from n bus master reception memorizer request of access, and the memory access request that receives is arbitrated, the output arbitration result;
One storer control signal is selected module, with the corresponding connection of described memory access arbitration module, and all be connected with a described n bus master, be used for receiving arbitration result from the memory access arbitration module, and according to arbitration result from the n road internal control signal of n bus master output, the road internal control signal that this arbitration result of selective reception is specified, and the internal control signal that will select exports corresponding storer to.
Above-mentioned read data processing module comprises:
One data channel is selected module, be connected with described m memory access arbitration module, be used for receiving arbitration result from m memory access arbitration module, read data requirement according to arbitration result and several types of memory, obtain each permission situation of reading of the bus path of n bus master correspondence constantly, and export n bar bus path read whether to allow signal;
N read data selected module, selects module to be connected with described data channel, is used for receiving correspondingly from what data channel was selected n bar bus path that module exports reading whether to allow signal; Each read data selects module all to be connected with all storeies, and be connected with described bus master correspondingly, be used to receive the read data and the read data useful signal of m storer output, and read whether to allow signal according to what receive, from m storer, select the read data and the read data useful signal of a storer output, export corresponding bus master to.
System of the present invention also comprises: n the bus interface that connects one to one with a described n bus master;
Correspondingly, the arbitrary storer arbitration modules in described m storer arbitration modules can receive, from n bus master by with its memory access request of sending of bus interface one to one;
Described read data processing module exports the read data of storer output to a described n bus master by n bus interface.
System of the present invention also comprises: m store control logic module connects one to one with a described m storer, and connects one to one with described m storer arbitration modules;
Described each store control logic module is used for the internal control signal that receives from the storer arbitration modules corresponding with it, and carry out read/write operation according to the internal control signal pair storer corresponding that receives with it, and receive read data and read data useful signal, and output from the storer corresponding with it.
M among a present invention storer is: m dissimilar storeies, the perhaps storer of m same type, perhaps m the storer that the part type is identical.
System of the present invention, by the read data processing module, and the storer arbitration modules corresponding respectively with m storer, allow n bus master can visit in m the storer any one, allow a plurality of different bus master of synchronization to visit different storeies separately again; When promptly realizing bus master 1 reference-to storage 1, bus master 2 can reference-to storage 2, and perhaps bus master 1 reference-to storage 2 time, bus master 2 can reference-to storage 1 ..., bus master n can reference-to storage m; The bus path of each bus master correspondence can both well be utilized at each constantly, and bandwidth is big, and the bandwidth availability ratio height.Increasing new passage, during new storer supporting interface (as memory access arbitration module, store control logic module etc.), can make amendment easily, have stronger design reusability.
For achieving the above object, the present invention supports the internal memory arbitration implementation method of multibus polymorphic type storer, comprises the steps:
(1) the arbitrary bus master in n bus master is by the bus interface corresponding with it, to m the storer arbitrary storer arbitration modules in the storer arbitration modules one to one, sends memory access request and internal control signal;
(2) each storer arbitration modules is arbitrated the memory access request that receives according to the arbitration algorithm of storing in it, the output arbitration result, and from bus interface the selective reception internal control signal corresponding with this arbitration result, and carry out read/write operation according to this internal control signal pair storer corresponding with it.
In the above-mentioned steps (2), the arbitration algorithm that each storer arbitration modules adopts comprises:
A) algorithm once arbitrated of each clock period;
Perhaps B) Writing/Reading of every bus master begins to finish as a minimum clock cycle to this time Writing/Reading, and the visit of other bus master can not be inserted in the centre;
Perhaps C) reads and writes the algorithm of arbitration according to fixed priority;
Perhaps D) arrives first first Processing Algorithm;
Perhaps E) dynamic priority algorithm;
Perhaps F) maximum wait period that allows according to each bus path is arranged the access order of each bus master;
Perhaps above-mentioned A) and C), D), E), combination in any F), perhaps B) and C), D), E), combination in any F).
In the above-mentioned steps (2): the storer arbitration modules is carried out read/write operation receiving after the internal control signal corresponding with arbitration result 1 or 1 during above clock period from bus interface to the storer corresponding with it.
Above-mentioned internal control signal comprises: to the read/write control of storer, byte is selected, read data length, read/write address and write data signal.
Method of the present invention can obtain different characteristics, and need not to revise the structure of other modules by revising the arbitration algorithm in the memory access arbitration module, has good design flexibility and reusability.In addition, to ROM (ROM (read-only memory)), the storer of the type of RAM (random access memory) can reach 100% bandwidth availability ratio when adopting each clock period once to arbitrate; Under certain access mechanism, also can reach quite high bandwidth availability ratio to SDRAM (synchronous DRAM).
Description of drawings
Fig. 1 is the block diagram that concerns of bus master and each storer in the existing bus arbitration technology;
Fig. 2 is the block diagram that concerns of bus master and each storer in the existing internal memory arbitration technique;
Fig. 3 is a system global structure block diagram of the present invention;
Fig. 4 is the first example structure block diagram of system of the present invention;
Fig. 5 is the second example structure block diagram of system of the present invention;
Fig. 6 is each module work relationship figure of method of the present invention.
Embodiment
Below in conjunction with accompanying drawing technical scheme of the present invention is described.
As shown in Figure 3, the internal memory arbitration realization system of support multibus polymorphic type storer of the present invention mainly comprises: n bus master, m storer, with m storer m the storer arbitration modules that connect one to one, and a read data processing module that all is connected with n bus master, a m storer arbitration modules and m storer; Wherein, m and n are the natural number greater than 1.
Each bus master in n bus master is connected with each the storer arbitration modules in m the storer arbitration modules; Each storer arbitration modules receives the memory access request that n bus master sends, and the memory access request that receives is arbitrated, the output arbitration result.Described arbitration result reflects current time, and the memory access request which bus master is sent is effective, has therefore wherein specified which bus master what kind of accessing operation which storer is carried out.
Described storer arbitration modules allows the bus master of appointment that corresponding memory is carried out write operation according to this arbitration result, thereby has made up an independently data transmission channel of total line write transactions.
The read data processing module is connected with described m storer arbitration modules, and is connected with a described m storer; Be used to receive the arbitration result of m storer arbitration modules output, and according to the read data of arbitration result storer that this arbitration result is specified output, export the specified bus master of this arbitration result to, thereby an independently data transmission channel of bus read operation is provided.
System of the present invention, by the design storer arbitration modules corresponding respectively with m storer, and the read data processing module, can allow n bus master can visit in m the storer any one, allow the different bus master of synchronization to visit different storeies separately again; When promptly realizing bus master 1 reference-to storage 1, bus master 2 can reference-to storage 2, and perhaps bus master 1 reference-to storage 2 time, bus master 2 can reference-to storage 1 ..., bus master n can reference-to storage m; Make the bus path of each bus master correspondence constantly can both well be utilized bandwidth height, and bandwidth availability ratio height at each.And independently write data path and read data path are arranged, make read-write can pass through PIPELINE (streamline) mode and continue write store.
Embodiment 1:
Below in conjunction with the embodiment that Fig. 4 provided, the internal memory of support multibus polymorphic type storer of the present invention is arbitrated the realization system is described further:
As shown in Figure 4, the structure of each the storer arbitration modules in the m in the system of present embodiment storer arbitration modules is all identical, wherein each storer arbitration modules can comprise: a memory access arbitration module, and a storer control signal of corresponding connection with this memory access arbitration module selection module, this storer control signal selects module also all to be connected with n bus master.
Wherein, the memory access request that each memory access arbitration module receives from n bus master, and the memory access request that receives arbitrated the output arbitration result; Be the memory access arbitration module according to certain arbitration algorithm from each bus master of visiting this memory access arbitration module, choose the pairing bus of one of them bus master, as the hardware path of this storer is carried out read/write operation time transmission data.
Each storer control signal selects module to receive arbitration result from the memory access arbitration module corresponding with it, and according to the arbitration result that receives from n bus master, the specified road internal control signal of this arbitration result of selective reception (such as, if arbitration result is for choosing bus master 1, then the storer control signal is selected the internal control signal that module selective reception bus master 1 sends), and with this internal control signal of choosing output.
Wherein, above-mentioned internal control signal can comprise: to the read/write control of storer, byte is selected, read data length, read/write address, write data signal etc.
As shown in Figure 4, the read data processing module in the system of present embodiment comprises: one is connected the data channel selecting module with m memory access arbitration module, and selects module with n bus master n the read data that connect one to one;
Wherein, data channel selects module to receive arbitration result from m memory access arbitration module, and according to the read data requirement of arbitration result and several types of memory, obtain each permission situation of reading of the n bar bus path of n bus master correspondence constantly, and export each moment n bus master correspondence n bar bus path read whether to allow signal; Whether the reading of described n bar bus path allows signal to be used to notify all read datas to select modules, current should which bus master of gating and which storer between the bus run that is used to carry out the read operation data transmission.
N read data selects each read data in the module to select module all to be connected with data channel selection module, and is connected with each storer in m the storer; N read data select each read data in the module select module receive respectively from data channel select module n bar bus path each constantly read whether to allow signal, also receive read data and read data useful signal that m storer exported; And according to the n bar bus path that receives each constantly read whether to allow signal, selection is allowed to the read data and the read data useful signal of the pairing storer output of bus path of read data from m storer, exports the pairing bus master of bus path that is allowed to read data to.
Embodiment 2:
As shown in Figure 5, the system of present embodiment also comprises with respect to Fig. 4: with n the bus interface that n bus master connects one to one, each bus interface provides a bus path;
Correspondingly, arbitrary memory access arbitration module can receive from n bus master by with its memory access request signal of sending of bus interface one to one; N read data selected the read data of module with storer output in the read data processing module, by with its one to one n bus interface export a described n bus master to.
Above-mentioned bus interface is mainly used in handles various types of bus protocols, with the memory access request that receives be converted to signal through the output of unified output interface (such as, bus interface provides 3 request of access line, 16 read/write address line, 16 byte selection wire, be equivalent to for follow-up module provides unified output interface, follow-up module can connect the signal wire in these hardware output interfaces as required).
As shown in Figure 5, the system of present embodiment also comprises m the store control logic module that connects one to one with m storer; M store control logic module also with m storer arbitration modules in the storer control signal select module to connect one to one, and and the read data processing module in arbitrary read data selection module be connected;
The store control logic module receives the internal control signal of selecting module output from the storer control signal, and carry out read/write operation according to the storer of the internal control signal that receives pair corresponding connection with it, the read data of storer that perhaps will corresponding connection with it and read data useful signal export all read datas to and select module, select read data and the read data useful signal of module by read data again, export to this read data and select the corresponding bus interface of module storer.
The store control logic module is the attached interface circuit of storer, can carry out the extensibility design according to dissimilar storeies, is mainly used in the read/write operation control to storer.
With reference to figure 5, the annexation between each module of present embodiment system and the transitive relation of signal are specifically described, this system comprises again:
N bus master;
N the bus interface that connects one to one with n bus master;
M storer, wherein, the type of each storer can be identical, also can be different, but also part is identical;
With m storer m memory access arbitration module one to one, each the memory access arbitration module in this m memory access arbitration module is connected with each bus interface in n the bus interface respectively;
With m storer one to one m storer control signal select module, this m storer control signal selection module and above-mentioned m memory access arbitration module connect one to one;
With m the store control logic module that m storer connects one to one, this m store control logic module and above-mentioned m storer control signal selects module to connect one to one;
N the read data that connects one to one with n bus interface selected module, and each read data selects module to be connected with each store control logic module in m the store control logic module;
And a data channel selecting module selecting modules to be connected with all read datas, and this data channel selection module is connected with all memory access arbitration module.
Wherein, arbitrary bus master in n bus master is by the bus interface corresponding with it, can the arbitrary memory access arbitration module in m memory access arbitration module initiates the memory access request data read/write request of storer (promptly to); Can select the corresponding arbitrary storer control signal in the module to select module to send read to m storer control signal simultaneously, byte be selected, read data length, read/write address, internal control signals such as write data content;
Each memory access arbitration module in m memory access arbitration module is respectively according to the arbitration algorithm of storage in it, the memory access request that receives is arbitrated, provide arbitration result, and with arbitration result riches all the way gives the storer control signal and select module, another road sends to data channel and selects module, promptly selects module and data channel to select module to send the request of access of choosing to the storer control signal;
M storer control signal selects each the storer control signal in the module to select module respectively according to its arbitration result that receives, from a plurality of bus interface, select the internal control signal of the specified bus interface transmission of its arbitration result that receives, and the internal control signal that this is chosen is sent to the store control logic module corresponding with it;
Each store control logic module in m store control logic module is respectively according to its internal control signal that receives, respectively the storer corresponding with it carried out read/write operation, and export the read data and the read data useful signal of this storer to all read data selection module;
Data channel selects module according to the arbitration result that receives, obtain each permission situation of reading of the n bar bus path of n bus interface correspondence constantly, and, whether allow signal to export n read data selection module respectively to each reading constantly according to the read data requirement of arbitration result and several types of memory;
N read data selects each read data in the module to select module to read whether to allow signal according to each moment of n the bus path that receives respectively, carrying out read data selects, promptly according to each constantly n bar bus path read whether to allow signal, from m read data and read data useful signal from the output of store control logic module, selection is allowed to the read data and the read data useful signal of the pairing store control logic module output of bus path of read data, export the pairing bus interface of bus path that is allowed to read data to, by this bus interface read data and read data useful signal are back to corresponding bus master again.
Above-mentioned store control logic module is to the read operation of general memory, its read data can be after receiving internal control signal just carries out after 1 or 1 above clock period, therefore preferably according to concrete memory characteristics, in some cycles time-delay back (all after dates more than 1 or 1), according to arbitration result storer is carried out read/write operation by the store control logic module again.
M in a system of the present invention storer can be m dissimilar storeies, the perhaps storer of m same type, perhaps m the storer that the part type is identical.Storer 1 as shown in Fig. 3, Fig. 4 and Fig. 5 can be ROM (ROM (read-only memory)), storer 2 can be SRAM (static RAM),, storer m can be SDRAM (synchronous DRAM) or NOR FLASH (NOR type flash memory) or APB (APB storer) etc.; The access interface sequential of dissimilar storeies is different, generally, the access interface sequential of the storer of same type is the same substantially, such as, read-write control to a plurality of SRAM (static RAM) is the same substantially, except each control signal, some difference of concrete time sequence parameter of data and address, but this difference does not influence the method for designing of sequential logic.
Support multibus polymorphic type store memory of the present invention is arbitrated the realization system, system of the present invention, by design storer arbitration modules and the read data processing module corresponding respectively with m storer, can allow n bus master can visit in m the storer any one, synchronization, a storer can only be allowed the different bus master of synchronization to visit different storeies separately again by the visit of one tunnel bus master; When promptly realizing bus master 1 reference-to storage 1, bus master 2 can reference-to storage 2, and perhaps bus master 1 reference-to storage 2 time, bus master 2 can reference-to storage 1 ..., bus master n can reference-to storage m; Make the bus path of each bus master correspondence constantly can both well be utilized bandwidth height, and bandwidth availability ratio height at each.And increasing new passage, during new storer supporting interface (as memory access arbitration module, store control logic module etc.), can make amendment easily, have extremely strong design reusability.
Again in conjunction with Fig. 5, the internal memory of support multibus polymorphic type storer of the present invention is arbitrated implementation method describe below, the present invention supports the internal memory arbitration implementation method of multibus polymorphic type storer to comprise the steps:
(1) the arbitrary bus master in n bus master is by the bus interface corresponding with it, to m storer one to one the arbitrary storer arbitration modules in the storer arbitration modules send memory access request and internal control signal;
(2) each storer arbitration modules is arbitrated the memory access request that receives according to the arbitration algorithm of storing in it, the output arbitration result, and from bus interface the selective reception internal control signal corresponding with this arbitration result, and carry out the read/write operation of data according to this internal control signal pair storer corresponding with it.
Above-mentioned memory access arbitration module can adopt following different arbitration algorithm at different memory characteristics, and adoptable arbitration algorithm mainly contains:
1) algorithm once arbitrated of each clock period;
2) read/write of every bus master begins to finish as a minimum clock cycle to this time read/write, and the visit of other bus master can not be inserted in the centre.
This algorithm of two types all can carry out prioritization to the memory access request signal with following algorithm combination:
A) read and write arbitration according to fixed priority;
B) employing arrives first first Processing Algorithm, promptly the bus master of request is at first arbitrated;
C) adopt dynamic priority algorithm, adjust the priority orders of each bus at regular intervals according to certain algorithm;
D) maximum wait period that allows according to each bus path is arranged the access order of each bus interface;
For example, for ROM, RAM, storeies such as SRAM can adopt each clock period according to fixing priority arbitration algorithm, promptly above-mentioned 1) and combination a);
Also can adopt separately and arrive first first disposal route; Can also adopt the maximum wait period that allows according to each bus path to arrange separately.
And can adopt the above-mentioned the 2nd for storeies such as SDRAM, NOR FLASH) type algorithm;
Also can arrange the access order of each bus interface according to the maximum wait period that each bus path allows;
Can also adopt and arrive first first Processing Algorithm.
For APB, APB generally is with visiting internal register, it need adopt with 2 clock period as the least unit of visit once, can not insert the algorithm of the arbitration result of other passages between 2 clock period, therefore arbitration occur in equally that last visit finishes that constantly; Also can adopt and arrive first first Processing Algorithm; Can also arrange the access order of each bus interface according to the maximum wait period that each bus hardware path allows.
The arbitration algorithm mechanism of other storer can be selected according to actual conditions, and this is the known technology of those skilled in the art, enumerates no longer one by one at this.
Hypothesis storer 1 is SRAM below, storer m is SDRAM, what then store in the storer 1 access arbitration module of SRAM correspondence is SRAM storer arbitration algorithm, to adopt the arbitration algorithm of each clock period according to fixed priority, the algorithm of selecting the high bus interface of priority to carry out memory access is an example; And what store in the storer m access arbitration module of SDRAM correspondence is SDRAM storer arbitration algorithm, and arriving first first Processing Algorithm with employing is example.
Then above-mentioned steps (1) is specially:
(11) corresponding with the bus master 1 storer 1 access arbitration module of bus interface 1 in the corresponding storer arbitration modules of SRAM initiated memory access request, and storer 1 control signal in the storer arbitration modules selects module to send internal control signal simultaneously;
The bus interface 2 of bus master 2 correspondences is also initiated request of access to the storer 1 access arbitration module of SRAM correspondence, also selects module to send the internal control signal of this bus interface 2 to storer 1 control signal simultaneously;
The bus interface n of bus master n correspondence also initiates memory access request to the storer 1 access arbitration module of SRAM correspondence, also selects module to send the internal control signal of this bus interface n to storer 1 control signal simultaneously.
As a same reason, bus master 1～n also in the same way SDRAM initiate memory access request.
Above-mentioned steps (2) is specially:
(21) storer 1 access arbitration module is according to the arbitration algorithm of storing in it, bus interface 1 in this storer 1 access arbitration module of visit, bus interface 2, among the bus interface n, adopt each clock period to arbitrate according to fixed priority, the priority of supposing bus interface 1 is higher, then this moment storer 1 access arbitration module arbitration result for choosing bus interface 1.
As a same reason, the storer m access arbitration module of SDRAM correspondence adopts the arbitration algorithm that arrives first processing earlier that the memory access request of bus interface 1～n is arbitrated, if the memory access request of bus interface n arrives at first, then arbitration result is for choosing bus interface n.
(22) storer 1 access arbitration module sends to the storer corresponding with SRAM 1 control signal with its arbitration result and selects module (promptly selecting module to send the request of access of choosing to corresponding storer 1 control signal of SRAM), this storer 1 control signal selects module according to its arbitration result that receives, and the internal control signal of selective reception bus interface 1 output (comprises; The read/write control request of bus, byte is selected, length, read/write address, and write data etc.), and storer 1 control logic module of the internal control signal that this selective reception is arrived input SRAM correspondence, this storer 1 control logic module is carried out read/write operation according to its arbitration result that receives and internal control signal to this SRAM;
This storer 1 access arbitration module also sends to its arbitration result data channel simultaneously and selects module, promptly selects module to initiate the request of access of choosing to data channel;
As a same reason, the storer m access arbitration module of SDRAM correspondence is sent to the storer m control signal corresponding with SDRAM with its arbitration result and selects module (promptly selecting module to initiate the request of access of choosing to the corresponding storer m control signal of SDRAM), this storer m control signal selects module according to its arbitration result that receives, the internal control signal of selective reception bus interface n output, and with the storer m control logic module of the internal control signal of this selective reception input SDRAM correspondence, this storer m control logic module is carried out read/write operation according to its arbitration result that receives and internal control signal to SDRAM.
(23) data channel selects module according to the arbitration result that receives, obtain each permission situation of reading of the bus path of n bus interface correspondence constantly, and according to the read data requirement of arbitration result and several types of memory, with each n bar bus path constantly read whether allow signal to be sent to n read data selection module respectively.
(24) read data select module 1 according to each the bus path constantly that receives read whether to allow signal, select the read data operation on the corresponding bus path.Such as, read data selects module 1 to read whether to allow signal according to this, the request of knowing 1 pair of storer 1 read data of bus master is allowed to, then select to connect the read data bus path between storer 1 and the bus master 1, promptly select read data and read data useful signal, and this read data and read data useful signal are sent to bus interface 1 from the SRAM storer of storer 1 control logic module output; By this bus interface 1 read data and read data useful signal are returned to bus master 1 again;
As a same reason, read data selects module n to read whether to allow signal according to each the bus path constantly that receives, know that bus master n is allowed to the request of the read data of storer m, then select read data and read data useful signal, and this read data and read data useful signal are sent to the bus interface n corresponding with it from the SDRAM storer of storer m control logic module output; By this bus interface n read data and read data useful signal are returned to the bus master n corresponding with it again.
In the above-mentioned steps (22), storer 1 control logic module is after receiving internal control signal, characteristic according to SRAM itself, the read data that may not can return storer immediately, but just storer is carried out read/write operation after after receiving internal control signal 1 or 1 above clock period, return the read data of storer.Therefore, need operate according to the characteristic of the storer of the arbitration result of memory access arbitration module and this memory access arbitration module correspondence itself.
Below in conjunction with Fig. 6, support the concrete implementation step of the internal memory arbitration implementation method of multibus polymorphic type storer to be described in further details to the present invention:
Suppose that bus master has 4, be respectively bus master 1, bus master 2, bus master 3, bus master 4, each bus master are all distinguished corresponding bus interface; Storer has 2, is respectively SRAM and SDRAM.
Suppose that bus master 1 desire reads 4 numbers from SRAM, 4 data that read are respectively: 0x10000000,0x10000001,0x10000002,0x10000003, the start address of these 4 data is respectively: 0x20000000,0x20000004,0x20000008,0x2000000c.
And the priority of the bus of bus master 2 correspondences is greater than the priority of the bus of bus master 1 correspondence;
The priority of the bus of bus master 4 correspondences is greater than the priority of the bus of bus master 3 correspondences.
Implementation step specifically comprises:
(A) the memory access arbitration module of 1 pair of SRAM correspondence of bus master is initiated the read operation request of access of 4 data;
The memory access arbitration module of 3 pairs of SDRAM correspondences of bus master is initiated the request of access of the write operation of 4 data; After the clock period, bus master 2 is initiated the write operation request of access of 4 data to the memory access arbitration of SRAM correspondence;
(B) the memory access arbitration module of SRAM correspondence is according to the arbitration algorithm of storing in it (this arbitration algorithm adopts each clock period to carry out a priority arbitration), choose bus master 1 in first clock period, choose bus master 2 since the 2nd clock period, after the write operation of 4 data of bus master 2 is finished, choose bus master 1 again;
(read/write of the every road of this arbitration algorithm bus master begins to finish as a minimum clock cycle to this time read/write the memory access arbitration module of SDRAM correspondence according to the arbitration algorithm of storage in it, the middle visit that can not insert other bus master, perhaps arrive first first Processing Algorithm), choose bus master 3, after the write operation of 4 data of bus master 3 is finished, choose bus master 4 (although the priority of the bus of bus master 4 correspondences is higher than the priority of the bus of bus master 3 correspondences again, but arrive first first processing owing to adopt, so bus master 4 begins read data after can only waiting until that 4 data writing operation of bus master 3 are finished again).
(C) the storer control signal of SRAM correspondence selects module in first clock period, receives the internal control signal (being the start address 0x20000000 of data 0x10000000) of bus interface 1 transmission of bus master 1 correspondence; From the second clock cycle, the internal control signal that receives the bus interface transmission of bus master 2 correspondences (is 0x20020000 start address 0x20000100, the start address 0x20000104 of data 0x20020001, the start address 0x20000108 of data 0x20020002, the start address 0x2000010c of data 0x20020003); After 4 data writing operation of bus master 2 were finished, beginning to receive bus master 1 again (was the start address 0x20000004 of data 0x10000001 by the internal control signal that the bus interface corresponding with it sends; The start address 0x20000008 of data 0x10000002; The start address 0x2000000c of data 0x10000003);
It (is the start address 0x40000100 of data 0x30003000 that the bus interface that the storer control signal of SDRAM correspondence selects module at first to receive bus master 3 correspondences sends internal control signal, the start address 0x40000104 of data 0x30003001, the start address 0x40000108 of data 0x30003002, the start address 0x4000010c of data 0x30003003); After the write operation of 4 data of bus master 3 is finished, the internal control signal that receives the bus interface transmission of bus master 4 correspondences again (is the start address 0x40001000 of data 0x40000400, the start address 0x40001004 of data 0x40000401, the start address 0x40001008 of data 0x40000402, the start address 0x4000100c of data 0x40000403).
(D) data channel selects module when the arbitration result of the memory access arbitration module that receives the SRAM correspondence, in first clock period bus path of bus master 1 correspondence is set at and reads to allow (the bus path that is bus master 1 correspondence is unimpeded);
Data channel selects module when the arbitration result of the memory access arbitration module that receives the SDRAM correspondence, the bus path of bus master 4 correspondences is set at reads to allow (the bus path that is bus master 4 correspondences is unimpeded).
(E) the store control logic module of SRAM correspondence carried out the read data of SRAM is operated in first clock period, begin to carry out data writing operation from the second clock cycle to SRAM, after 4 data write operations of bus master 2 are finished, proceed read data operation to SRAM;
The store control logic module of SDRAM correspondence is at first carried out the data writing operation to SDRAM, after 4 data write operations of bus master 3 are finished, carries out the read data operation to SDRAM again.
(F) corresponding with bus master 1 read data is selected module, read data and read data useful signal that first clock period was obtained from the store control logic module of SRAM correspondence, bus interface by bus master 1 correspondence exports bus master 1 to, by the time after the write operation of 4 data of 2 couples of SRAM of bus master is finished, continue read data and the read data useful signal that will obtain from the store control logic module again, the bus interface by bus master 1 correspondence exports bus master 1 to;
The read data corresponding with bus master 4 selected module, after the write operation of 4 data of 3 couples of SDRAM of bus master is finished by the time, the read data and the read data useful signal that will obtain from the store control logic module of SDRAM correspondence, the bus interface by bus master 4 correspondences exports bus master 4 to.
The present invention is connected to a plurality of memory access arbitration modules by the bus interface corresponding with it respectively by a plurality of bus master, can visit a plurality of storeies, make like this that in one tunnel bus master reference-to storage 1 another road bus master can reference-to storage 2; Independently write data path and read data path are arranged, make read-write can pass through PIPELINE (streamline) mode and continue write store; And, storer 1 access arbitration module is only arbitrated a plurality of bus interface of visiting this module, and the arbitration process of storer 2 access arbitration modules is not influenced each other, storer can be implemented in first and handles the data of coming from bus master 1 constantly, next constantly can the processing, i.e. the zero-waiting time of storer in the different bus primary module switches and the zero-waiting time of read-write switching from the read signal of bus master 2; The memory access arbitration module can each provide an arbitration result constantly, makes the read/write signal of each different bus primary module can continuously be transferred to the storer control signal and selects to go in the module.Therefore, the present invention has higher bandwidth availability ratio height, and to ROM, the storer of the type of RAM can reach 100% bandwidth availability ratio; Under certain access mechanism, also can reach quite high bandwidth availability ratio to SDRAM by queuing algorithm and concurrent access mechanism.
The technical scheme that the foregoing description disclosed only is specifying system and method for the present invention, though and in the literary composition by specific term (as the storer arbitration modules, read data processing module etc.) describe, but can not limit the protection domain of patent of the present invention with this; Thought of the present invention is not limited only to the access technique of multibus to multi-memory, also can be applicable to select or field such as switch as the hyperchannel of router; Those skilled in the art should be after understanding spirit of the present invention and principle, to its change and modification of carrying out equivalent purpose, all should be covered by within the scope that scope of patent protection of the present invention defines.
Claims (10)
1, a kind of internal memory arbitration realization system that supports multibus polymorphic type storer, comprise: n bus master, m storer, it is characterized in that, also comprise: m the storer arbitration modules that connects one to one with m storer, and a read data processing module that is connected with a described n bus master;
Wherein, each bus master in the described n bus master is connected with each storer arbitration modules in described m the storer arbitration modules;
Described each storer arbitration modules is used to receive the memory access request that n bus master sends, and the memory access request that receives is arbitrated, the output arbitration result, and the storer of correspondence is carried out write operation according to this arbitration result;
Described read data processing module is connected with described m storer arbitration modules, and is connected with a described m storer; Be used to receive the arbitration result of described m storer arbitration modules output, and, export the specified bus master of this arbitration result to according to the read data that the arbitration result storer that this arbitration result is specified is exported;
Wherein, m and n are the natural number greater than 1.
2, the internal memory of support multibus polymorphic type storer according to claim 1 arbitration realization system is characterized in that, each the storer arbitration modules in described m storer arbitration modules includes:
One memory access arbitration module is connected respectively with a described n bus master, is used for from n bus master reception memorizer request of access, and the memory access request that receives is arbitrated, the output arbitration result;
One storer control signal is selected module, with the corresponding connection of described memory access arbitration module, and all be connected with a described n bus master, be used for receiving arbitration result from the memory access arbitration module, and according to arbitration result from the n road internal control signal of n bus master output, the road internal control signal that this arbitration result of selective reception is specified, and the internal control signal that will select exports corresponding storer to.
3, the internal memory of support multibus polymorphic type storer according to claim 2 arbitration realization system is characterized in that described read data processing module comprises:
One data channel is selected module, be connected with described m memory access arbitration module, be used for receiving arbitration result from m memory access arbitration module, read data requirement according to arbitration result and several types of memory, obtain each permission situation of reading of the bus path of n bus master correspondence constantly, and export n bar bus path read whether to allow signal;
N read data selected module, selects module to be connected with described data channel, is used for receiving correspondingly from what data channel was selected n bar bus path that module exports reading whether to allow signal; Each read data selects module all to be connected with all storeies, and is connected with described bus master correspondingly; Be used to receive the read data and the read data useful signal of m storer output, and read whether to allow signal, from m storer, select the read data and the read data useful signal of a storer output, export the bus master of correspondence to according to what receive.
4, the internal memory of support multibus polymorphic type storer according to claim 1 arbitration realization system is characterized in that, also comprises: n the bus interface that connects one to one with a described n bus master;
Correspondingly, the arbitrary storer arbitration modules in described m storer arbitration modules can receive, from n bus master by with its memory access request of sending of bus interface one to one;
Described read data processing module exports the read data of storer output to a described n bus master by n bus interface.
5, the internal memory of support multibus polymorphic type storer according to claim 1 arbitration realization system, it is characterized in that, also comprise: m store control logic module connects one to one with a described m storer, and connects one to one with described m storer arbitration modules;
Described each store control logic module is used for the internal control signal that receives from the storer arbitration modules corresponding with it, and carry out read/write operation according to the internal control signal pair storer corresponding that receives with it, and receive read data and read data useful signal, and output from the storer corresponding with it.
6, according to the internal memory arbitration realization system that wants the described support multibus of claim 1 polymorphic type storer, it is characterized in that, a described m storer is: m dissimilar storeies, the perhaps storer of m same type, perhaps m the storer that the part type is identical.
7, a kind of internal memory arbitration implementation method of supporting multibus polymorphic type storer is characterized in that, comprises the steps:
(1) the arbitrary bus master in n bus master is by the bus interface corresponding with it, to m the storer arbitrary storer arbitration modules in the storer arbitration modules one to one, sends memory access request and internal control signal;
(2) each storer arbitration modules is arbitrated the memory access request that receives according to the arbitration algorithm of storing in it, the output arbitration result, and from bus interface the selective reception internal control signal corresponding with this arbitration result, and carry out read/write operation according to this internal control signal pair storer corresponding with it.
8, the internal memory of support multibus polymorphic type storer according to claim 7 arbitration implementation method is characterized in that, in the described step (2), the arbitration algorithm that each storer arbitration modules adopts comprises:
A) algorithm once arbitrated of each clock period;
Perhaps B) Writing/Reading of every bus master begins to finish as a minimum clock cycle to this time Writing/Reading, and the visit of other bus master can not be inserted in the centre;
Perhaps C) reads and writes the algorithm of arbitration according to fixed priority;
Perhaps D) arrives first first Processing Algorithm;
Perhaps E) dynamic priority algorithm;
Perhaps F) maximum wait period that allows according to each bus path is arranged the access order of each bus master;
Perhaps above-mentioned A) and C), D), E), combination in any F), perhaps B) and C), D), E), combination in any F).
9, arbitrate implementation method according to the internal memory of claim 7 or 8 described support multibus polymorphic type storeies, it is characterized in that, in the described step (2): the storer arbitration modules is carried out read/write operation receiving after the internal control signal corresponding with arbitration result 1 or 1 during above clock period from bus interface to the storer corresponding with it.
10, the internal memory of support multibus polymorphic type storer according to claim 9 arbitration implementation method, it is characterized in that described internal control signal comprises: to the read/write control of storer, byte is selected, read data length, read/write address and write data signal.
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| CN115312094A (en) * | 2022-07-04 | 2022-11-08 | 深圳市紫光同创电子有限公司 | SRAM control system and method, FPGA chip and electronic equipment |
| CN115312094B (en) * | 2022-07-04 | 2024-04-09 | 深圳市紫光同创电子有限公司 | SRAM control system, method, FPGA chip and electronic equipment |
| CN116225346A (en) * | 2023-05-09 | 2023-06-06 | 此芯科技(上海)有限公司 | Memory data access method and electronic equipment |
| CN116860185A (en) * | 2023-09-05 | 2023-10-10 | 深圳比特微电子科技有限公司 | Data access apparatus, system, method, device, chip and medium for SRAM array |
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