CN114490456B

CN114490456B - Circuit module, credit control method, integrated circuit, and storage medium

Info

Publication number: CN114490456B
Application number: CN202111623764.2A
Authority: CN
Inventors: 贾启祥
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2021-12-28
Filing date: 2021-12-28
Publication date: 2024-06-04
Anticipated expiration: 2041-12-28
Also published as: CN114490456A

Abstract

A circuit module, a credit control method, an integrated circuit, and a non-transitory computer storage medium. The circuit module includes: the system comprises a plurality of input ports, a plurality of cache entries, a data survival control module and an arbitration logic module. The plurality of input ports comprises input ports corresponding to the data survival control module, and the data survival control module is configured to output a first control signal to the arbitration logic module in response to the data survival quantity corresponding to the input ports reaching a data quantity threshold corresponding to the input ports, wherein the data survival quantity represents the quantity of data packets currently stored by the plurality of cache entries and received by the input ports; the arbitration logic module is configured to cease releasing credits to the input port in response to receiving the first control signal.

Description

Circuit module, credit control method, integrated circuit, and storage medium

Technical Field

Embodiments of the present disclosure relate to a circuit module, a credit control method, an integrated circuit, and a non-transitory computer storage medium.

Background

In the field of integrated circuits, the switching unit is a unit module commonly used in Network on chip (NoC), and the switching unit includes N input ports and N output ports, which are n×n data switching transmission units, where N is a positive integer. In NoC, the flow control mechanism is mainly used to ensure lossless transmission from node to node and from switching unit to switching unit in the network on chip, and the flow control mechanism can prevent frame loss under the condition of port congestion.

Disclosure of Invention

At least one embodiment of the present disclosure provides a circuit module comprising: the data survival control module is configured to output a first control signal to the arbitration logic module in response to a data survival number corresponding to the input port reaching a data number threshold corresponding to the input port, wherein the data survival number represents a number of data packets currently stored by the plurality of cache entries and received by the input port; the arbitration logic module is configured to cease releasing credits to the input port in response to receiving the first control signal.

For example, at least one embodiment of the present disclosure provides that the circuit module further includes a plurality of output ports, the data survival control module includes a data survival threshold memory, a data survival counter, and a first output sub-module, the data survival counter is configured to add a predetermined value to the number of data survival in response to the input port receiving one data packet, and subtract the predetermined value from the number of data survival in response to one of the data packets stored by the plurality of cache entries received by the input port being output through one output port; the data survival threshold memory is configured to store the data quantity threshold; the first output sub-module is configured to output the first control signal to the arbitration logic module in response to the number of data survivors reaching the number of data threshold.

For example, at least one embodiment of the present disclosure provides that the circuit module further includes a credit control module configured to output a second control signal to the arbitration logic module in response to a number of credits corresponding to the input port reaching a threshold of the number of credits corresponding to the input port, wherein the number of credits represents a number of credits currently owned by the circuit module that sent the data packet to the input port corresponding to the input port; the arbitration logic module is further configured to cease releasing credits to the input port in response to receiving the second control signal.

For example, in a circuit module provided in at least one embodiment of the present disclosure, the credit control module includes a credit threshold memory, a credit counter, and a second output sub-module, wherein the credit counter is configured to add a predetermined value to the number of credits in response to releasing a credit to the input port, and subtract the predetermined value from the number of credits in response to the input port receiving a packet; the credit threshold memory is configured to store the credit number threshold; the second output sub-module is configured to output the second control signal to the arbitration logic module in response to the credit number reaching the credit number threshold.

For example, in a circuit module provided by at least one embodiment of the present disclosure, the plurality of cache entries are shared by the plurality of input ports.

For example, in a circuit module provided in at least one embodiment of the present disclosure, the arbitration logic module is further configured to release credits to the plurality of input ports in response to at least one of the plurality of cache entries not storing information.

For example, the circuit module provided in at least one embodiment of the present disclosure further includes a plurality of output ports, where the input ports include a plurality of virtual channels, and destinations corresponding to the plurality of virtual channels are different from each other, for each virtual channel in the plurality of virtual channels: the data survival control module includes a data survival threshold memory corresponding to the virtual channel, a data survival counter, and a first output sub-module, the data survival number including a channel data survival number corresponding to the virtual channel, the data number threshold including a channel data number threshold corresponding to the virtual channel, the first control signal including a first sub-control signal corresponding to the virtual channel, the channel data survival number representing a number of data packets corresponding to the virtual channel received by the input port stored by the plurality of cache entries, the data survival counter configured to receive one data packet in response to the input port and the data packet corresponding to the virtual channel, add a predetermined value to the channel data survival number, output one of the data packets corresponding to the virtual channel in response to the plurality of cache entries through an output port, subtract the predetermined value from the channel data survival number; the data survival threshold memory is configured to store the channel data quantity threshold; the first output sub-module is configured to output the first sub-control signal to the arbitration logic module in response to the number of lane data survivors reaching the number of lane data threshold, the arbitration logic module being configured to cease releasing credits to the virtual lane of the input port in response to receiving the first sub-control signal.

For example, in a circuit module provided in at least one embodiment of the present disclosure, the input port includes a plurality of virtual channels, and destinations corresponding to the plurality of virtual channels are different from each other, for each virtual channel of the plurality of virtual channels: the credit control module includes a credit threshold memory corresponding to the virtual channel, a credit counter and a second output sub-module, the credit number including a channel credit number corresponding to the virtual channel, the credit number threshold including a channel credit number threshold corresponding to the virtual channel, the second control signal including a second sub-control signal corresponding to the virtual channel, the channel credit number representing a number of credits currently owned by a circuit module sending data packets to the input port corresponding to the virtual channel, the credit counter being configured to add a predetermined value to the channel credit number in response to releasing a credit to the virtual channel, to receive a data packet in response to the input port, and the data packet corresponding to the virtual channel, subtracting the predetermined value from the channel credit number; the credit threshold memory is configured to store the channel credit number threshold; the second output sub-module is configured to output the second sub-control signal to the arbitration logic module in response to the number of lane credits reaching the threshold number of lane credits, the arbitration logic module being configured to cease releasing credits to the virtual lane in response to receiving the second sub-control signal.

For example, in a circuit module provided in at least one embodiment of the present disclosure, the predetermined value is 1.

At least one embodiment of the present disclosure also provides a credit control method applied to a circuit module, wherein the circuit module includes: a plurality of input ports and a plurality of cache entries, the credit control method comprising: for each of the plurality of input ports: recording the survival number of the data corresponding to the input port; and stopping releasing the credit to the input port in response to the data survival number reaching a data number threshold corresponding to the input port, wherein the data survival number represents the number of data packets currently stored by the plurality of cache entries and received by the input port.

For example, in the credit control method provided in at least one embodiment of the present disclosure, the circuit module further includes a plurality of output ports, recording a data survival number corresponding to the input ports, including: and adding a preset value to the data survival number in response to the input port receiving one data packet, and subtracting the preset value from the data survival number in response to the output of one data packet in the data packets stored in the plurality of cache entries and received by the input port through one output port.

For example, in the credit control method provided in at least one embodiment of the present disclosure, the input port includes a plurality of virtual channels, the destinations corresponding to the plurality of virtual channels are different, and each virtual channel in the plurality of virtual channels is: the number of data survivors includes a number of surviving channel data corresponding to the virtual channel, the threshold of data number includes a threshold of number of channel data corresponding to the virtual channel, the number of surviving channel data represents a number of data packets corresponding to the virtual channel received by the input port stored by the plurality of cache entries, the recording of the number of surviving data corresponding to the input port includes: recording the survival number of channel data corresponding to each virtual channel; and stopping releasing the credit to the input port in response to the data survival number reaching the data number threshold corresponding to the input port, including: for each virtual channel of the plurality of virtual channels: and stopping releasing the credit to the virtual channel in response to the survival number of the channel data corresponding to the virtual channel reaching the threshold value of the channel data corresponding to the virtual channel.

For example, the credit control method provided in at least one embodiment of the present disclosure further includes: and recording the credit number corresponding to the input port, and stopping releasing the credit to the input port in response to the credit number reaching a credit number threshold corresponding to the input port, wherein the credit number represents the number of credits corresponding to the input port currently owned by a circuit module for transmitting a data packet to the input port.

For example, in a credit control method provided in at least one embodiment of the present disclosure, recording the number of credits corresponding to the input port includes: adding a predetermined value to said number of credits in response to releasing a credit to said input port, subtracting said predetermined value from said number of credits in response to said input port receiving a data packet.

For example, in the credit control method provided in at least one embodiment of the present disclosure, the input port includes a plurality of virtual channels, the destinations corresponding to the plurality of virtual channels are different, and each virtual channel in the plurality of virtual channels is: the credit number includes a channel credit number corresponding to the virtual channel, the credit number threshold includes a channel credit number threshold corresponding to the virtual channel, the channel credit number represents a number of credits currently owned by a circuit module that sends a data packet to the input port and corresponding to the virtual channel, and recording the credit number corresponding to the input port includes: recording the channel credit number corresponding to each virtual channel; and stopping releasing the credit to the input port in response to the credit number reaching a credit number threshold corresponding to the input port, including: for each virtual channel of the plurality of virtual channels: and stopping releasing the credit to the virtual channel in response to the channel credit number corresponding to the virtual channel reaching a channel credit number threshold corresponding to the virtual channel.

For example, in the credit control method provided in at least one embodiment of the present disclosure, the circuit module further includes: and the arbitration logic module is used for stopping releasing credit to the input port in response to the data survival quantity reaching a data quantity threshold corresponding to the input port, and comprises the following steps: outputting a first control signal to the arbitration logic module in response to the data survival number corresponding to the input port reaching a data number threshold corresponding to the input port; the arbitration logic module stops releasing credits to the input port in response to receiving the first control signal.

For example, in the credit control method provided in at least one embodiment of the present disclosure, the plurality of cache entries are shared by the plurality of input ports, and the credit control method further includes: and releasing credit to the plurality of input ports in response to at least one cache entry of the plurality of cache entries not storing information.

For example, in a credit control method provided by at least one embodiment of the present disclosure, releasing credits to the plurality of input ports includes: determining a selected input port in the plurality of input ports according to the port sequence corresponding to the plurality of input ports; and releasing credit to the selected input port in response to the data survival quantity corresponding to the selected input port not reaching the data quantity threshold corresponding to the selected input port.

At least one embodiment of the present disclosure also provides an integrated circuit comprising a circuit module according to any one of the embodiments of the present disclosure.

At least one embodiment of the present disclosure also provides a non-transitory computer storage medium storing computer-executable instructions, wherein the computer-executable instructions, when executed by a computer, cause the computer to perform a credit control method according to any embodiment of the present disclosure.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

Fig. 1A is a schematic diagram of a single-shared fluidic mechanism provided by some embodiments of the present disclosure;

Fig. 1B is a schematic diagram of a shared flow control mechanism provided by some embodiments of the present disclosure;

FIG. 2A is a schematic block diagram of a circuit module provided by some embodiments of the present disclosure;

FIG. 2B is a schematic block diagram of another circuit module provided by some embodiments of the present disclosure;

fig. 3 is a schematic block diagram of a data survival control module provided by some embodiments of the present disclosure;

FIG. 4 is a schematic block diagram of a credit control module provided by some embodiments of the disclosure;

FIG. 5 is a schematic diagram of a circuit module according to some embodiments of the present disclosure;

FIG. 6 is a schematic diagram of another circuit module provided in some embodiments of the present disclosure;

FIG. 7A is a schematic flow chart diagram of a credit control method provided by at least one embodiment of the present disclosure;

FIG. 7B is a schematic flow chart diagram of a credit control method provided by at least one embodiment of the present disclosure;

FIG. 8 is a schematic block diagram of an integrated circuit provided in accordance with at least one embodiment of the present disclosure;

FIG. 9 is a schematic block diagram of a credit control device provided in accordance with at least one embodiment of the present disclosure;

Fig. 10 is a schematic diagram of a non-transitory computer storage medium according to at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits a detailed description of some known functions and known components.

In an integrated circuit, an upstream module transmits a data packet to a downstream module based on a Credit (Credit) released by the downstream module to the upstream module. How many free cache entries are in the cache queue of the downstream module, how many credits can be released to the upstream module, and after the upstream module receives the credits, the downstream module can transmit the data packet. The upstream module and the downstream module are both circuit modules in an integrated circuit.

Currently, the commonly used lossless flow control mechanism is mainly based on a credit-based mode. The lossless flow control mechanism of the credit-based designs an accurate flow control mechanism for network-on-chip transmission by adding a counter at the output port of an upstream module (which may be a host (master) in a master-slave mode, or a switch unit, etc.), if the upstream module is a switch unit, adding a counter at each output port of the switch unit, so as to design an accurate flow control mechanism for the network-on-chip transmission, wherein the value of the counter of the output port of the upstream module represents the number of idle buffer entries corresponding to the input port of the downstream module corresponding to the output port of the upstream module, and by judging whether the value of the counter in the upstream module is 0, it is determined whether all buffer entries in the buffer queue of the downstream module have already stored data packets, so as to determine whether to send the data packets to the downstream module. Each time the output port of the upstream module sends a data packet to the input port of the downstream module, the counter corresponding to the output port of the upstream module is decremented by 1. When a new free cache entry is in the cache queue of the downstream module and is allocated to the input port, credit may be released to the output port of the upstream module (corresponding to the input port), and the value of the counter corresponding to the output port of the upstream module is incremented by 1.

The method is an accurate flow control mechanism, and meanwhile, the phenomenon that the data packet is lost due to the fact that the upstream module continues to send the data packet under the condition that all cache entries in a cache queue of the downstream module store the data packet can be avoided. One of the main features of the credit-based flow control is that the value of the counter in the upstream module needs to correspond to the cache entry in the downstream module to ensure that the data packet sent by obtaining the credit can accurately enter the cache queue of the downstream module without being lost.

Fig. 1A is a schematic diagram of a single-shared-fluid control mechanism according to some embodiments of the present disclosure. Fig. 1A is a schematic diagram of the allocation of buffers (buffers) in a credit-based single-shared-flow control mechanism.

As shown in fig. 1A, for one circuit module 100, taking a switching unit of 4*4 as an example of the circuit module 100, that is, the circuit module 100 includes four input ports (i.e., an input port 101A, an input port 101b, an input port 101c, and an input port 101 d) and four output ports (i.e., an output port 102a, an output port 102b, an output port 102c, and an output port 102 d), the upstream module 110 includes four counters 104a to 104d corresponding to the four input ports 101A to 101d one by one, the counter 104a corresponds to the input port 101A, the counter 104b corresponds to the input port 101b, the counter 104c corresponds to the input port 101c, and the counter 104d corresponds to the input port 101 d.

As shown in fig. 1A, assuming that the circuit module 100 includes 24 buffers 103, in general, 24 buffers 103 may be equally allocated to four input ports 101A to 101d, and a corresponding number of credits may be released to the upstream module 110 of the circuit module 100, for example, 6 buffers for each input port, so that each input port may release 6 credits to the upstream module 110. At this time, the maximum value of each of the counters 104a to 104d is 6.

The number of credits that each input port needs to allocate is typically determined based on the credit cycle (credit loop) and the bandwidth requirements of each input port. Assuming that 3 clock cycles (cycles) are required for the upstream module to send a data packet to the buffer of the downstream module, the downstream module processes the data packet and releases a new message to the counter of the upstream module, and the credit loop is 6, at this time, 6 credits are allocated to each input port, so that the use efficiency of the transmission link can be guaranteed to reach 1 packet/cycle (i.e. 1 data packet is sent out per cycle). If the target bandwidth corresponding to the input port is 0.5packet/cycle, each input port only needs to be allocated with 3 credits.

One feature of the exclusive flow control mechanism is: each time a data packet buffered in a circuit module is sent out to a corresponding downstream module of the circuit module, a new credit may be released to the corresponding input port.

Disadvantages of the shared-nothing flow control mechanism include: firstly, in order to ensure that each input port can reach a target bandwidth, each input port needs to allocate enough credit (reference credit loop), when the number of input ports is large and the credit loop corresponding to each input port is relatively large, the buffer size (buffer size) of the circuit module becomes large, which is not beneficial to timing convergence under high frequency; second, if some input ports of the circuit module only have a certain bandwidth requirement in a time-division manner, a sufficient number of cache entries are statically allocated to the input ports, which can reduce the resource utilization of the cache queue. For example, the four input ports 101A-101D of the circuit module 100 in fig. 1A each have data transmission during four time periods (e.g., time window A, B, C, D), i.e., the input port 101A has data transmission during time window a, the input port 101B has data transmission during time window B, the input port 101C has data transmission during time window C, and the input port 101D has data transmission during time window D, and if the time periods of time window A, B, C, D do not overlap, then the resource utilization of the buffer queue does not exceed 25%.

Fig. 1B is a schematic diagram of a shared flow control mechanism provided in some embodiments of the present disclosure. Fig. 1B is a schematic diagram of allocation of buffers in a shared-flow control mechanism of credit-based. In fig. 1A and 1B, the same drawing indicates the same meaning, and the repetition is not repeated.

As shown in fig. 1B, it is assumed that the circuit module 100 includes a buffer queue composed of 24 buffers, each of which is shared by four input ports of the circuit module 100. In the initial state, 24 buffers in the buffer queue are all idle buffers. A configurable threshold register may be added to each input port, as shown in fig. 1B, with a threshold register 105a for input port 101a, a threshold register 105B for input port 101B, a threshold register 105c for input port 101c, and a threshold register 105d for input port 101 d. The value stored in the threshold register corresponding to each input port represents a threshold of the number of credits that the input port can release to the corresponding upstream module, i.e. the value stored in the threshold register corresponding to each input port is the credit threshold corresponding to that input port. For example, if the value stored in the threshold register corresponding to the input port is 4, it means that the input port can release 4 credits to the corresponding upstream module at most, and at this time, 16 buffers 103a of the 24 buffers are allocated to each input port, and 8 free buffers 103b are also provided in the buffer queue. Each input port of the circuit module 100 receives a data packet and can immediately release a new credit to the input port, i.e. release the credit corresponding to the input port to the upstream module corresponding to the circuit module 100, without waiting for the data packet to be sent to the downstream module corresponding to the circuit module 100. Whenever the circuit module 100 sends a packet to a downstream module, it indicates that a buffer is released, which acts as an empty buffer. For example, if the credit number of the plurality of input ports (the number of credits indicating that the input port has released to the corresponding upstream module at the current time) does not reach the credit threshold, each time the number of free buffers is greater than 0, the input ports are polled in turn according to the port number of the input port to release credits until the credit number of a certain input port meets the credit threshold, and then the credit release of the input port is skipped.

The shared flow control mechanism can maximize the buffer utilization rate, and for input ports with low bandwidth requirements, the value stored in the corresponding threshold register can be configured to be smaller. For input ports with high bandwidth requirements, the value stored in the corresponding threshold register can be configured to be larger. Since the buffer is shared among all input ports, for input ports with frequent transmission, idle buffers can be frequently utilized, and the buffer utilization can be maximized.

One feature of the shared flow control mechanism is: as long as the buffer queue has an idle buffer, the data packets which are not needed to wait for the credit release of the upstream module can be sent to the downstream module, so that the credit loop is reduced.

However, the shared flow control mechanism has the following drawbacks: first, since the opportunities for each input port to obtain credit are equal when competing for credit, if a certain input port can compete for credit, the transmission conditions of all input ports need to be seen, which results in that the target bandwidth that can be achieved by a certain input port cannot be controlled accurately. For example, as shown in fig. 1B, for packet transmission from the input port 101a to the output port 102a, if the upstream module corresponding to the input port 101a transmits a relatively dense packet, the downstream module corresponding to the output port 101a processes the data relatively slowly, which may cause frequent credit to be taken away by the input port 101a, and the packet sent by the input port 101a cannot be timely output to the downstream module, so that most of the buffers in the circuit module 100 store the packet received by the input port 101a, and it is difficult for other input ports to reassign to obtain the credit. Second, there is a risk of deadlock in extreme cases. As described above, in an extreme case, there may be a case where all buffers of the circuit module 100 are occupied by data packets of the input port 101a, and if processing of a downstream module corresponding to the input port 101a requires data packets received by other input ports of the circuit module 100, deadlock may be caused because the other input ports have no credit available.

From the above description of fig. 1A and fig. 1B, the inventor finds that in the prior art, either the buffer queue resource utilization is not high, or buffer size is very unfavorable for timing convergence at high frequency, or bandwidth cannot be controlled precisely, or there is a risk of deadlock.

At least one embodiment of the present disclosure provides a circuit module. The circuit module may include a plurality of input ports, a plurality of cache entries, a data survival control module, and an arbitration logic module. The plurality of input ports comprises input ports corresponding to the data survival control module, and the data survival control module is configured to output a first control signal to the arbitration logic module in response to the data survival quantity corresponding to the input ports reaching a data quantity threshold corresponding to the input ports, wherein the data survival quantity represents the quantity of data packets currently stored by the plurality of cache entries and received by the input ports; the arbitration logic module is configured to cease releasing credits to the input port in response to receiving the first control signal.

In the circuit module provided by the embodiment of the disclosure, the data survival control module is set for the input port, so that the number of data packets received by each input port stored by the cache entry in the circuit module can be controlled, a certain input port is prevented from occupying more cache entries, and the resource utilization rate of a cache queue comprising a plurality of cache entries is improved on the premise of ensuring the bandwidth of each input port, so that the cache queue can be minimized, and timing convergence under high frequency is facilitated. The circuit module provided by the embodiment of the disclosure has the advantages of the single-shared flow control mechanism and the shared flow control mechanism, so that the bandwidth control problem of each input port is solved, the utilization rate problem of the buffer queue is solved, the potential deadlock risk is avoided, and the data transmission efficiency and the time sequence convergence efficiency are greatly optimized.

At least one embodiment of the present disclosure also provides a credit control method, an integrated circuit, and a non-transitory computer storage medium applied to the above-described circuit module.

Embodiments of the present disclosure will be described in detail below with reference to the attached drawings, but the present disclosure is not limited to these specific embodiments.

Fig. 2A is a schematic block diagram of one circuit module provided by some embodiments of the present disclosure, and fig. 2B is a schematic block diagram of another circuit module provided by some embodiments of the present disclosure.

For example, the circuit module 200 may be one module in an integrated circuit. In a specific circuit design process of an integrated circuit, the integrated circuit may be divided into tens and hundreds of modules for design. For example, the modules may be divided according to the functions and the positional relationship of the modules, each module may implement a specific function, and the modules perform data interaction through ports (for example, an input port (input port) and an output port (output port)). For example, in transmitting data, when the circuit module 200 receives a data packet, the circuit module 200 is a downstream module, and when the circuit module 200 sends a data packet to other modules, the circuit module 200 is an upstream module. In the embodiments of the present disclosure, the circuit module 200 is illustrated as a downstream module, but it should be understood that the upstream module and the downstream module are merely used to distinguish between sending out data packets and receiving data packets, and are not any remaining limitations of the circuit module 200.

For example, in some embodiments, the circuit module 200 may be a switching unit or the like for performing data exchange transmissions.

As shown in fig. 2A, in some embodiments of the present disclosure, a circuit module 200 may include a plurality of input ports 201, a plurality of cache entries 202, a data survival control module 203, and an arbitration logic module 204.

For example, the number of the plurality of input ports 201 may be determined according to actual circumstances, and the embodiment of the present disclosure is not limited.

For example, multiple cache entries 202 may form a cache queue. For example, in some embodiments, the cache entry 202 may be a buffer (buffer) or the like that may cache the data packet.

For example, each cache entry 202 may cache one data packet.

For example, in some embodiments, the plurality of cache entries 202 are each shared cache entries, i.e., the plurality of cache entries 202 are each shared by the plurality of input ports 201, that is, each cache entry may be used by any of the plurality of input ports 201. However, the disclosure is not limited thereto, and in other embodiments, the plurality of cache entries 202 may include a plurality of private cache entries and a plurality of shared cache entries, with a private cache entry corresponding to an input port representing a cache entry used by the input port alone. The input ports 201 may correspond to the use of at least one dedicated cache entry, with multiple shared cache entries being shared by multiple input ports 201. In the embodiments of the present disclosure, the sharing of the plurality of cache entries 202 by the plurality of input ports 201 is illustrated as an example.

For example, the plurality of input ports 201 includes an input port 201a corresponding to the data survival control module 203, and the data survival control module 203 is configured to output a first control signal to the arbitration logic module 204 in response to the number of data survival corresponding to the input port 201a reaching a data number threshold corresponding to the input port 201 a.

For example, the number of surviving data packets corresponding to the input port 201a indicates the number of data packets received by the input port 201a currently stored (at the present moment) by the plurality of cache entries 202, that is, indicates the number of data packets received by the input port 201a that are currently surviving, that is, indicates the upper limit of the number of surviving data packets received by the input port 201 a.

For example, the data number threshold corresponding to the input port 201a indicates the maximum value of the number of data packets received by the input port 201a currently stored by the plurality of cache entries 202, that is, the maximum value of the number of cache entries storing the data packets received by the input port 201a at the present time.

For example, the threshold value of the data amount corresponding to each input port 201 may be set according to the actual situation. For example, in some embodiments, the threshold amount of data corresponding to input port 201a may be 6. For example, the threshold value of the number of data corresponding to the input port 201 may be determined according to the number of multiple cache entries, the credit period of the input port, the packet transmission condition, the bandwidth requirement, and so on.

For example, the thresholds of the data amounts corresponding to the input ports 201 may be different from each other, or may be at least partially the same, which is set according to the actual situation, which is not limited by the embodiments of the present disclosure.

It should be noted that, in the embodiment of the present disclosure, the "surviving packet" indicates that the packet is stored in a cache entry of the circuit module, that is, the packet is not yet sent to the downstream module corresponding to the circuit module 200.

For example, the arbitration logic module 204 is configured to cease releasing credits to the input port 201a (i.e., to cease releasing credits to the circuit module that sent the data packet to the input port 201 a) in response to receiving the first control signal. That is, when the arbitration logic module 204 receives the first control signal, the release of the credit to the input port 201a is stopped, so that the excessive buffer entries are prevented from being allocated to the input port 201a, and the phenomenon that the data packets are lost due to the excessive transmission of the data packets to the input port 201a by the upstream module can be avoided, and the resource utilization rate of the buffer queue including a plurality of buffer entries is improved on the premise of ensuring the bandwidth of the input port 201a, so that the buffer queue can be minimized, and the time sequence convergence under high frequency is facilitated.

For example, as shown in fig. 2B, in some embodiments, the circuit module 200 may also include a credit control module 205. Credit control module 205 also corresponds to input port 201 a.

For example, the credit control module 205 is configured to output a second control signal to the arbitration logic module 204 in response to the number of credits corresponding to the input port 201a reaching a threshold number of credits corresponding to the input port 201 a.

For example, the number of credits corresponding to the input port 201a indicates the number of credits corresponding to the input port 201a currently owned by the circuit module sending the data packet to the input port 201a, and the credit control module 205 may control the number of credits released to the input port 201a to avoid releasing too many credits to the input port 201 a.

For example, the credit number threshold corresponding to the input port 201a represents the maximum value of the number of credits corresponding to the input port 201a currently owned by the circuit module that transmits the data packet to the input port 201a, that is, the maximum value of the number of free cache entries allocated to the input port. In an embodiment of the present disclosure, the cache entry that does not store a data packet is a free cache entry.

For example, the threshold of the credit number corresponding to each input port 201 may be set according to practical situations, for example, may be determined according to the credit period and bandwidth requirement of the input port. For example, in some embodiments, the credit number threshold corresponding to input port 201a may be 4.

For example, the threshold values of the credit numbers corresponding to the input ports 201 may be different from each other, or may be at least partially the same, which is set according to practical situations, which is not limited in the embodiments of the present disclosure.

For example, the arbitration logic module 204 is further configured to cease releasing credits to the input port 201a in response to receiving the second control signal.

For example, in some embodiments, the arbitration logic module 204 is further configured to release credit to the plurality of input ports 201 in response to at least one of the plurality of cache entries 202 not storing information, i.e., the at least one cache entry does not store a data packet.

The manner in which credits are released to the plurality of input ports 201 is not limited by the present disclosure, for example, in some embodiments, when releasing credits to the plurality of input ports 201, the arbitration logic module 204 is configured to determine a selected input port of the plurality of input ports 201 in a port order corresponding to the plurality of input ports 201; and releasing credit to the selected input port in response to the data survival quantity corresponding to the selected input port not reaching the data quantity threshold corresponding to the selected input port. Port numbers (e.g., 1, 2, 3, etc.) may be set for the plurality of input ports 201, respectively, and the port order corresponding to the plurality of input ports 201 may represent an order (ascending or descending) of the port numbers corresponding to the plurality of input ports 201, respectively. For example, if the circuit module 200 includes an empty cache entry, credit may be released to the input port with port number 1, then when the circuit module 200 transmits a data packet to its corresponding downstream module, an empty cache entry is released, at this time, credit may be released to the input port with port number 2, and so on, and the credit may be released to each input port in the order of port numbers.

When the credit control module 205 is provided for each input port 201, when releasing credits to a certain input port, it is required to first determine whether the number of credits corresponding to the input port reaches the threshold of the number of credits corresponding to the input port, and if the number of credits corresponding to the input port reaches the threshold of the number of credits corresponding to the input port, then release of credits to the input port is skipped, i.e. no credit is released to the input port, and determine whether to release credits to the remaining input ports based on the port order. And if the credit numbers corresponding to all the input ports reach the corresponding credit number threshold, not releasing the credit until the credit number corresponding to any input port is smaller than the corresponding credit number threshold.

For example, the circuit module 200 may set a plurality of data survival control modules 203 corresponding to the plurality of input ports 201 one by one, and may set a plurality of credit control modules 205 corresponding to the plurality of input ports 201 one by one, that is, one data survival control module 203 and one credit control module 205 are set for each input port 201, so as to control the number of data packets received by each input port stored by the buffer entries, and on the premise of guaranteeing the bandwidth of each input port, improve the resource utilization rate of the buffer queue including the plurality of buffer entries, so that the buffer queue can be minimized, which is beneficial to timing convergence under high frequency.

For example, the arbitration logic module 204 may be implemented in hardware, software, firmware, or any feasible combination thereof, or may include code and programs stored in memory; the processor may execute the code and programs to implement some or all of the functions of arbitration logic module 204 as described above. In other embodiments, the arbitration logic module 204 may be a dedicated hardware device that performs some or all of the functions of the arbitration logic module 204 as described above. For example, the arbitration logic module 204 may be a circuit board or a combination of circuit boards for implementing the functions described above. In embodiments of the present disclosure, the circuit board or combination of circuit boards may include: (1) one or more processors; (2) One or more non-transitory computer-readable memories coupled to the processor; and (3) firmware stored in the memory that is executable by the processor.

Fig. 3 is a schematic block diagram of a data survival control module provided in some embodiments of the present disclosure.

For example, in some embodiments, the circuit module 200 further includes a plurality of output ports. For example, the number of the plurality of output ports may be the same as the number of the plurality of input ports 201, however, the present disclosure is not limited thereto, and the number of the plurality of output ports may be the same as the number of the plurality of input ports 201. The data packet received by each input port 201 may be output through any one of a plurality of output ports.

As shown in fig. 3, in some embodiments, the data survival control module 203 includes a data survival threshold memory 2031, a data survival counter 2032, and a first output submodule 2033.

For example, the data survivor counter 2032 is configured to add a predetermined value to the number of data survivors in response to the input port 201a receiving one packet, and subtract the predetermined value from the number of data survivors in response to one packet out of the packets received by the input port 201a stored in the plurality of cache entries being output through one output port.

For example, in some embodiments, the predetermined value is 1.

For example, the data survival counter 2032 may be implemented as any element that can perform a count, e.g., the data survival counter 2032 may be a counter, e.g., an up counter, a down counter, or a reversible counter, etc.

For example, the data survival threshold memory 2031 is configured to store a data amount threshold.

For example, in some embodiments, the data survival threshold memory 2031 may be implemented as any type of register, e.g., a data register. Embodiments of the present disclosure are not limited thereto, and the data survival threshold memory 2031 may be implemented as any element that can store data, e.g., a memory, etc.

For example, the first output submodule 2033 is configured to output a first control signal to the arbitration logic module 204 in response to the number of data survivors reaching the number of data threshold.

For example, any of the data survival threshold memory 2031, the data survival counter 2032, and the first output submodule 2033 may be implemented in hardware, software, firmware, or any feasible combination thereof.

Fig. 4 is a schematic block diagram of a credit control module provided by some embodiments of the disclosure.

For example, as shown in fig. 4, in some embodiments, the credit control module 205 includes a credit threshold memory 2051, a credit counter 2052, and a second output submodule 2053.

For example, the credit counter 2052 is configured to add a predetermined value to the number of credits in response to releasing a credit to the input port 201a, and subtract the predetermined value from the number of credits in response to the input port 201a receiving a packet. For example, "release one credit to the input port 201 a" means that the circuit module transmitting the data packet to the input port 201a releases the credit corresponding to the input port 201a, and the circuit module transmitting the data packet to the input port 201a with respect to the input port 201a is the upstream module corresponding to the input port 201 a.

For example, each input port 201 receives data packets sent out by only one output port of its corresponding upstream module. If the upstream module includes only one output port, the upstream module sends the data packet to only the input port 201a through the output port; if the upstream module includes a plurality of output ports, the upstream module sends a packet to the input port 201a through one of the plurality of output ports, for example, each output port in the upstream module is provided with a counter for recording the number of credits, where "releasing a credit to the input port 201 a" means releasing a credit to the output port corresponding to the input port 201a in the upstream module corresponding to the input port 201a, where the number of credits corresponding to the input port 201a is increased by 1, and the value of the counter corresponding to the output port corresponding to the input port 201a is increased by 1.

For example, credit counter 2052 may be implemented as any element that may enable counting, e.g., credit counter 2052 may be a counter, e.g., an up counter, a down counter, or a reversible counter, etc.

For example, credit threshold memory 2051 is configured to store a credit number threshold.

For example, the second output submodule 2053 is configured to output a second control signal to the arbitration logic module 204 in response to the number of credits reaching the credit threshold.

For example, the arbitration logic module 204 is further configured to, in the event that the number of credits corresponding to the input port does not reach the threshold number of credits corresponding to the input port, release credits to the input port until the number of credits corresponding to the input port reaches the threshold number of credits corresponding to the input port.

For example, any of the credit threshold memory 2051, credit counter 2052, and second output submodule 2053 may be implemented in hardware, software, firmware, or any feasible combination thereof.

For example, in some embodiments, if the data number threshold corresponding to the input port 201a is 6 and the credit number threshold corresponding to the input port 201a is 4, when the number of data packets received by the input port 201a is currently stored in the plurality of cache entries 202, it is determined that the data survival number corresponding to the input port 201a (i.e. 6) reaches the data number threshold, so that the first output submodule 2033 outputs the first control signal to the arbitration logic module 204, and at this time, the maximum credit number corresponding to the input port 201a may be 4, so that the upstream module corresponding to the input port 201a may also send 4 data packets to the input port 201a, and thus the maximum number of data packets received by the input port 201a that the plurality of cache directories 202 may store is 10.

For example, in some embodiments, any one or more of the data survival threshold memory 2031, the data survival counter 2032, the first output submodule 2033, the credit threshold memory 2051, the credit counter 2052, and the second output submodule 2053 may include code and programs stored in memory; the processor may execute the code and program to implement some or all of the functions of any one or more of the data-alive threshold memory 2031, the data-alive counter 2032, the first output submodule 2033, the credit threshold memory 2051, the credit counter 2052, and the second output submodule 2053 as described above. In other embodiments, any one or more of the data-alive threshold memory 2031, the data-alive counter 2032, the first output sub-module 2033, the credit threshold memory 2051, the credit counter 2052, and the second output sub-module 2053 may be dedicated hardware devices for implementing some or all of the functionality of any one or more of the data-alive threshold memory 2031, the data-alive counter 2032, the first output sub-module 2033, the credit threshold memory 2051, the credit counter 2052, and the second output sub-module 2053 as described above. For example, any one or more of the data-alive threshold memory 2031, the data-alive counter 2032, the first output sub-module 2033, the credit threshold memory 2051, the credit counter 2052, and the second output sub-module 2053 may be one circuit board or a combination of circuit boards for realizing the functions as described above. In embodiments of the present disclosure, the circuit board or combination of circuit boards may include: (1) one or more processors; (2) One or more non-transitory computer-readable memories coupled to the processor; and (3) firmware stored in the memory that is executable by the processor.

Fig. 5 is a schematic structural diagram of a circuit module according to some embodiments of the present disclosure.

As shown in fig. 5, in one embodiment, the circuit module 200 may be implemented as a switching unit 300.

As shown in fig. 5, the switching unit 300 of 4*4 is taken as an example, that is, the switching unit 300 includes four input ports (i.e., input port 301a, input port 301b, input port 301c, and input port 301 d) and four output ports (i.e., output port 302a, output port 302b, output port 302c, and output port 302 d).

For example, in some embodiments, as shown in FIG. 5, four input ports 301 a-301 d correspond to the same upstream module 310, i.e., receiving data sent by the upstream module 310 includes. The upstream module 310 may include four output ports (not shown) corresponding to the four input ports 301a to 301d one by one to transmit data packets to the four input ports 301a to 301d, respectively, the four output ports of the upstream module 310 are provided with four counters 304a to 304d corresponding to each other, the output port corresponding to the counter 304a transmits data packets to the input port 301a, the output port corresponding to the counter 304b transmits data packets to the input port 301b, the output port corresponding to the counter 304c transmits data packets to the input port 301c, and the output port corresponding to the counter 304d transmits data packets to the input port 301 d. For another example, the four input ports 301 a-301 d may correspond to different upstream modules, which is not limited by the disclosure, and a corresponding counter may be set in the upstream module corresponding to each input port for recording the credit released by the input port.

Assuming that the switch unit 300 includes 24 cache entries, in the initial state, the 24 cache entries are all free cache entries. It should be noted that the number of cache entries may be set according to practical situations, and is not limited thereto.

For example, the credit number thresholds corresponding to the four input ports 301a to 301d of the switch unit 300 may be the same, for example, all are 4, and at this time, as shown in fig. 5, 16 cache entries 303a of the 24 cache entries may be equally allocated to the four input ports 301a to 301d, that is, each input port of the switch unit 300 uses 4 cache entries 303a. As shown in fig. 5, the remaining 8 cache entries 303b of the 24 cache entries are free cache entries.

After allocating a cache entry to each input port, a corresponding number of credits may be released to the corresponding upstream module 310 of the switch unit 300, e.g., 4 credits may be released per input port. For example, the maximum value of each of the counters 304a to 304d is 4. The working principles of the counters 304 a-304 d are the same, taking the counter 304a as an example, the count value of the counter 304a is incremented by 1 whenever the input port 301a releases a credit to the upstream module 310, and the count value of the counter 304a is decremented by 1 whenever the upstream module 310 sends a data packet to the input port 301 a.

For example, a credit control module and a data survival control module are configured for each input port, the credit control module includes a credit threshold memory, the data survival control module includes a data survival threshold memory, and the credit number threshold and the data number threshold corresponding to each input port can be modified according to the configuration of the requirement, i.e. the value stored in the credit threshold memory and the value stored in the data survival threshold memory can be modified according to the configuration of the requirement. For example, as shown in fig. 5, input port 301a corresponds to credit threshold memory 305a and data-surviving threshold memory 306a, input port 301b corresponds to credit threshold memory 305b and data-surviving threshold memory 306b, input port 301c corresponds to credit threshold memory 305c and data-surviving threshold memory 306c, and input port 301d corresponds to credit threshold memory 305d and data-surviving threshold memory 306d.

It should be noted that the data survival control module further includes a data survival counter and a first output sub-module (not shown), and the credit control module further includes a credit counter and a second output sub-module (not shown).

For example, as shown in fig. 5, the interaction unit 300 may include an arbitration logic module 307.

Every time a credit is released to an input port, adding 1 to the count value of the credit counter corresponding to the input port (i.e. the credit number corresponding to the input port); each time a data packet is received by an input port, the count value of the credit counter corresponding to the input port is subtracted by 1. When the credit number corresponding to the input port reaches the credit number threshold corresponding to the input port, the second output sub-module feeds back to the arbitration logic module 307, that is, the second output sub-module outputs a second control signal to the arbitration logic module 307, so that the arbitration logic module 307 no longer releases the credit to the input port.

The count value of the data survivor counter corresponding to the input port (i.e., the number of data survivors corresponding to the input port) is incremented by 1 each time a packet in the packets received by the input port stored by the plurality of cache entries is sent to one output port (any one of output ports 302 a-302 d), the count value of the data survivor counter corresponding to the input port is decremented by 1. When the data survival number corresponding to the input port reaches the data number threshold corresponding to the input port, the first output submodule feeds back to the arbitration logic module 307, that is, the first output submodule outputs the first control signal to the arbitration logic module 307, so that the arbitration logic module 307 does not release the credit to the input port any more, even if the credit number corresponding to the input port does not reach the credit number threshold at this time.

In the embodiment of the present disclosure, when the arbitration logic module 307 receives any one of the first control signal and the second control signal, the release of the credit to the input port corresponding to the first control signal, that is, the release of the credit to the circuit module that sends the data packet to the input port, is stopped. For example, when the arbitration logic module 307 receives the first control signal, the credit release to the input port is stopped, regardless of whether the second control signal is received.

In the embodiment of the disclosure, by setting the data survival control module in the circuit module, the situation that most of cache entries in the circuit module are occupied by a data packet of a certain input port can be avoided, and the deadlock risk can be avoided. Meanwhile, the bandwidth of each input port can be controlled within a certain range, and the buffer queue can be utilized to the maximum degree due to the strategy of sharing the buffer queue still adopted, and the buffer queue entry can be minimized according to the bandwidth requirement, so that the time sequence is easy to converge under high frequency.

The circuit module provided by the disclosure is added with the data survival control module on the basis of the shared flow control mechanism, so that the condition of the data packet received by each input port stored in the buffer memory entry is monitored, and the data packet is timely fed back to the arbitration logic module, so that the credit release number of each input port is dynamically adjusted, the problem of the utilization rate of the buffer memory queue is solved, the potential deadlock risk is avoided, and the data transmission efficiency and the time sequence convergence efficiency are greatly optimized.

For example, in embodiments of the present disclosure, both the input port and the output port represent actual physical ports.

For example, in some embodiments, each input port 201 of the circuit module 200 may be subdivided into a plurality of Virtual Channels (VC) again, i.e., each input port 201 may include a plurality of Virtual channels. The destination corresponding to the plurality of virtual channels is different, and the destination corresponding to each virtual channel represents the destination to which the data packet corresponding to the virtual channel is destined, i.e. the destination of the data packet corresponding to the plurality of virtual channels is different. For example, "destination" means the element/module to which the packet eventually arrives.

For example, for performing data reading and writing operations on two modules, the two modules are respectively a module a and a module B, if the module a sends a reading request to the module B to read data from the module B, the destination to which the reading request is sent is the module B, the reading request may correspond to one virtual channel a1 in one input port P, when the read data is transferred from the module B to the module a, the destination to which the read data is sent is the module a, and at this time, the read data may correspond to the other virtual channel a2 in the input port P; if the module a sends a write request to the module B to write data to the module B, the write request and the data to be written are both destined for the module B, and the write request and the data to be written may both correspond to a virtual channel a1 in the input port P.

For another example, the Central Processing Unit (CPU) may read data from different places, for example, the Central Processing Unit (CPU) may read data from the main memory or may read data from the input/output device, where the read request issued by the Central Processing Unit (CPU) to the main memory and the read request issued to the input/output device may correspond to different virtual channels of the same input port.

Note that, in the circuit module 200, each of some of the plurality of input ports includes a plurality of virtual channels, and another of the plurality of input ports does not include a virtual channel; or each of the plurality of input ports includes a plurality of virtual channels; or each of the plurality of input ports does not include a virtual channel.

When each input port includes multiple virtual lanes, then the credits for each input port may be partitioned by virtual lane, e.g., if the input port includes 2 virtual lanes, the packet corresponding to the first of the 2 virtual lanes represents the packet destined for destination 0, and the packet corresponding to the second of the 2 virtual lanes represents the packet destined for destination 1. Accordingly, when the input port releases the credits to the corresponding upstream module, the input port is also subdivided into credits of different virtual channels, for example, the credits corresponding to the first virtual channel and the credits corresponding to the second virtual channel, so that the data flow and the bandwidth to each destination can be accurately controlled.

For example, the data packet corresponding to each virtual channel may be output through any one of the plurality of output ports. The data packet corresponding to the first virtual channel may be output through the output port 0, and the data packet corresponding to the second virtual channel may be output through the output port 1.

It should be noted that, in the embodiment of the present disclosure, when the input port is not divided into a plurality of virtual channels, the input port may correspond to having only one virtual channel.

For example, for each virtual channel of a plurality of virtual channels included by the input port 201 a: the data survival control module corresponding to the input port 201a includes a data survival threshold memory, a data survival counter, and a first output sub-module corresponding to the virtual channel. That is, in the embodiment of the present disclosure, a set of elements corresponding to the data survival number and the data number threshold, that is, the data survival threshold memory, the data survival counter, and the first output sub-module may be set for each virtual channel, so that the number of data packets corresponding to the virtual channel stored by the cache entry in the circuit module may be controlled, a certain virtual channel may be avoided from occupying more cache entries, and on the premise of guaranteeing the bandwidth of each input port, the resource utilization of the cache queue including a plurality of cache entries may be improved, so that the cache queue may be minimized, which is beneficial to timing convergence under high frequency, and the data flow and bandwidth to each destination may be precisely controlled.

For example, for each virtual channel of a plurality of virtual channels included by the input port 201 a: the data survival number corresponding to the input port 201a includes a channel data survival number corresponding to the virtual channel, the data number threshold corresponding to the input port 201a includes a channel data number threshold corresponding to the virtual channel, and the first control signal corresponding to the input port 201a includes a first sub-control signal corresponding to the virtual channel.

For example, the channel data survival number corresponding to the virtual channel indicates the number of data packets corresponding to the virtual channel received by the input port 201a stored by the plurality of cache entries. The channel data number threshold corresponding to the virtual channel represents the maximum value of the number of data packets corresponding to the virtual channel currently stored by the plurality of cache entries 202 and received by the input port 201 a.

For example, the data survival counter corresponding to the virtual channel is configured to receive a data packet in response to the input port, and the data packet corresponds to the virtual channel, add a predetermined value (e.g., 1) to the number of channel data survival corresponding to the virtual channel, and subtract the predetermined value from the number of channel data survival corresponding to the virtual channel in response to one of the data packets corresponding to the virtual channel stored in the plurality of cache entries being output through an output port.

For example, the data survival threshold memory corresponding to the virtual channel is configured to store a channel data amount threshold corresponding to the virtual channel.

For example, the channel data number threshold values corresponding to the virtual channels may be different from each other or may be partially the same.

For example, the first output sub-module corresponding to the virtual channel is configured to output a first sub-control signal corresponding to the virtual channel to the arbitration logic module 204 in response to the surviving number of channel data corresponding to the virtual channel reaching the threshold number of channel data corresponding to the virtual channel.

For example, the arbitration logic module 204 is further configured to cease releasing credits to the virtual channel of the input port in response to receiving the first sub-control signal corresponding to the virtual channel.

For example, for each virtual channel of a plurality of virtual channels included by the input port 201 a: the credit control module corresponding to the input port 201a includes a credit threshold memory corresponding to the virtual channel, a credit counter, and a second output sub-module. That is, in embodiments of the present disclosure, a set of elements corresponding to the number of credits and the threshold of the number of credits, namely the credit threshold memory, the credit counter, and the second output sub-module, may be provided for each virtual channel, so that the number of credits released to each virtual channel may be controlled, avoiding that a certain virtual channel occupies more cache entries.

For example, for each virtual channel of a plurality of virtual channels included by the input port 201 a: the credit number corresponding to the input port 201a includes a channel credit number corresponding to the virtual channel, the credit number threshold corresponding to the input port 201a includes a channel credit number threshold corresponding to the virtual channel, and the second control signal corresponding to the input port 201a includes a second sub-control signal corresponding to the virtual channel.

For example, the number of channel credits corresponding to a virtual channel represents the number of credits corresponding to the virtual channel currently owned by a circuit module that sends a data packet to the virtual channel. The channel credit number threshold corresponding to a virtual channel represents the maximum value of the number of credits corresponding to the virtual channel currently owned by the circuit module that sent the data packet to that virtual channel.

For example, the credit counter corresponding to the virtual channel is configured to add a predetermined value to the number of channel credits corresponding to the virtual channel in response to releasing a credit to the virtual channel; in response to the input port receiving a data packet, the data packet corresponds to the virtual channel, subtracting a predetermined value from the channel credit number corresponding to the virtual channel.

For example, the credit threshold memory for the virtual channel is configured to store a channel credit number threshold for the virtual channel.

For example, the second output sub-module corresponding to the virtual channel is configured to output the second sub-control signal corresponding to the virtual channel to the arbitration logic module 204 in response to the channel credit number corresponding to the virtual channel reaching the channel credit number threshold corresponding to the virtual channel.

For example, the channel credit number threshold value corresponding to each virtual channel may be different from each other or may be partially the same.

For example, the arbitration logic module 204 is configured to cease releasing credits to the virtual channel in response to receiving the second sub-control signal corresponding to the virtual channel.

Fig. 6 is a schematic structural diagram of another circuit module according to some embodiments of the present disclosure.

In the embodiments of the present disclosure, the method may be adapted to control the flow control of different virtual channels. As shown in fig. 6, in one embodiment, the circuit module 200 may be implemented as a switching unit 400.

For example, as shown in fig. 6, the switching unit 400 of 4*4 is taken as an example, that is, the switching unit 400 includes four input ports (i.e., an input port 401a, an input port 401b, an input port 401c, and an input port 401 d) and four output ports (i.e., an output port 402a, an output port 402b, an output port 402c, and an output port 402 d).

For example, each input port may include two virtual channels, and one data survival threshold memory and credit threshold memory may be provided for each virtual channel. As shown in fig. 6, taking the input port 401a as an example, the input port 401a includes a virtual channel VC0 and a virtual channel VC1, the virtual channel VC0 corresponds to the credit threshold memory 405a and the data survival threshold memory 406a, and the virtual channel VC1 corresponds to the credit threshold memory 415a and the data survival threshold memory 416a. For example, fig. 6 also shows credit threshold memory 405b, data surviving threshold memory 406b, credit threshold memory 415b, and data surviving threshold memory 416b corresponding to the two virtual channels included in input port 401b, credit threshold memory 405c, data surviving threshold memory 406c, credit threshold memory 415c, and data surviving threshold memory 416c corresponding to the two virtual channels included in input port 401c, and credit threshold memory 405d, data surviving threshold memory 406d, credit threshold memory 415d, and data surviving threshold memory 416d corresponding to the two virtual channels included in input port 401 d. A data survival counter, a first output sub-module, a credit counter, and a second output sub-module (not shown) are also provided for each virtual channel.

For example, in some embodiments, as shown in FIG. 6, four input ports 401 a-401 d correspond to the same upstream module 410, i.e., receiving data sent by the upstream module 410 includes. The upstream module 410 may include four output ports (not shown) in one-to-one correspondence with the four input ports 401a to 401d to transmit data packets to the four input ports 401a to 401d, respectively, and two counters are provided for each output port of the upstream module 410, so that 8 counters 404a to 404d and 414a to 414b are provided in the upstream module 410. Counter 404a and counter 414a correspond to two virtual channels of input port 401a, counter 404b and counter 414b correspond to two virtual channels of input port 401b, counter 404c and counter 414c correspond to two virtual channels of input port 401c, and counter 404d and counter 414d correspond to two virtual channels of input port 401 d.

For example, the credit number thresholds corresponding to the four input ports 401a to 401d of the switching unit 400 may be the same, for example, all 4, and the channel credit number thresholds corresponding to the two virtual channels in each input port may be the same, for example, all 2. At this time, as shown in fig. 6, 16 cache entries 403a among 24 cache entries included in the switching unit 400 are equally allocated to 8 virtual channels, i.e., each virtual channel in the switching unit 400 uses 2 cache entries 403a.

For example, after each virtual lane is allocated a cache entry, a corresponding number of credits may be released to the corresponding upstream module 410 of the switch unit 400, e.g., 4 credits may be released per virtual lane. For example, as shown in fig. 6, the counter 404a and the counter 414a respectively correspond to two virtual channels VC0 and VC1 of the input port 401a, taking the counter 404a as an example, the count value of the counter 404a is incremented by 1 every time the virtual channel VC0 releases a credit to the upstream module 410, and the count value of the counter 404a is decremented by 1 every time the upstream module 310 sends a packet to the input port 401a, where the packet corresponds to the virtual channel VC 0.

For example, as shown in fig. 6, the interaction unit 400 may include an arbitration logic module 407.

Each time the switching unit 400 receives a packet, a virtual channel corresponding to the packet is determined according to an input port of the received packet and a destination to which the packet needs to be destined, so that a count value of a data survival counter corresponding to the virtual channel (i.e., a channel data survival number corresponding to the virtual channel) is increased by 1, and each time a packet in the packets corresponding to the virtual channel stored in the plurality of buffer entries is sent out through one output port (any one of output ports 402a to 402 d) of the switching unit 400, the count value of the data survival counter corresponding to the virtual channel is decreased by 1. When the count value of the data survival counter corresponding to the virtual channel reaches the channel data number threshold corresponding to the virtual channel, the first output sub-module corresponding to the virtual channel feeds back to the arbitration logic module 407, that is, the first output sub-module outputs the first sub-control signal corresponding to the virtual channel to the arbitration logic module 407, so that the arbitration logic module 407 stops releasing the credit to the virtual channel, even if the channel credit number corresponding to the virtual channel does not reach the channel credit number threshold, thereby controlling the data bandwidths of different virtual channels.

Every time a credit is released to a virtual channel, the count value of the credit counter corresponding to the virtual channel (i.e. the number of channel credits corresponding to the virtual channel) is added with 1; whenever a data packet is received at an input port including the virtual channel and corresponds to the virtual channel, the count value of the credit counter corresponding to the virtual channel is subtracted by 1. When the channel credit number corresponding to the virtual channel reaches the channel credit number threshold corresponding to the virtual channel, the second output sub-module corresponding to the virtual channel is fed back to the arbitration logic module 407, that is, the second output sub-module outputs the second sub-control signal corresponding to the virtual channel to the arbitration logic module 407, so that the arbitration logic module 307 does not release the credit to the virtual channel.

It should be noted that, in the embodiment of the present disclosure, "releasing credit to an input port" means that credit corresponding to the input port is released to an upstream module corresponding to the input port, and "releasing credit to the input port" also means that a cache entry is allocated to the input port; similarly, "releasing credit to a virtual channel" means releasing credit corresponding to the virtual channel to an upstream module corresponding to an input port including the virtual channel, and also means allocating a cache entry to the virtual channel.

At least one embodiment of the present disclosure also provides a credit control method. Fig. 7A is a schematic flow chart of a credit control method according to at least one embodiment of the present disclosure, and fig. 7B is a schematic flow chart of a credit control method according to at least one embodiment of the present disclosure.

For example, the credit control method may be applied to a circuit module that includes a plurality of input ports and a plurality of cache entries. The circuit module may be a circuit module provided in any of the embodiments of the present disclosure, for example, the circuit module 200 described above.

As shown in fig. 7A and 7B, the credit control method includes the following steps S10 to S11. For each of a plurality of input ports: in step S10, recording the data survival number corresponding to the input port; in step S11, in response to the data survival number reaching the data number threshold corresponding to the input port, releasing the credit to the input port is stopped.

For example, the data survivor number indicates the number of data packets received by the input port currently stored by the plurality of cache entries.

For example, the circuit module further includes a data survival control module including a data survival threshold memory, a data survival counter, and a first output sub-module. The data survival counter is used for recording the data survival number corresponding to the input port, that is, the data survival counter is used for implementing the step S10.

For example, the circuit module further includes a plurality of output ports, and in some embodiments, step S10 includes: the method includes adding a predetermined value to the number of data survivors in response to the input port receiving a packet, and subtracting the predetermined value from the number of data survivors in response to an output port outputting a packet of the packets received by the input port stored in the plurality of cache entries.

For example, in some embodiments, the predetermined value may be 1.

For example, in some embodiments, the circuit module further includes an arbitration logic module. For example, step S11 includes: responding to the data survival quantity corresponding to the input port reaching the data quantity threshold value corresponding to the input port, and outputting a first control signal to the arbitration logic module; the arbitration logic module stops releasing credits to the input port in response to receiving the first control signal.

For example, in some embodiments, in step S11, the data survival threshold memory is configured to store a data quantity threshold corresponding to the input port, and the first output sub-module is configured to output, in response to the data survival quantity corresponding to the input port reaching the data quantity threshold corresponding to the input port, a first control signal corresponding to the input port to the arbitration logic module, where the arbitration logic module is configured to implement the operation of stopping the credit release to the input port in step S11. The arbitration logic module and the data survival control module combine to implement step S11 described above.

For example, in some embodiments, as shown in fig. 7B, the credit control method further includes the following steps S12 to S13. For each of a plurality of input ports: in step S12, the credit number corresponding to the input port is recorded; in step S13, in response to the credit number reaching the credit number threshold corresponding to the input port, releasing the credit to the input port is stopped.

For example, the credit number indicates the number of credits corresponding to the input port currently owned by the circuit module that sent the data packet to the input port.

For example, the circuit module further includes a credit control module including a credit threshold memory, a credit counter, and a second output sub-module. The credit counter is used for recording the number of credits corresponding to the input port, i.e. the credit counter is used for implementing step S12 described above.

For example, in some embodiments, step S12 may include: the credit number is incremented by a predetermined value in response to releasing a credit to the input port, and decremented by the predetermined value in response to the input port receiving a data packet.

For example, in some embodiments, step S13 includes: responding to the credit quantity corresponding to the input port reaching a credit quantity threshold corresponding to the input port, and outputting a second control signal corresponding to the input port to the arbitration logic module; the arbitration logic module stops releasing credits to the input port in response to receiving the second control signal.

For example, the credit threshold memory is configured to store a credit number threshold; the second output sub-module is configured to output a second control signal corresponding to the input port to the arbitration logic module in response to the number of credits corresponding to the input port reaching a threshold number of credits corresponding to the input port, the arbitration logic module further configured to cease releasing credits to the input port in response to receiving the second control signal. The arbitration logic module and the credit control module combine to implement step S13 described above.

In fig. 7B, the steps S10 to S13 are shown in a certain order, but the order does not indicate the execution order of the steps S10 to S13. The execution order of the respective steps S10 to S13 is determined according to actual conditions, and for example, the steps S10 and S12 may be executed simultaneously.

For example, in other embodiments, each input port includes a plurality of virtual channels, where the destinations corresponding to the plurality of virtual channels are different.

For example, for each virtual channel of a plurality of virtual channels included by the input port: the data survival number corresponding to the input port includes a channel data survival number corresponding to the virtual channel, and the data number threshold corresponding to the input port includes a channel data number threshold corresponding to the virtual channel.

For example, the number of surviving channel data corresponding to the virtual channel represents the number of data packets corresponding to the virtual channel received by the input port that are stored by the plurality of cache entries. The channel data number threshold corresponding to the virtual channel represents a maximum value of a number of data packets corresponding to the virtual channel currently stored by the plurality of cache entries and received by the input port.

For example, step S10 includes: the number of surviving channel data corresponding to each virtual channel is recorded. The step S11 includes: for each virtual channel of the plurality of virtual channels: and stopping releasing the credit to the virtual channel in response to the survival number of the channel data corresponding to the virtual channel reaching the threshold value of the channel data corresponding to the virtual channel.

For example, when an input port includes a plurality of virtual channels, a data survival control module corresponding to the input port includes a data survival threshold memory, a data survival counter, and a first output sub-module corresponding to each virtual channel. The functions implemented by the data survival threshold memory, the data survival counter and the first output sub-module corresponding to each virtual channel are referred to above for the relevant description in the embodiment of the circuit module, and are not repeated here.

For example, for each virtual channel of a plurality of virtual channels: the credit number includes a channel credit number corresponding to the virtual channel, and the credit number threshold includes a channel credit number threshold corresponding to the virtual channel. For example, the number of channel credits corresponding to the virtual channel represents the number of credits corresponding to the virtual channel currently owned by the circuit module sending the data packet to the virtual channel, and the threshold value of the number of channel credits corresponding to the virtual channel represents the maximum value of the number of credits corresponding to the virtual channel currently owned by the circuit module sending the data packet to the virtual channel.

For example, step S12 includes: the number of channel credits corresponding to each virtual channel is recorded. The step S13 includes: for each virtual channel of the plurality of virtual channels: and stopping releasing the credit to the virtual channel in response to the channel credit number corresponding to the virtual channel reaching the channel credit number threshold corresponding to the virtual channel.

For example, when the input port includes a plurality of virtual channels, the credit control module corresponding to the input port includes a credit threshold memory, a credit counter, and a second output sub-module corresponding to each virtual channel. The functions implemented by the credit threshold memory, the credit counter and the second output sub-module corresponding to each virtual channel are referred to above for the relevant description in the embodiment of the circuit module, and are not repeated here.

For example, in some embodiments, multiple cache entries are shared by multiple input ports. When each input port includes a plurality of virtual channels, the plurality of cache entries are shared by all virtual channels included by the plurality of input ports.

For example, in some embodiments, the credit control method further comprises: and releasing the credit to the plurality of input ports in response to at least one cache entry of the plurality of cache entries not storing information.

For example, the arbitration logic is configured to enable credit release to a plurality of input ports.

For example, in some embodiments, releasing credits to the plurality of input ports includes: determining a selected input port in the plurality of input ports according to the port sequence corresponding to the plurality of input ports; and releasing credit to the selected input port in response to the data survival quantity corresponding to the selected input port not reaching the data quantity threshold corresponding to the selected input port.

For example, in some embodiments, releasing credits to the plurality of input ports includes: determining a selected input port in the plurality of input ports according to the port sequence corresponding to the plurality of input ports; and releasing the credit to the selected input port in response to the credit number corresponding to the selected input port not reaching the credit number threshold corresponding to the selected input port.

For example, the technical effects achieved by the credit control method are the same as those achieved by the circuit module, and will not be described here again.

At least one embodiment of the present disclosure also provides an integrated circuit. Fig. 8 is a schematic block diagram of an integrated circuit provided in accordance with at least one embodiment of the present disclosure.

As shown in fig. 8, the integrated circuit 800 includes a circuit module 801, where the circuit module 801 may be a circuit module provided in any embodiment of the disclosure, for example, the circuit module 200 described above. The integrated circuit 800 may also include various other elements to implement the functions it is required to implement, and embodiments of the present disclosure are not limited to the specific structure of the integrated circuit 800.

The integrated circuit 800 may achieve the technical effects achieved by the circuit module 200 described above.

It should be noted that, the integrated circuit in the present disclosure may refer to a part of a large circuit design or a part of a module, that is, the integrated circuit in the present disclosure may be a complete integrated circuit, or may be a part of a complete integrated circuit, which is not limited in this disclosure.

At least one embodiment of the present disclosure also provides an electronic device including the integrated circuit according to any one of the embodiments of the present disclosure.

For example, the electronic device may be a product or a component such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

At least one embodiment of the present disclosure further provides a credit control device, and fig. 9 is a schematic block diagram of a credit control device provided by at least one embodiment of the present disclosure.

For example, as shown in fig. 9, the credit control device includes a processor 901, a communication interface 902, a memory 903, and a communication bus 904. The processor 901, the communication interface 902, and the memory 903 communicate with each other via the communication bus 904, and the components of the processor 901, the communication interface 902, and the memory 903 may communicate with each other via a network connection. The present disclosure is not limited herein with respect to the type and functionality of the network.

For example, the memory 903 is used to store computer executable instructions non-transitory. The processor 901 is configured to execute computer-executable instructions that when executed by the processor 901 implement a credit control method according to any one of the embodiments described above. For specific implementation of the steps of the credit control method and related explanation, reference may be made to the above embodiments of the credit control method, which are not described herein.

For example, the implementation manner of the credit control method by the processor 901 executing the program stored in the memory 903 is the same as the implementation manner mentioned in the foregoing embodiment of the credit control method, and will not be repeated here.

For example, the communication bus 904 may be a peripheral component interconnect standard (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be classified as an address bus, a data bus, a control bus, or the like. For ease of illustration, the figures are shown with only one bold line, but not with only one bus or one type of bus.

For example, the communication interface 902 is used to enable communication between the credit control means and other devices.

For example, the processor 901 and the memory 903 may be provided at the server side (or cloud).

For example, the processor 901 may control other components in the credit control device to perform desired functions. Processor 901 may be a Central Processing Unit (CPU), network Processor (NP), etc., as well as a Digital Signal Processor (DSP), application Specific Integrated Circuit (ASIC), field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The Central Processing Unit (CPU) can be an X86 or ARM architecture, etc.

For example, the memory 903 may comprise any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, random Access Memory (RAM) and/or cache memory (cache) and the like. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer-executable instructions may be stored on the computer-readable storage medium that may be executed by the processor 901 to implement various functions of the credit control device. Various applications and various data, etc. may also be stored in the storage medium.

For example, a detailed description of the procedure of the credit control apparatus performing the credit control method may refer to the relevant description in the embodiment of the credit control method, and the repetition is omitted.

Fig. 10 is a schematic diagram of a non-transitory computer storage medium according to at least one embodiment of the present disclosure. For example, the non-transitory computer storage medium may be a non-transitory computer readable storage medium.

For example, as shown in FIG. 10, one or more computer-executable instructions 1001 may be stored non-transitory on a non-transitory computer storage medium 1000. For example, the computer-executable instructions 1001, when executed by a computer, may cause the computer to perform one or more steps of a credit control method according to any of the embodiments described above.

For example, non-transitory computer storage medium 1000 is a non-transitory computer readable storage medium.

For example, the non-transitory computer storage medium 1000 may be applied to the credit control device and/or the electronic device described above. For example, non-transitory computer storage medium 1000 may include memory 903 in a credit control device.

For example, the description of the non-transitory computer storage medium 1000 may refer to the description of the memory 903 in the embodiment of the credit control device, and the repetition is omitted.

For the purposes of this disclosure, the following points are also noted:

(1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

The foregoing is merely a specific embodiment of the disclosure, but the scope of the disclosure is not limited thereto and should be determined by the scope of the claims.

Claims

1. A circuit module, comprising: a plurality of input ports, a plurality of cache entries, a data survival control module, and an arbitration logic module,

Wherein the plurality of input ports includes an input port corresponding to the data survival control module,

The data survival control module is configured to output a first control signal to the arbitration logic module in response to the data survival number corresponding to the input port reaching a data number threshold corresponding to the input port, wherein the data survival number represents the number of data packets currently stored by the plurality of cache entries and received by the input port;

The arbitration logic module is configured to cease releasing credits to the input port in response to receiving the first control signal.

2. The circuit module of claim 1, further comprising a plurality of output ports,

Wherein the data survival control module comprises a data survival threshold memory, a data survival counter and a first output sub-module,

The data survival counter is configured to add a predetermined value to the number of data survival in response to the input port receiving a data packet, and subtract the predetermined value from the number of data survival in response to one of the data packets stored by the plurality of cache entries received by the input port being output through an output port;

The data survival threshold memory is configured to store the data quantity threshold;

The first output sub-module is configured to output the first control signal to the arbitration logic module in response to the number of data survivors reaching the number of data threshold.

3. The circuit module of claim 1, further comprising: the credit control module is configured to control the credit card,

The credit control module is configured to output a second control signal to the arbitration logic module in response to the credit number corresponding to the input port reaching a credit number threshold corresponding to the input port, wherein the credit number represents the number of credits corresponding to the input port currently owned by a circuit module that sends a data packet to the input port;

the arbitration logic module is further configured to cease releasing credits to the input port in response to receiving the second control signal.

4. The circuit module of claim 3, wherein the credit control module comprises a credit threshold memory, a credit counter, and a second output sub-module,

Wherein the credit counter is configured to add a predetermined value to the number of credits in response to releasing a credit to the input port, and subtract the predetermined value from the number of credits in response to the input port receiving a data packet;

The credit threshold memory is configured to store the credit number threshold;

the second output sub-module is configured to output the second control signal to the arbitration logic module in response to the credit number reaching the credit number threshold.

5. The circuit module of any of claims 1-4, wherein the plurality of cache entries are shared by the plurality of input ports.

6. The circuit module of claim 5, wherein the arbitration logic module is further configured to release credits to the plurality of input ports in response to at least one of the plurality of cache entries not storing information.

7. The circuit module of claim 1, further comprising a plurality of output ports,

Wherein the input port comprises a plurality of virtual channels, the destinations corresponding to the virtual channels are different,

For each virtual channel of the plurality of virtual channels:

The data survival control module comprises a data survival threshold memory corresponding to the virtual channel, a data survival counter and a first output sub-module,

The number of data survivors including a number of lane data survivors corresponding to the virtual lane, the number of data thresholds including a number of lane data thresholds corresponding to the virtual lane, the first control signal including a first sub-control signal corresponding to the virtual lane, the number of lane data survivors representing a number of data packets stored by the plurality of cache entries corresponding to the virtual lane received by the input port,

The data survival counter is configured to respond to the input port receiving a data packet, the data packet corresponds to the virtual channel, add a preset value to the channel data survival number, respond to the output of one of the data packets stored in the plurality of cache entries and corresponding to the virtual channel through an output port, and subtract the preset value from the channel data survival number;

The data survival threshold memory is configured to store the channel data quantity threshold;

the first output sub-module is configured to output the first sub-control signal to the arbitration logic module in response to the number of lane data survivors reaching the number of lane data threshold,

The arbitration logic module is configured to cease releasing credits to the virtual channel of the input port in response to receiving the first sub-control signal.

8. The circuit module of claim 3, wherein the input port comprises a plurality of virtual channels, the plurality of virtual channels having respective destinations that are different from one another,

For each virtual channel of the plurality of virtual channels:

the credit control module includes a credit threshold memory corresponding to the virtual channel, a credit counter and a second output sub-module,

The credit number comprising a channel credit number corresponding to the virtual channel, the credit number threshold comprising a channel credit number threshold corresponding to the virtual channel, the second control signal comprising a second sub-control signal corresponding to the virtual channel, the channel credit number representing a number of credits corresponding to the virtual channel currently owned by a circuit module sending data packets to the input port,

The credit counter is configured to add a predetermined value to the number of channel credits in response to releasing a credit to the virtual channel, subtract the predetermined value from the number of channel credits in response to the input port receiving a data packet corresponding to the virtual channel;

the credit threshold memory is configured to store the channel credit number threshold;

the second output sub-module is configured to output the second sub-control signal to the arbitration logic module in response to the channel credit number reaching the channel credit number threshold,

The arbitration logic is configured to cease releasing credits to the virtual channel in response to receiving the second sub-control signal.

9. The circuit module of any of claims 2,4 and 7-8, wherein the predetermined value is 1.

10. A credit control method applied to a circuit module, wherein the circuit module comprises: a plurality of input ports and a plurality of cache entries,

The credit control method comprises the following steps:

For each of the plurality of input ports:

recording the survival number of the data corresponding to the input port;

and stopping releasing the credit to the input port in response to the data survival number reaching the data number threshold corresponding to the input port,

Wherein the number of data survivors represents a number of data packets currently stored by the plurality of cache entries that are received by the input port.

11. The credit control method of claim 10, wherein the circuit module further includes a plurality of output ports,

Recording the data survival quantity corresponding to the input port, comprising:

in response to the input port receiving a data packet, adding a predetermined value to the number of data survivors,

And subtracting the predetermined value from the data survival number in response to one of the data packets received by the input ports stored in the plurality of cache entries being output through one output port.

12. The credit control method of claim 10, wherein the input port includes a plurality of virtual channels, the destinations corresponding to the plurality of virtual channels being different from each other,

For each virtual channel of the plurality of virtual channels: the number of data survivors including a number of lane data survivors corresponding to the virtual lanes, the number of data thresholds including a number of lane data thresholds corresponding to the virtual lanes, the number of lane data survivors representing a number of data packets corresponding to the virtual lanes received by the input port stored by the plurality of cache entries,

Recording the data survival quantity corresponding to the input port, comprising: recording the survival number of channel data corresponding to each virtual channel;

And stopping releasing the credit to the input port in response to the data survival number reaching the data number threshold corresponding to the input port, including: for each virtual channel of the plurality of virtual channels: and stopping releasing the credit to the virtual channel in response to the survival number of the channel data corresponding to the virtual channel reaching the threshold value of the channel data corresponding to the virtual channel.

13. The credit control method of claim 10, further comprising:

The number of credits corresponding to the input port is recorded,

In response to the credit number reaching a credit number threshold corresponding to the input port, ceasing to release credits to the input port,

Wherein the credit number represents the number of credits corresponding to the input port currently owned by the circuit module sending the data packet to the input port.

14. The credit control method of claim 13, wherein recording the number of credits corresponding to the input port includes:

in response to releasing a credit to the input port, adding a predetermined value to the number of credits,

In response to the input port receiving a data packet, subtracting the predetermined value from the credit number.

15. The credit control method of claim 13, wherein the input port includes a plurality of virtual channels, the destinations corresponding to the plurality of virtual channels being different from each other,

For each virtual channel of the plurality of virtual channels: the credit number comprising a channel credit number corresponding to the virtual channel, the credit number threshold comprising a channel credit number threshold corresponding to the virtual channel, the channel credit number representing a number of credits corresponding to the virtual channel currently owned by a circuit module sending data packets to the input port,

Recording the credit number corresponding to the input port, comprising: recording the channel credit number corresponding to each virtual channel;

and stopping releasing the credit to the input port in response to the credit number reaching a credit number threshold corresponding to the input port, including: for each virtual channel of the plurality of virtual channels: and stopping releasing the credit to the virtual channel in response to the channel credit number corresponding to the virtual channel reaching a channel credit number threshold corresponding to the virtual channel.

16. The credit control method of any of claims 10-11 and 13-14, wherein the circuit module further comprises: the arbitration logic module is configured to determine,

And stopping releasing the credit to the input port in response to the data survival number reaching the data number threshold corresponding to the input port, including:

outputting a first control signal to the arbitration logic module in response to the data survival number corresponding to the input port reaching a data number threshold corresponding to the input port;

The arbitration logic module stops releasing credits to the input port in response to receiving the first control signal.

17. The credit control method of any of claims 10-15, wherein the plurality of cache entries are shared by the plurality of input ports,

The credit control method further comprises the following steps: and releasing credit to the plurality of input ports in response to at least one cache entry of the plurality of cache entries not storing information.

18. The credit control method of claim 17, wherein releasing credits to the plurality of input ports comprises:

determining a selected input port in the plurality of input ports according to the port sequence corresponding to the plurality of input ports;

And releasing credit to the selected input port in response to the data survival quantity corresponding to the selected input port not reaching the data quantity threshold corresponding to the selected input port.

19. An integrated circuit comprising the circuit module according to any one of claims 1-9.

20. A non-transitory computer storage medium storing computer executable instructions which, when executed by a computer, cause the computer to perform the credit control method of any of claims 10-18.