CN101000926A - Ferroelectric field effect transistor storage device structure and preparation method - Google Patents

Abstract

The invention relates to a structure of ferroelectric memory and its preparation method, which specifically relates to a ferroelectric memory preparation technology of MFPIS structure. This invention includes: an upper electrode, a source region and a drain region. There are a PZT ferroelectric thin film, a multicrystal Si, an insulating layer, a well and a Si substrate, and the upper electrode lies on the PZT ferroelectric thin film. There are several beneficial effects of the invention, to overcome the general ferroelectric memory effect component contact surface difference, the working voltage high shortcoming, and have the good memory capability. This invention also provided the preparation method of this ferroelectric field effect transistor, and this preparation craft is simple, and compatible with the semiconductor manufacture craft.

Description

Ferroelectric field effect transistor storage device structure and preparation method

Technical field

The invention belongs to field of microelectronic devices, be specifically related to a kind of ferroelectric field effect transistor storage device technology of preparing of MFPIS structure.

Background technology

Ferro-electric field effect transistor (Ferroelectric Field Effect Transistors, FFET) be as the gate dielectric layer in the transistor with ferroelectric thin film, by the modulation of grid polarized state realization, read a kind of ferroelectric memory of stored information according to the relative size of leakage-source electric current to leakage-source electric current.Reading of ferro-electric field effect transistor do not need to make the grid polarization reversal, is that a kind of non-destructive is read the memory device of (NDRO).Compare with other non-volatility memorizer, it is low that FFET has operating voltage, the storage density height, and the little and high advantage of read-write number of times of power consumption has great application prospect in technical field of information storage.

When ferroelectric thin film directly was deposited on the Si substrate, high leakage current was a FAQs.It is owing to exist serious interfacial reaction and counterdiffusion mutually between ferroelectric thin film and silicon substrate, thereby makes and be difficult to form the performance that good interfacial state has influenced the FFET device between ferroelectric thin film and the silicon substrate.In order to address this problem, people such as Hirai (see Hirai T, Teramoto K, Nishi T, et al.Formation of Metal/Ferroelectric/Insulator/Semiconductorstructure with a CeO ₂Buffer layer.Jpn.J.Appl.Phys., 1994,33:5219-5222) between ferroelectric thin film and silicon substrate, insert one deck CeO ₂Make insulating barrier, formed the ferro-electric field effect transistor of Metal/Ferroelectric/Insulator/Si (MFIS) structure.CeO ₂Be deposited on the Si substrate, can form SiO ₂, and CeO ₂Can not be too thin, having approached very much to increase leakage current, influences the memory property of device, blocked up and can cause operating voltage too high.

People such as SiTokumitsu (see Tokumitsu E, Fujii G, Ishiwara H.Nonvolatileferroelectric-gate field-effect transistors usingSrBi ₂Ta ₂O ₉/ Pt/SrTa ₂O ₆/ SiON/Si structures.Appl.Phys.Lett., 1999,75:575-577) on the basis of MFIS, add one deck hearth electrode Pt again, formed the ferro-electric field effect transistor of Metal/Ferroelectric/Metal/Insulator/Si (MFMIS) structure, by regulating the area ratio of electric capacity up and down, can reduce operating voltage, but processing step is more.

It is simple how to seek a kind of technology, and can overcome interfacial state again and cross high working voltage is the problem that this device faces, and below enumerates some solutions that existing patent proposes.

1 United States Patent (USP): Structure of high dielectric constantmetal/dielectric/semiconductor capacitor for use as the storge capacitor inmemory devices

The patent No.: US5338951

Authorize day: 1994.8.16

This patent utilization ZrO ₂, LaO ₂And TiO ₂As transition zone, formed the ferro-electric field effect transistor of MFIS structure, but the transition zone of oxide meeting and Si formation SiO in high annealing ₂, can cause too high operating voltage.

2 United States Patent (USP)s: Non-volatile semiconductor memory of a metal ferroelectricfield effect transistor

The patent No.: US5768185

Authorize day: 1998.6.16

This patent is used the ferro-electric field effect transistor of MFMIS structure, will add that between hearth electrode and transition zone Ti, Ta, TiN add strongly adherent, and transition zone is SiO ₂, MgO and CaF ₂, this structural manufacturing process complexity.

3 United States Patent (USP)s: Fabrication method and structure for ferroelectricnonvolatile memory field effect transistor

The patent No.: US6815219

Authorize day: 2004.11.9

This patent utilization MgO/SiO ₂The common transition zone of forming, the ferro-electric field effect transistor of formation MFIS structure is because MgO/SiO ₂The dividing potential drop effect of layer also can cause too high operating voltage.

Summary of the invention

The purpose of this invention is to provide a kind of ferroelectric field effect transistor storage device structure, this device can overcome the high shortcoming of prior art operating voltage; Another object of the present invention provides this ferro-electric field effect transistor structural approach of preparation.

The technical scheme that the present invention solve the technical problem employing is:

Ferroelectric field effect transistor storage device structure comprises top electrode, source region and drain region, and each layer is followed successively by from top to bottom: PZT ferroelectric thin film, polysilicon, insulating barrier, trap and Si substrate, top electrode is positioned on the PZT ferroelectric thin film.

Further, the source region is n ⁺Source region, drain region are n ⁺Drain region, trap are the p trap.Perhaps the source region is p ⁺Source region, drain region are p ⁺Drain region, trap are the n trap.

Described insulating layer material is SiO ₂

The present invention also provides a kind of method for preparing aforementioned ferroelectric field effect transistor storage device structure, may further comprise the steps:

(1) on the Si substrate, forms the p trap;

(2) the thin SiO of surface heat oxidation one deck ₂As insulating barrier, thickness 5nm-30nm;

(3) deposit polysilicon;

(4) inject phosphonium ion and form n ⁺Source region and n ⁺The drain region, and to polysilicon doping;

(5) to substrate base surface deposition PZT ferroelectric thin film;

(6) etch PZT ferroelectric thin film figure;

(7) preparation top electrode, and adopt stripping means to obtain the top electrode figure;

(8) the PZT ferroelectric thin film is carried out short annealing;

(9) preparation SiO ₂Insulating barrier;

(10) etch away the SiO in source region, drain region and grid region ₂, obtain source, leakage and gate electrode window;

(11) sputter Al metal level anti-carves the Al metal level and obtains source, leakage and grid.

Perhaps, form the n trap in the step (1), step (4) injecting nitrogen ion forms p ⁺Source region and p ⁺The drain region.

The invention has the beneficial effects as follows that it is poor to have overcome general ferroelectric storage effect device interfaces, the shortcoming that operating voltage is high, and have good memory property; The present invention also provides preparation this ferro-electric field effect transistor method, and this method technology is simple, and compatible mutually with semiconductor technology.

The present invention is further illustrated below in conjunction with the drawings and specific embodiments.

Description of drawings

Fig. 1 is a ferro-electric field effect transistor device cell schematic cross-section of the present invention.

Fig. 2 is ferro-electric field effect transistor device drain-source current-grid voltage of the present invention (Ids-Vgs) curve chart.

Embodiment

Referring to Fig. 1.

Ferro-electric field effect transistor of the present invention is made up of substrate, source region, drain region and the grid region between source region and drain region, and substrate is the n type monocrystalline silicon piece 101 in (100) crystal orientation.After injecting formation p trap 102, surface heat oxidation one deck SiO ₂103 as insulating barrier.

The present invention is also included within the transistor that n type monocrystalline silicon piece directly forms the p raceway groove.

Ferroelectric field effect transistor storage device structure comprises Pt top electrode 108, n ⁺Source region 104 and n ⁺Drain region 105, each layer is followed successively by from top to bottom: PZT ferroelectric thin film 107, polysilicon 106, SiO ₂ Insulating barrier 103, p trap 102 and Si substrate 101, top electrode 108 is positioned on the PZT ferroelectric thin film 107.

The preparation method of above-mentioned ferro-electric field effect transistor may further comprise the steps successively:

Clean Si substrate 101;

On the Si substrate, inject and form p trap 102;

Surface heat oxidation one deck approaches SiO ₂103 as insulating barrier, thickness 5nm-30nm;

LPCVD deposit poly-Si 106;

Adopt self-registered technology to inject phosphonium ion and form n ⁺Source region 104 and n ⁺Drain region 105, and to poly-Si 106 doping;

Adopt radio frequency magnetron sputtering method to carrying out n ⁺The substrate base surface deposition PbZr that ion injects _0.52Ti _0.48O ₃(PZT) 107 ferroelectric thin films;

Etch PZT 107 ferroelectric thin film figures;

Adopt dc magnetron sputtering method to prepare Pt 108 top electrodes, and adopt stripping means to obtain Pt 108 top electrode figures;

PZT 107 ferroelectric thin films are carried out short annealing;

LPCVD prepares SiO ₂109 insulating barriers;

Etch away the SiO in source region, drain region and grid region ₂109, obtain source, leakage and gate electrode window;

Direct current sputtering Al 110 metal levels anti-carve Al 110 metal levels and obtain source, leakage and grid.

Fig. 2 is ferro-electric field effect transistor device drain-source current-grid voltage of the present invention (Ids-Vgs) curve, and abscissa is Vgs, and ordinate is Ids.Test shows, gate voltage-5V and+5V between, the memory window of device is 2.6V, satisfies the practical application of device fully.

The preparation method who directly forms the transistorized preparation method of p raceway groove and previous embodiment at n type monocrystalline silicon piece is similar, repeats no more.

Claims (6)

1, ferroelectric field effect transistor storage device structure, comprise top electrode (108), source region (104) and drain region (105), it is characterized in that, each layer is followed successively by from top to bottom: PZT ferroelectric thin film (107), polysilicon (106), insulating barrier (103), trap (102) and Si substrate (101), top electrode (108) is positioned on the PZT ferroelectric thin film (107).

2, ferroelectric field effect transistor storage device structure as claimed in claim 1 is characterized in that, source region (104) are n ⁺The source region, drain region (105) are n ⁺The drain region, trap (102) is the p trap.

3, ferroelectric field effect transistor storage device structure as claimed in claim 1 is characterized in that, source region (104) are p ⁺The source region, drain region (105) are p ⁺The drain region, trap (102) is the n trap.

4, ferroelectric field effect transistor storage device structure as claimed in claim 1 is characterized in that, described insulating barrier (103) material is SiO ₂

5, prepare the method for the described ferroelectric field effect transistor storage device structure of claim 1, may further comprise the steps:

(1) on the Si substrate, injects formation p trap (102);

(2) the thin SiO of surface heat oxidation one deck ₂(103) as insulating barrier, thickness 5nm-30nm;

(3) deposit polysilicon (106);

(4) inject phosphonium ion and form n ⁺Source region (104) and n ⁺Drain region (105), and polysilicon (106) mixed;

(5) to carrying out n ⁺The substrate base surface deposition PZT ferroelectric thin film (107) that ion injects;

(6) etch PZT (107) ferroelectric thin film figure;

(7) preparation top electrode (108), and adopt stripping means to obtain top electrode (108) figure;

(8) PZT ferroelectric thin film (107) is carried out short annealing;

(9) preparation SiO ₂Insulating barrier (109);

(10) etch away the SiO in source region, drain region and grid region ₂(109), obtain source, leakage and gate electrode window;

(11) sputter Al (110) metal level anti-carves Al (110) metal level and obtains source, leakage and grid.

6, prepare the method for the described ferroelectric field effect transistor storage device structure of claim 1, may further comprise the steps:

(1) on the Si substrate, injects formation n trap (102);

(2) the thin SiO of surface heat oxidation one deck ₂(103) as insulating barrier, thickness 5nm-30nm;

(3) deposit polysilicon (106);

(4) injecting nitrogen ion forms p ⁺Source region (104) and p ⁺Drain region (105), and polysilicon (106) mixed;

(5) to carrying out p ⁺The substrate base surface deposition PZT ferroelectric thin film (107) that ion injects;

(6) etch PZT (107) ferroelectric thin film figure;

(7) preparation top electrode (108), and adopt stripping means to obtain top electrode (108) figure;

(8) PZT ferroelectric thin film (107) is carried out short annealing;

(9) preparation SiO ₂Insulating barrier (109);

(10) etch away the SiO in source region, drain region and grid region ₂(109), obtain source, leakage and gate electrode window;

(11) sputter Al (110) metal level anti-carves Al (110) metal level and obtains source, leakage and grid.

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