CN100590830C - Method and structure for impriving the measurment accuracy of LDD doping layer square resistance - Google Patents
Method and structure for impriving the measurment accuracy of LDD doping layer square resistance Download PDFInfo
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- CN100590830C CN100590830C CN200710044807A CN200710044807A CN100590830C CN 100590830 C CN100590830 C CN 100590830C CN 200710044807 A CN200710044807 A CN 200710044807A CN 200710044807 A CN200710044807 A CN 200710044807A CN 100590830 C CN100590830 C CN 100590830C
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Abstract
A method for improving measurement accuracy of the square resistance of a lightly doped drain (LDD) doped layer comprises the following steps: providing a semiconductor substrate; forming a first doped layer with first doping ions and a second doped layer with second doping ions in the semiconductor substrate, wherein the first doped layer is positioned below the second doped layer and contacts with the second doped layer; annealing the semiconductor substrate with the first doped layer and the second doped layer; and measuring the square resistance of the second doped layer. The invention also provides a structure for improving measurement accuracy of the square resistance of the LDD doped layer. The method can reduce the influence of the substrate on measurement results.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of raising lightly doped drain (Light Doped Drain, LDD) method and the structure of doped layer square resistance (Sheet Resistivity) certainty of measurement.
Background technology
Along with CMOS (Complementary Metal Oxide Semiconductor) transistor (CMOS) continuous advancement in technology, integrated level is more and more higher, and the live width of grid is more and more littler, and the length of the conducting channel below the grid structure also constantly reduces.
, promptly before the heavy doping of carrying out source electrode and drain electrode, carry out shallow junction with the bigger ion of molecular weight earlier and inject because the LDD injection technology is introduced in the generation of leakage current between the source electrode that reduces to cause of conducting channel length and the drain electrode for suppressing.
In the LDD technology, need the energy of injection low, junction depth is more shallow, and the square resistance after the injection is as much as possible little; Number of patent application be US7105427 U.S. Patent Publication the method injected of a kind of shallow junction, described by high-energy ion bombardment in its disclosed patent document at semiconductor substrate surface, produce more hole at semiconductor substrate surface; Then carrying out first dopant ion injects; Carry out annealing process then; Described first dopant ion is a boron, and the hole of described semiconductor substrate surface can stop that in injection first dopant ion to be injected dark.
The technologist of industry is when how research and development can form the LDD doped layer of shallow junction, and the problem of the testing electrical property of also having in the face of how the LDD doped layer of shallow junction be carried out is for example to the measurement of doped layer square resistance.
In existing a kind of technology, adopt the square resistance of four-point probe measurment LDD doped layer.When measuring, at first go up and carry out LDD technology at nude film (Bare Wafer), form the LDD doped layer of shallow junction, contact described LDD doped layer with probe then, carry out square resistance and measure.
Yet because the junction depth of the doped layer of LDD is more shallow, for example in 65nm technology, the junction depth of LDD can reach 30nm, even littler, when using probe operation, probe is easy to prick wears this LDD doped layer, as shown in Figure 1, because probe 104 has touched the Semiconductor substrate 100 of LDD doped layer below 102, can cause measurement result inaccurate, repeatability is relatively poor.
Summary of the invention
The invention provides a kind of method and structure of the LDD of raising doped layer square resistance certainty of measurement, the present invention can reduce the influence of Semiconductor substrate to measurement result.
A kind of method that improves the certainty of measurement of LDD doped layer square resistance provided by the invention comprises:
Semiconductor substrate is provided;
In described Semiconductor substrate, form first doped layer with first dopant ion and second doped layer with second dopant ion; Described first doped layer is positioned at described second doped layer below, and contacts with described second doped layer;
Semiconductor substrate with first doped layer and second doped layer is carried out annealing process;
After the annealing, measure the square resistance of described second doped layer.
Optionally, the molecular weight of described second dopant ion is greater than the molecular weight of described first dopant ion.
Optionally, the step of formation first doped layer and second doped layer is as follows in described Semiconductor substrate:
Described Semiconductor substrate is carried out surperficial pre-amorphous injection;
The Semiconductor substrate of the executed pre-amorphous injection in surface is carried out first dopant ion inject, form first doped layer;
Semiconductor substrate with described first doped layer is carried out carbon or fluorine injection;
After finishing the injection of carbon or fluorine, described Semiconductor substrate is carried out second dopant ion inject, form second doped layer;
Wherein, the degree of depth of described first dopant ion injection is greater than the degree of depth of described first dopant ion injection.
Optionally, the step of formation first doped layer and second doped layer is as follows in described Semiconductor substrate:
Described Semiconductor substrate is carried out surperficial pre-amorphous injection;
The Semiconductor substrate of the executed pre-amorphous injection in surface is carried out carbon or fluorine injection;
After finishing the injection of carbon or fluorine, described Semiconductor substrate is carried out first dopant ion inject, form first doped layer;
The Semiconductor substrate that forms first doped layer is carried out second dopant ion inject, form second doped layer;
Wherein, the degree of depth of described first dopant ion injection is greater than the degree of depth of described first dopant ion injection.
Optionally, the step of formation first doped layer and second doped layer is as follows in described Semiconductor substrate:
Described Semiconductor substrate is carried out first dopant ion inject, form first doped layer;
The Semiconductor substrate that is formed with first doped layer is carried out surperficial pre-amorphous injection;
Semiconductor substrate after the surperficial pre-amorphous injection is carried out carbon or fluorine injects to carrying out;
After finishing the injection of carbon or fluorine, described Semiconductor substrate is carried out second dopant ion inject, form second doped layer;
Wherein, the degree of depth of described first dopant ion injection is greater than the degree of depth of described first dopant ion injection.
Optionally, the step of formation first doped layer and second doped layer is as follows in described Semiconductor substrate:
Described Semiconductor substrate is carried out surperficial pre-amorphous injection;
The Semiconductor substrate of the executed pre-amorphous injection in surface is carried out carbon or fluorine injection;
After finishing the injection of carbon or fluorine, described Semiconductor substrate is carried out second dopant ion inject, form second doped layer;
Semiconductor substrate with second doped layer is carried out first dopant ion inject, form first doped layer;
Wherein, the degree of depth of described first dopant ion injection is greater than the degree of depth of described first dopant ion injection.
Optionally, described second doped layer is the PLDD doped layer.
Optionally, described first dopant ion is an indium, and second dopant ion is a boron.
Optionally, the energy that injects of described first dopant ion is 30 to 200KeV.
Optionally, the dosage of described first dopant ion injection is 5 * 10
12To 5 * 10
13Atom/cm
2
Optionally, the impurity of the decrystallized ion injection in described surface is a kind of of Ge, Si, Sb.
Optionally, the described spike annealing that is annealed into.
Optionally, the method for described measurement is a four probe method.
Optionally, described second doped layer is the NLDD doped layer.
Optionally, described first dopant ion is an arsenic, and second dopant ion is a phosphorus.
The present invention also provides a kind of structure of certainty of measurement of the LDD of raising doped layer square resistance, comprising:
Semiconductor substrate;
First doped layer in the described Semiconductor substrate and second doped layer with second dopant ion with second dopant ion; Described first doped layer is positioned at described second doped layer below, and contacts with described second doped layer.
Optionally, the molecular weight of described second dopant ion is greater than the molecular weight of described first dopant ion.
Optionally, described first dopant ion is an indium, and second dopant ion is a boron.
Optionally, described first dopant ion is an arsenic, and second dopant ion is a phosphorus.
Compared with prior art, the present invention has the following advantages:
When measurement has the square resistance of first doped layer (being the LDD doped layer) of first dopant ion, below second doped layer, form first doped layer, first doped layer that forms be positioned at described second doped layer below, and contact with described second doped layer, when adopting probe method to measure the square resistance of second doped layer, if probe can enter first doped layer after pricking and wearing described second doped layer, this first doped layer can not cause bigger influence to measurement result; Promptly with respect to silicon substrate, described first doped layer is less to the influence of measurement result, overcome owing to probe passes and directly contacted the defective that causes measuring result error bigger behind second doped layer with silicon substrate, the square resistance of feasible second doped layer of measuring is comparatively accurate, improves the precision of measuring;
In addition, this first doped layer can electrically not impacting described second doped layer;
By forming first doped layer, also make when measuring the square resistance of second doped layer, can adopt the probe measurement method, four probe method for example, this method is simple to operate, and can carry out at the diverse location of Semiconductor substrate, and can be according to the measurement result drawing isoline, the square resistance of comparatively comprehensive reaction semiconductor substrate diverse location is to assess the consistency of second doping process at the Semiconductor substrate diverse location.
Description of drawings
Probe was pricked the schematic diagram of wearing doped layer when Fig. 1 measured LDD doped layer square resistance for existing a kind of sonde method;
Fig. 2 to Fig. 4 for the relevant structural representation of first embodiment of the method for raising of the present invention LDD doped layer square resistance certainty of measurement;
Probe entered into the schematic diagram of first doped layer when Fig. 5 method of the present invention was measured LDD doped layer square resistance;
Fig. 6 for the relevant structural representation of second embodiment of the method for raising of the present invention LDD doped layer square resistance certainty of measurement;
Fig. 7 for the relevant structural representation of the 3rd embodiment of the method for raising of the present invention LDD doped layer square resistance certainty of measurement;
Fig. 8 for the relevant structural representation of the 4th embodiment of the method for raising of the present invention LDD doped layer square resistance certainty of measurement.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Along with semiconductor fabrication process develops to 65nm even littler technology node, the junction depth of LDD is more and more shallow in the CMOS manufacturing process, and this brings for measurement of LDD doped layer square resistance and separates bigger difficulty; When with probe the LDD doped layer being carried out the square resistance measurement, probe is easy to prick wears described doped layer, causes the result who measures influenced by Semiconductor substrate, and measurement result is inaccurate, poor repeatability.
The invention provides a kind of method of the LDD of raising doped layer square resistance certainty of measurement, promptly below the LDD doped layer, form first doped layer, dopant ion and the dopant ion in the LDD doped layer in this first doped layer are same kind, for example be all N type or P type, but molecular weight is greater than the molecular weight of the dopant ion in the LDD doped layer; After forming described first doped layer, when the square resistance of LDD doped layer being measured with probe, probe can directly not contact with Semiconductor substrate after pricking and wearing the LDD doped layer, but contact with first doped layer, this first doped layer is less to the influence of measurement result, promptly reduces or has eliminated the influence of Semiconductor substrate to measurement result.
Below in conjunction with embodiment the method for raising LDD doped layer square resistance certainty of measurement of the present invention is described in detail.
Embodiment one
Described first dopant ion is an indium, and second dopant ion is a boron, and second doped layer is the PLDD doped layer.
As shown in Figure 2, provide Semiconductor substrate 10, described Semiconductor substrate 10 can be monocrystalline silicon or polysilicon.
Clean the surface of described Semiconductor substrate 10, with the impurity particle of removing described Semiconductor substrate 10 surfaces, the pollutant of organic or inorganic, and natural oxidizing layer.
Optionally; can generate a thin oxide layer (figure does not show) on described Semiconductor substrate 10 surfaces; this oxide layer can protect Semiconductor substrate 10 surfaces to avoid staining; and when stoping follow-up ion to inject to the excessive damage of Semiconductor substrate 10; can also be as the oxidation buffer layer, the degree of depth that the control ion injects.
Then, (Pre-AmorphousImplantation PAI), makes described Semiconductor substrate 10 surfaces be decrystallized state described Semiconductor substrate 10 to be carried out surperficial pre-amorphous injection.
Generally select the ion of big quality when the pre-amorphous silication in surface is injected for use, for example the ion of pre-amorphous injection can be a kind of of Ge, Si, Sb.
By selecting for use big mass ion that described Semiconductor substrate 10 surfaces are bombarded, can make described Semiconductor substrate 10 surfaces decrystallized, help to suppress the degree of depth injected when follow-up PLDD mixes, form the more shallow PLDD doped layer of junction depth.
Then, as shown in Figure 3, described Semiconductor substrate 10 is carried out the first dopant ion a inject, in described Semiconductor substrate 10, form first doped layer 14.
Described first dopant ion is an indium, and the energy of injection can be 30 to 200KeV, and dosage can be 5 * 10
12To 5 * 10
13Atom/cm
2, the inclination angle during injection can be 0 degree.
Energy was bigger when described first dopant ion injected, and the degree of depth of injection is darker, the degree of depth that the degree of depth is injected greater than subsequent P LDD doping process.
After forming described first doped layer 14, described Semiconductor substrate 10 is carried out carbon or the injection of fluorine impurity, the transient state diffusion effect when being used to be suppressed at PLDD doping post growth annealing.
Follow again, as shown in Figure 4, after finishing carbon or fluorine and injecting, described Semiconductor substrate 10 is carried out the second dopant ion b inject, form PLDD doped layer 12.
Described second dopant ion is a boron, the energy that the energy that injects and the degree of depth of injection are injected less than described first dopant ion, make the PLDD doped layer 12 that forms be positioned at the top of described first doped layer 14, and described PLDD doped layer 12 contact with described first doped layer 14.
After forming described PLDD doped layer 12, described Semiconductor substrate 10 is carried out annealing process, described annealing can be spike annealing.Activate on the one hand dopant ion in the PLDD doped layer 12 by annealing, repair the damage that when ion injects, described Semiconductor substrate 10 is caused on the other hand.
After the annealing, measure the square resistance of described PLDD doped layer, the method for described measurement can be a four probe method.
In the present embodiment, in the PLDD technology that the boron ion injects, introduce the indium ion injection technology and form first doped layer 14 PLDD doped layer 12 below, on the one hand, the indium ion injection can electrically not impacting described PLDD doped layer 12;
On the other hand, first doped layer 14 that forms with indium ion be positioned at described PLDD doped layer 12 below, when adopting probe method to measure the square resistance of PLDD doped layer 12, if probe 16 can enter first doped layer 14 after pricking and wearing described PLDD doped layer 12, as shown in Figure 5, this first doped layer 14 can not cause bigger influence to described measurement result, promptly with respect to silicon substrate, the influence of 14 pairs of measurement results of described first doped layer is less, overcome owing to probe passes PLDD doped layer 12 backs and directly contacted the defective that causes measuring result error bigger with silicon substrate, the square resistance of the feasible PLDD doped layer of measuring 12 is comparatively accurate, has improved certainty of measurement.
In addition, by forming first doped layer 14, also make when measuring the square resistance of PLDD doped layer 12, can adopt the probe measurement method, four probe method for example, this method is simple to operate, and can carry out square resistance to the diverse location of Semiconductor substrate 12 and measure, and can be according to the measurement result drawing isoline, the square resistance of comparatively comprehensive reaction semiconductor substrate 10 diverse locations is with the consistency of assessment PLDD doping process at Semiconductor substrate 10 diverse locations.
Embodiment two
Described first dopant ion is an indium, and second dopant ion is a boron, and second doped layer is the PLDD doped layer.
Described Semiconductor substrate 20 is carried out surperficial pre-amorphous injection, make described Semiconductor substrate 20 surfaces be decrystallized state.
Generally select the ion of big quality when the pre-amorphous silication in surface is injected for use, for example the impurity of pre-amorphous injection can be a kind of of Ge, Si, Sb.
By selecting for use big mass ion that described Semiconductor substrate 20 surfaces are bombarded, can make described Semiconductor substrate 20 surfaces decrystallized, help to suppress the degree of depth injected when follow-up PLDD mixes, form the more shallow PLDD doped layer of junction depth.
Then, described Semiconductor substrate 20 is carried out carbon or the injection of fluorine impurity, the transient state diffusion effect when being used to be suppressed at PLDD doping post growth annealing.
Then, described Semiconductor substrate 20 is carried out first dopant ion inject, in described Semiconductor substrate 20, form first doped layer 24.
Described first dopant ion is an indium, and the energy of injection can be 30 to 200KeV, and dosage can be 5 * 10
12To 5 * 10
13Atom/cm
2, the inclination angle during injection can be 0 degree.
Energy was bigger when described first dopant ion injected, and the degree of depth of injection is darker, the degree of depth that the degree of depth is injected greater than subsequent P LDD doping process.
After forming described first doped layer 24, described Semiconductor substrate 20 is carried out second dopant ion inject, form PLDD doped layer 22.
Described second dopant ion is a boron, the energy that the energy that injects and the degree of depth of injection are injected less than described first dopant ion, make the PLDD doped layer 22 that forms be positioned at the top of described first doped layer 24, and described PLDD doped layer contact with described first doped layer 24.
After forming described PLDD doped layer 22, described Semiconductor substrate 20 is carried out annealing process, described annealing can be spike annealing.Activate on the one hand dopant ion in the PLDD doped layer 22 by annealing, repair the damage that when ion injects, described Semiconductor substrate 20 is caused on the other hand.
After the annealing, measure the square resistance of described PLDD doped layer, the method for described measurement can be a four probe method.
By the PLDD technology of injecting at the boron ion, introduce the indium ion injection technology and below PLDD doped layer 22, form first doped layer 24, can reduce when adopting sonde method to measure the square resistance of PLDD doped layer 22, the influence of 20 pairs of measurement results of Semiconductor substrate improves the accuracy of measuring.
Embodiment three
Described first dopant ion is an indium, and second dopant ion is a boron, and second doped layer is the PLDD doped layer.
Described Semiconductor substrate 30 is carried out first dopant ion inject, in described Semiconductor substrate 30, form first doped layer 34.
Described first dopant ion is an indium, and the energy of injection can be 30 to 200KeV, and dosage can be 5 * 10
12To 5 * 10
13Atom/cm
2, the inclination angle during injection can be 0 degree.
Energy was bigger when described first dopant ion injected, and the degree of depth of injection is darker, the degree of depth that the degree of depth is injected greater than subsequent P LDD doping process.
After forming described doped layer 34, described Semiconductor substrate 30 is carried out surperficial pre-amorphous injection, make described Semiconductor substrate 30 surfaces be decrystallized state.
Generally select the ion of big quality when the pre-amorphous silication in surface is injected for use, for example the impurity of pre-amorphous injection can be a kind of of Ge, Si, Sb.
By selecting for use big mass ion that described Semiconductor substrate 30 surfaces are bombarded, can make described Semiconductor substrate 30 surfaces decrystallized, help to suppress the degree of depth injected when follow-up PLDD mixes, form the more shallow PLDD doped layer of junction depth.
Then, described Semiconductor substrate 30 is carried out carbon or the injection of fluorine impurity, the transient state diffusion effect when being used to be suppressed at PLDD doping post growth annealing.
After finishing the injection of described carbon or fluorine impurity, described Semiconductor substrate 30 is carried out second dopant ion inject, form PLDD doped layer 32.
Described second dopant ion is a boron, the energy that the energy that injects and the degree of depth of injection are injected less than described first dopant ion, make the PLDD doped layer 32 that forms be positioned at the top of described first doped layer 34, and described PLDD doped layer 32 contact with described first doped layer 34.
After forming described PLDD doped layer 32, described Semiconductor substrate 30 is carried out annealing process, described annealing can be spike annealing.Activate on the one hand dopant ion in the PLDD doped layer 32 by annealing, repair the damage that when ion injects, described Semiconductor substrate 30 is caused on the other hand.
After the annealing, measure the square resistance of described PLDD doped layer, the method for described measurement can be a four probe method.
By the PLDD technology of injecting at the boron ion, introduce the indium ion injection technology and below PLDD doped layer 32, form first doped layer 34, can reduce when adopting sonde method to measure the square resistance of PLDD doped layer 32, the influence of 30 pairs of measurement results of Semiconductor substrate improves the accuracy of measuring.
Embodiment four
Described first dopant ion is an indium, and second dopant ion is a boron, and second doped layer is the PLDD doped layer.
Described Semiconductor substrate 40 is carried out surperficial pre-amorphous injection, make described Semiconductor substrate 40 surfaces be decrystallized state.
Generally select the ion of big quality when the pre-amorphous silication in surface is injected for use, for example the impurity of pre-amorphous injection can be a kind of of Ge, Si, Sb.
By selecting for use big mass ion that described Semiconductor substrate 40 surfaces are bombarded, can make described Semiconductor substrate 20 surfaces decrystallized, help to suppress the degree of depth injected when follow-up PLDD mixes, form the more shallow PLDD doped layer of junction depth.
Then, described Semiconductor substrate 40 is carried out carbon or the injection of fluorine impurity, the transient state diffusion effect when being used to be suppressed at PLDD doping post growth annealing.
After finishing the injection of execution carbon or fluorine, described Semiconductor substrate 40 is carried out second dopant ion inject, form PLDD doped layer 42.
Described second dopant ion is a boron, the energy the when energy of injection and the degree of depth of injection are injected less than described first dopant ion, and the junction depth of the feasible PLDD doped layer 42 that forms is more shallow.
After forming described PLDD doped layer 42, described Semiconductor substrate 40 is carried out first dopant ion inject, in described Semiconductor substrate 40, form first doped layer 44.
Described first dopant ion is an indium, and the energy of injection can be 30 to 200KeV, and dosage can be 5 * 10
12To 5 * 10
13Atom/cm
2, the inclination angle during injection can be 0 degree.
Energy when described first dopant ion injects is bigger, the degree of depth that the degree of depth of injecting is injected greater than described second dopant ion, first doped layer 44 that make to form be positioned at described PLDD doped layer 42 below, and described first doped layer 44 contacts with described PLDD doped layer 42.
Form institute first and mix layer by layer after 42, described Semiconductor substrate 40 is carried out annealing processs, described annealing can be spike annealing.Activate on the one hand dopant ion in the PLDD doped layer 42 by annealing, repair the damage that when ion injects, described Semiconductor substrate 40 is caused on the other hand.
After the annealing, measure the square resistance of described PLDD doped layer, the method for described measurement can be a four probe method.
By the PLDD technology of injecting at the boron ion, introduce the indium ion injection technology and below PLDD doped layer 42, form first doped layer 44, can reduce when adopting sonde method to measure the square resistance of PLDD doped layer 42, the influence of 40 pairs of measurement results of Semiconductor substrate improves the accuracy of measuring.
In other embodiments, second dopant ion in the LDD doped layer can be phosphorus, forms the NLDD doped layer that the N type mixes, and first dopant ion in first doped layer can be arsenic.With sonde method the NLDD doped layer is being carried out square resistance when measuring, the existence of described first doped layer can reduce the influence of Semiconductor substrate to measurement result, helps to improve the result's of measurement accuracy.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (18)
1, a kind of method that improves the certainty of measurement of LDD doped layer square resistance is characterized in that, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form first doped layer with first dopant ion and second doped layer with second dopant ion; Described first doped layer is positioned at described second doped layer below, and contacts with described second doped layer;
Described first dopant ion and described second dopant ion are same kind;
The dosage that described first dopant ion injects is 5 * 10
12To 5 * 10
13Atom/cm
2
Semiconductor substrate with first doped layer and second doped layer is carried out annealing process;
After the annealing, measure the square resistance of described second doped layer.
2, the method for raising LDD doped layer square resistance certainty of measurement as claimed in claim 1, it is characterized in that: the molecular weight of described second dopant ion is greater than the molecular weight of described first dopant ion.
3, the method for raising LDD doped layer square resistance certainty of measurement as claimed in claim 1 is characterized in that the step that forms first doped layer and second doped layer in described Semiconductor substrate is as follows:
Described Semiconductor substrate is carried out surperficial pre-amorphous injection;
The Semiconductor substrate of the executed pre-amorphous injection in surface is carried out first dopant ion inject, form first doped layer;
Semiconductor substrate with described first doped layer is carried out carbon or fluorine injection;
After finishing the injection of carbon or fluorine, described Semiconductor substrate is carried out second dopant ion inject, form second doped layer;
Wherein, the degree of depth of described first dopant ion injection is greater than the degree of depth of described second dopant ion injection.
4, the method for raising LDD doped layer square resistance certainty of measurement as claimed in claim 1 is characterized in that the step that forms first doped layer and second doped layer in described Semiconductor substrate is as follows:
Described Semiconductor substrate is carried out surperficial pre-amorphous injection;
The Semiconductor substrate of the executed pre-amorphous injection in surface is carried out carbon or fluorine injection;
After finishing the injection of carbon or fluorine, described Semiconductor substrate is carried out first dopant ion inject, form first doped layer;
The Semiconductor substrate that forms first doped layer is carried out second dopant ion inject, form second doped layer;
Wherein, the degree of depth of described first dopant ion injection is greater than the degree of depth of described second dopant ion injection.
5, the method for raising LDD doped layer square resistance certainty of measurement as claimed in claim 1 is characterized in that the step that forms first doped layer and second doped layer in described Semiconductor substrate is as follows:
Described Semiconductor substrate is carried out first dopant ion inject, form first doped layer;
The Semiconductor substrate that is formed with first doped layer is carried out surperficial pre-amorphous injection;
Semiconductor substrate after the surperficial pre-amorphous injection is carried out carbon or fluorine injects to carrying out;
After finishing the injection of carbon or fluorine, described Semiconductor substrate is carried out second dopant ion inject, form second doped layer;
Wherein, the degree of depth of described first dopant ion injection is greater than the degree of depth of described second dopant ion injection.
6, the method for raising LDD doped layer square resistance certainty of measurement as claimed in claim 1 is characterized in that the step that forms first doped layer and second doped layer in described Semiconductor substrate is as follows:
Described Semiconductor substrate is carried out surperficial pre-amorphous injection;
The Semiconductor substrate of the executed pre-amorphous injection in surface is carried out carbon or fluorine injection;
After finishing the injection of carbon or fluorine, described Semiconductor substrate is carried out second dopant ion inject, form second doped layer;
Semiconductor substrate with second doped layer is carried out first dopant ion inject, form first doped layer;
Wherein, the degree of depth of described first dopant ion injection is greater than the degree of depth of described second dopant ion injection.
7, as the method for the described raising of the arbitrary claim of claim 1 to 6 LDD doped layer square resistance certainty of measurement, it is characterized in that: described second doped layer is the PLDD doped layer.
8, the method for raising LDD doped layer square resistance certainty of measurement as claimed in claim 7, it is characterized in that: described first dopant ion is an indium, second dopant ion is a boron.
9, the method for raising as claimed in claim 8 LDD doped layer square resistance certainty of measurement is characterized in that: the energy that described first dopant ion injects is 30 to 200KeV.
10, as the method for the described raising of the arbitrary claim of claim 3 to 6 LDD doped layer square resistance certainty of measurement, it is characterized in that: the impurity that the decrystallized ion in described surface injects is a kind of of Ge, Si, Sb.
11, the method for raising LDD doped layer square resistance certainty of measurement as claimed in claim 1 is characterized in that: the described spike annealing that is annealed into.
12, the method for raising LDD doped layer square resistance certainty of measurement as claimed in claim 1, it is characterized in that: the method for described measurement is a four probe method.
13, the method for raising LDD doped layer square resistance certainty of measurement as claimed in claim 1, it is characterized in that: described second doped layer is the NLDD doped layer.
14, the method for raising LDD doped layer square resistance certainty of measurement as claimed in claim 13, it is characterized in that: described first dopant ion is an arsenic, second dopant ion is a phosphorus.
15, a kind of structure that improves the certainty of measurement of LDD doped layer square resistance is characterized in that, comprising:
Semiconductor substrate;
First doped layer in the described Semiconductor substrate and second doped layer with second dopant ion with first dopant ion; Described first doped layer is positioned at described second doped layer below, and contacts with described second doped layer;
Described first dopant ion and described second dopant ion are same kind;
The dosage that described first dopant ion injects is 5 * 10
12To 5 * 10
13Atom/cm
2
16, the structure of raising LDD doped layer square resistance certainty of measurement as claimed in claim 15, it is characterized in that: the molecular weight of described second dopant ion is greater than the molecular weight of described first dopant ion.
17, structure as claimed in claim 15 is characterized in that: described first dopant ion is an indium, and second dopant ion is a boron.
18, structure as claimed in claim 15 is characterized in that: described first dopant ion is an arsenic, and second dopant ion is a phosphorus.
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| CN104347441B (en) * | 2013-07-26 | 2018-01-19 | 和舰科技(苏州)有限公司 | The monitoring method of ion implanting |
| CN107579025A (en) * | 2017-08-29 | 2018-01-12 | 德淮半导体有限公司 | A kind of monitoring method of the ion implantation technology of IV races element ion |
| CN109444551B (en) * | 2018-09-10 | 2020-09-15 | 全球能源互联网研究院有限公司 | Method and circuit for testing square resistance of semiconductor |
| CN111103460B (en) * | 2018-10-25 | 2021-03-16 | 株洲中车时代半导体有限公司 | Method for improving accuracy of four-probe RS test |
| CN117059509B (en) * | 2023-10-11 | 2024-02-06 | 粤芯半导体技术股份有限公司 | Method for improving ion implantation monitoring stability |
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