CN100589240C - Once programmable memory structure and manufacturing method thereof - Google Patents
Once programmable memory structure and manufacturing method thereof Download PDFInfo
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- CN100589240C CN100589240C CN200710106056A CN200710106056A CN100589240C CN 100589240 C CN100589240 C CN 100589240C CN 200710106056 A CN200710106056 A CN 200710106056A CN 200710106056 A CN200710106056 A CN 200710106056A CN 100589240 C CN100589240 C CN 100589240C
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Abstract
The invention provides a one-time programmable memory and a manufacturing method thereof, the manufacturing method at least comprises the following steps: step 1. a substrate is provided, a field region and a trap for isolating an active region are formed on the substrate, a gate dielectric layer is formed above the active region, and polysilicon is formed on the gate dielectric layer, thus forming a polysilicon gate; the ion implantation process is adopted to form at least one impurity which is needed for forming an MOS transistor source/drain, and at least one polysilicon side wall dielectric is formed at the side surface of the polysilicon gate; step 2. the MOS capacitor region is exposed, the ion implantation process is further adopted in the MOS capacitor region to implant the impurity which is inverted with the located trap, the impurity and the trap further form a PN junction to be covered on at least one impurity. Compared with the prior art, the manufacturing method can solvethe shortcomings of mis-storage, mis-reading and easy breakdown of the transistor gate dielectric in the prior art, and the area of the OTP memory can also be reduced.
Description
Technical field
The present invention relates to programmable storage (Programmable Read Only Memory, PROM), particularly disposable programmable memory (one-time programmable Read Only Memory, manufacture method OTP-ROM).
Background technology
Otp memory is a kind of nonvolatile storage, is characterized in the one-time programming stored information, even outage also can be preserved for a long time.Its kind is a lot, and present integrated circuit is based on CMOS technology, require OTP-ROM can with CMOS standard technology compatibility.The example with CMOS standard technology compatibility early is the proposition of 5943264 United States Patent (USP)s by the patent No., constitute the OTP memory element by a nmos pass transistor and a PN junction series connection, as shown in Figure 1a, select the source end of pipe nmos pass transistor and the P end of PN junction to link to each other, select the grid of pipe to connect word line (word line, WL) 182, drain electrode connection bit line (the bit line of selection pipe, BL) 181, the N end ground connection of PN junction.During programming, word line 182 connects the high potential gating, adds higher voltage on the bit line 181, and big electric current punctures PN junction.Can be similar to after the puncture and think a resistance,, have big electric current when adding the read-out voltage that is lower than the diode cut-in voltage on the bit line 181 and pass through, can think cell stores " 1 " (or " 0 ") when word line 182 connects the high potential gating.Only have word line 182 to connect the high potential gating or only have when adding higher voltage on the bit line 181, PN junction can be not breakdown, and electric current is very little when adding the read-out voltage that is lower than the diode cut-in voltage again on bit line 181, is considered to storage " 0 " (or " 1 ").But sort memory needs higher breakdown current and voltage, and dynatron effect (snap-back) can appear in breakdown process, might damage the gate dielectric layer of selecting pipe.In addition, the PN diode must be made in the N trap, area occupied is big.
The patent No. is that 6,822,888 United States Patent (USP) proposes a kind of improved OTP storage organization, the shortcoming of having avoided said structure.It is the mos capacitance series connection with the nmos pass transistor of a thicker gate medium and thin dielectric film, shown in Fig. 1 b.This memory comprises silicon substrate 10, place 11, and the P trap 12 of selection pipe nmos pass transistor, thick gate medium 131, thin dielectric film 132, nmos pass transistor polysilicon gate (poly) electrode 141, mos capacitance polygate electrodes 142, N+ district 15 is leaked in the nmos pass transistor source.When the source end ground connection of selecting pipe NMOS pipe, after grid (connection word line) connects the high potential gating, mos capacitance grid (connection bit line) adds higher voltage, the thin dielectric film of the oxide layer 142-15 in zone will puncture between mos capacitance polysilicon gate and the N+, can be similar to after the puncture and think a resistance, the source electrode of bit line 191 and nmos pass transistor can have been stored " 1 " information by the grid control conducting that is connected word line 192.Do not have the mos capacitance that punctures can't the conducting electric current, be considered to record " 0 " information.But there are two shortcomings in this structure, and one is mos capacitance grid when adding high voltage, even select pipe not have under the situation of gating, thin dielectric film punctures also may occur in regional 142-12 between mos capacitance polysilicon gate and the P type silicon.This be because in fact after the polysilicon gate etching in order to guarantee that the gate medium reliability need implement a step rapid thermal oxidation, shown in Fig. 1 c, oxide layer 142-15 under the polysilicon edge is thicker, than the anti-puncture of thin dielectric film of regional 142-12 between polysilicon gate and the P type silicon.This wrong storage just easily appears or mistake read (even because during the bit line making alive word line not the gate medium of gating mos capacitance also may puncture and have the electric current of leakage to silicon substrate).Foregoing invention also proposes another kind of selection mode, shown in Fig. 1 d, forms the preceding N+ district 121 that forms of thermal oxidation of gate medium on the silicon substrate under the mos capacitance, and the PN junction protection does not have leakage current to silicon substrate after mos capacitance gate medium 142-121 is punctured.But this can bring new problem, and N+ can increase the oxidation rate of mos capacitance gate medium 142-121 when oxidation, and mos capacitance gate medium 142-121 thickness is increased, and puncture voltage improves.Must improve bit-line voltage in order to puncture the mos capacitance gate medium in this case, but voltage can raise between the grid leak of selecting pipe after the mos capacitance gate medium 142-121 puncture, this may cause selecting the pipe gate dielectric breakdown to lose efficacy again.In addition, also all there is a shortcoming in they, promptly because the mos capacitance thin gate oxide of this class OTP structure, and nmos pass transistor must be used thick grating oxide layer, aim at and the etch process error is considered for mask, design rule requires between them border and mos capacitance and MOS to select the distance of pipe polysilicon gate must be enough greatly.Generally all be 0.4um for 0.13-0.25umCMOS technology for example, i.e. mos capacitance and MOS selection pipe polysilicon gate is 0.8um apart from minimum, and this causes whole memory usage area bigger.
Summary of the invention
In view of the above shortcoming of prior art, the present invention proposes a kind of improved otp memory and manufacture method thereof, misread out and select the easy shortcoming that punctures of pipe gate medium to solve the mistake storage, and dwindle the area of otp memory.
The manufacture method of the otp memory that the present invention proposes may further comprise the steps:
Step 1, substrate is provided, on above-mentioned substrate, form the place and the trap of isolating active area, above active area, form gate dielectric layer, on gate dielectric layer, form polysilicon, thereby the formation polysilicon gate adopts ion implantation technology to implant and forms the needed at least a impurity of MOS transistor source/drain, then forms at least one polysilicon side wall dielectric at multi-crystal silicon grid side;
When above-mentioned trap was the N trap, above-mentioned impurity was p type impurity; When above-mentioned trap was the P trap, above-mentioned impurity was N type impurity.
The impurity of implanting in the described step 2 is that energy is the arsenic ion of 300-800keV or the phosphonium ion that energy is 150-500keV.
In the described step 2, expose the mos capacitance zone by the photoetching development technology behind the covering photoresistance film.
In the described step 1, form polysilicon gate by etching, above-mentioned polysilicon gate comprises the polysilicon gate of MOS transistor and the polysilicon gate in mos capacitance zone at least.
The present invention also provides a kind of otp memory, comprise substrate, the place and the trap of the isolation active area that on above-mentioned substrate, forms, above active area, be formed with gate dielectric layer, polysilicon, in trap, implant at least a impurity that has the MOS transistor source/drain to need, the mos capacitance zone also implant the part that covers above-mentioned at least a impurity, with the impurity of the trap transoid at place, as forming PN junction.
When above-mentioned trap was the N trap, above-mentioned impurity was p type impurity; When above-mentioned trap was the P trap, above-mentioned impurity was N type impurity.
The impurity that implant in the mos capacitance zone can comprise that energy is the arsenic ion of 300-800keV or the phosphonium ion that energy is 150-500keV.
Above-mentioned gate dielectric layer can form by the method for deposition or oxidation growth.
The present invention compared with prior art, it can solve the shortcoming that mistake storage of the prior art is misread out and the transistor gate medium easily punctures, and can also dwindle the area of otp memory.Its beneficial effect comprises, 1, the PN junction below the mos capacitance gate medium overcome the shortcoming that the mistake storage is misread out; 2, the impurity that mixes in the gate medium of mos capacitance can reduce its puncture voltage, and the operating voltage of bit line when promptly storing can rationally be controlled by energy and the dosage of regulating implant impurity, thereby has avoided the breakdown possibility of gate medium of MOS transistor; 3, MOS transistor and mos capacitance are all used the gate medium with a kind of thickness, this can dwindle their polysilicon gate distances, for example can be 0.22um for the 0.13umCMOS standard technology, can be 0.3um for the 0.18umCMOS standard technology, and transistorized length also can be used minimum dimension.
Description of drawings
Fig. 1 a is the circuit of otp memory in the prior art.
Fig. 1 b-1d is the structure of another kind of otp memory in the prior art.
Fig. 2 a-2d is respectively the manufacturing step schematic diagram of the otp memory of a preferred embodiment of the present invention.
Fig. 3 a-3b is the equivalent circuit diagram of the otp memory of a preferred embodiment of the present invention.
Fig. 4 is the structure of the otp memory of another preferred embodiment of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is done to introduce further, but not as a limitation of the invention.
The present invention adopts standard CMOS process to be made in same N trap or the P trap MOS transistor of otp memory and mos capacitance and uses gate medium with a kind of thickness, but in mos capacitance device zone the mos capacitance device is increased the implantation of a step and trap transoid impurity after side wall dielectric (spacer) formation of polysilicon, the ion of implantation passes the part drain electrode of gate medium and following trap formation PN junction and covering MOS transistor.
The manufacturing step of the otp memory of a preferred embodiment of the present invention comprises shown in Fig. 2 a-2d:
Step 1, adopt silicon sheet material as substrate 20, it can be P type or N type, or the certain thickness silicon thin film of extension above it, or (the Silicon on Insulator of the silicon on the employing insulator, abbreviation SOI) silicon (the Silicon on Sapphire on material or the sapphire, abbreviation SOS) material of formation silicon thin film on the material, in this embodiment, adopt the P type silicon chip substrate of low-resistivity (less than 5ohm.cm), on above-mentioned substrate 20, form the place 21 and the trap 22 of isolating active area 2, wherein utilize selective oxidation technology or shallow-trench isolation technology to form place 21 on the surface of substrate 20, the enforcement trap injects, and forms the P trap 22 of isolating place 21 and nmos pass transistor, and structure is shown in Fig. 2 a.Wherein, nmos pass transistor is to select pipe; P trap injection condition can be identical with other transistorized insulation requests, so that save mask plate in manufacturing process; Also can be different with other transistorized insulation requests, in other steps, finish comprising of standard CMOS process multiple P trap and other traps of N trap isolate.
Step 3, the needed N-type of the source/drain impurity that adopts autoregistration or other suitable methods to implant lightly doped nmos pass transistor forms light doping section 25.This step can be implemented separately in this step, also can implant synchronously so that save the light shield mask plate with other transistors.
Step 5, the needed N+ type of the source/drain impurity that adopts autoregistration or other suitable methods to implant nmos pass transistor once more forms doped region 27.This step can be implemented separately in this step, also can implant synchronously so that save the light shield mask plate with other transistors.
Step 6, cover the photoresistance film, otp memory is carried out photoetching and development, expose the mos capacitance zone, implant N type impurity, form doped region 28, it passes gate medium 23 makes this part gate medium change, become gate medium 231, in the P trap, form PN junction with the P trap, and cover part N+ type impurity 27.Wherein N type impurity 28 can adopt the foreign ion that high-energy is implanted, for example be the arsenic ion of 300-800keV or the phosphonium ion of 150-500keV, although mos capacitance gate medium 231 and selection pipe gate medium 23 are of uniform thickness, but because the damage and the impurity of the ion that high-energy is implanted mix, gate medium 231 is littler than the puncture voltage of gate medium 23, the dosage of ion is big more, energy is high more, quality is heavy more, and then the difference of puncture voltage is big more.Preferable, dosage, energy and the kind that can regulate the ion of implantation according to the chip circuit designing requirement of otp memory also can increase the puncture voltage that gate medium 231 is regulated in the implantation of metal ion.The main effect of the PN junction that N type impurity doped region 28 and P trap form be guarantee gate medium 231 breakdown after to the electric leakage of P trap, the main effect of N type impurity doped region 28 cover part N+ type impurity doped regions 27 is that the N type zone, bottom that guarantees mos capacitance device zone well contacts with the N type of the drain electrode of MOS transistor is regional.
Step 7 is implanted the needed ion of other devices, carries out impurity activation, metallization, and interconnection waits the needed step of other CMOS technologies, is not main points of the present invention herein, does not describe in detail at this.
Equivalent electric circuit of the present invention is shown in Fig. 3 a and Fig. 3 b, the 0V common port of the grid connected storage array of mos capacitance 31, the P of diode 33 holds the also 0V common port of connected storage array, the word line (WL) 382 of the grid connected storage array of nmos pass transistor 32, the bit line (BL) 381 of the source electrode connected storage array of nmos pass transistor 32.If the voltage that bit line 381 inserts when writing information is greater than the puncture voltage of the gate medium of mos capacitance 31, puncture voltage less than the gate medium of nmos pass transistor 32, word line 382 meets operating supply voltage Vcc, the voltage of node 34 then can approach the voltage of bit line 381, make that the gate medium of mos capacitance 31 is breakdown, can not recover again after mos capacitance 31 punctures that equivalence is a resistance 35, shown in Fig. 3 b, be considered to permanent storage information " 1 "; During sense information, bit line 381 and word line 382 all are connected to voltage vcc, can read current on the bit line 381, and sense information " 1 ".Connect high voltage on the bit line 381 and word line when being 0V if only have when writing information, then node 34 is floating empty, and the gate medium of mos capacitance can be not breakdown, thinks the information of having stored " 0 "; During sense information, bit line 381 and word line 382 all are connected to voltage vcc, but owing to the electric capacity that is connected in transistor drain is not breakdown, so bit line current is 0, at this moment, information is " 0 ".
Fig. 4 represents the otp memory structure of another preferred embodiment of the present invention, its manufacturing step is to similar shown in Fig. 2 a-2d, in this embodiment, comprise silicon sheet material substrate 40, the place 41 and the N trap 42 of the isolation active area 4 that on substrate 40, forms, the transistorized gate medium 43 of PMOS, the gate medium 431 of mos capacitance, the polysilicon gate of PMOS transistor and mos capacitance is respectively 441 and 442, the PMOS transistor mixes p type impurity and forms light doping section 45, the heavily doped region 47 that mixes the formation of heavy doping p type impurity is the transistorized source-drain area of PMOS, mix p type impurity in doped region 48, doped region 48 is connected with PMOS transistor drain 47, and forms PN junction with N trap 42, gate medium 431 is because of the p type impurity of implanting in the doped region 48 damages, so its puncture voltage is lower than the transistorized gate medium 43 of PMOS.
The above is preferred embodiment of the present invention only, is not to be used for limiting practical range of the present invention; If do not break away from the spirit and scope of the present invention, the present invention is made amendment or is equal to replacement, all should be encompassed in the middle of the protection range of claim of the present invention.
Claims (9)
1. the manufacture method of disposable programmable memory is characterized in that may further comprise the steps at least:
Step 1, substrate is provided, on above-mentioned substrate, form the place and the trap of isolating active area, above active area, form gate dielectric layer, on gate dielectric layer, form polysilicon, thereby the formation polysilicon gate adopts ion implantation technology to implant and forms the needed at least a impurity of MOS transistor source/drain, then forms at least one polysilicon side wall dielectric at multi-crystal silicon grid side;
Step 2, expose the mos capacitance zone, adopt the impurity of the trap transoid at ion implantation technology implantation and place again in the mos capacitance zone, the puncture voltage that makes the mos capacitance gate medium is less than the puncture voltage as the gate medium of the above-mentioned MOS transistor of selecting pipe, and the impurity of the trap transoid at above-mentioned and place is with trap formation PN junction and cover above-mentioned at least a impurity.
2. manufacture method according to claim 1, when it is characterized in that above-mentioned trap is the N trap, the impurity of the trap transoid at above-mentioned and place is p type impurity; When above-mentioned trap was the P trap, the impurity of the trap transoid at above-mentioned and place was N type impurity.
3. manufacture method according to claim 2 is characterized in that the impurity of implanting in the described step 2 comprises that energy is the arsenic ion of 300-800keV or the phosphonium ion that energy is 150-500keV.
4. manufacture method according to claim 3 is characterized in that in the described step 2, exposes the mos capacitance zone by the photoetching development technology behind the covering photoresistance film.
5. manufacture method according to claim 4 is characterized in that in the described step 1, forms polysilicon gate by etching, and above-mentioned polysilicon gate comprises the polysilicon gate of MOS transistor and the polysilicon gate in mos capacitance zone at least.
6. disposable programmable memory, comprise substrate, the place and the trap of the isolation active area that on above-mentioned substrate, forms, above active area, be formed with gate dielectric layer, polysilicon, in trap, implant at least a impurity that has the MOS transistor source/drain to need, it is characterized in that the mos capacitance zone also implant the part that covers above-mentioned at least a impurity, with the impurity of the trap transoid at place, as forming PN junction; The puncture voltage of mos capacitance gate medium is less than the puncture voltage of the gate medium of the above-mentioned MOS transistor of conduct selection pipe.
7. disposable programmable memory according to claim 6, when it is characterized in that above-mentioned trap is the N trap, the impurity of the trap transoid at above-mentioned and place is p type impurity; When above-mentioned trap was the P trap, the impurity of the trap transoid at above-mentioned and place was N type impurity.
8. disposable programmable memory according to claim 7 is characterized in that the impurity that implant in the mos capacitance zone comprises that energy is the arsenic ion of 300-800keV or the phosphonium ion that energy is 150-500keV.
9. disposable programmable memory according to claim 6 is characterized in that above-mentioned gate dielectric layer forms by the method for deposition or oxidation growth.
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| CN200710106056A CN100589240C (en) | 2007-05-31 | 2007-05-31 | Once programmable memory structure and manufacturing method thereof |
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| CN200710106056A CN100589240C (en) | 2007-05-31 | 2007-05-31 | Once programmable memory structure and manufacturing method thereof |
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101752381B (en) * | 2008-12-10 | 2013-07-24 | 上海华虹Nec电子有限公司 | OTP (one-time programmable) element structure and preparation method thereof |
| CN101752384B (en) * | 2008-12-18 | 2012-06-13 | 北京兆易创新科技有限公司 | One-time programmable memory and manufacture and programming reading method |
| JP5328020B2 (en) * | 2009-01-15 | 2013-10-30 | セイコーインスツル株式会社 | Memory device and memory access method |
| CN102544004A (en) * | 2010-12-09 | 2012-07-04 | 和舰科技(苏州)有限公司 | Embedded flash memory and manufacturing method thereof |
| CN102306210A (en) * | 2011-07-05 | 2012-01-04 | 上海宏力半导体制造有限公司 | MOS transistor modeling method for verifying consistency of layout and schematic diagram |
| CN103050495B (en) * | 2011-10-14 | 2016-06-15 | 无锡华润上华科技有限公司 | OTP memory cell and making method thereof |
| US9183933B2 (en) * | 2014-01-10 | 2015-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell |
| CN104851885B (en) * | 2014-02-13 | 2018-12-21 | 中国科学院微电子研究所 | A kind of manufacturing method of otp memory array |
| TWI543302B (en) * | 2014-03-14 | 2016-07-21 | 林崇榮 | One time programming memory and associated memory cell structure |
| CN109326603A (en) * | 2017-02-16 | 2019-02-12 | 杰华特微电子（张家港）有限公司 | A kind of single programmable read-only memory based on CMOS technology |
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Address after: 215123 333 Xinghua street, Suzhou Industrial Park, Jiangsu Patentee after: Warship chip manufacturing (Suzhou) Limited by Share Ltd Address before: 215025 Xinghua street, Suzhou Industrial Park, Suzhou, Jiangsu 333 Patentee before: Hejian Technology (Suzhou) Co., Ltd. |