US20230413540A1

US20230413540A1 - One-time programmable memory unit cell

Info

Publication number: US20230413540A1
Application number: US18/239,745
Authority: US
Inventors: Geeng-Chuan Chern
Original assignee: HeFeChip Corp Ltd
Current assignee: HeFeChip Corp Ltd
Priority date: 2020-04-13
Filing date: 2023-08-29
Publication date: 2023-12-21
Also published as: US20210408017A1; US20210320110A1; US11152381B1

Abstract

A one-time programmable memory unit cell includes a substrate comprising thereon a first active area and a second active area isolated from the first active area, a read select transistor disposed on the first active area, a data storage transistor disposed on the first active area and serially connected to the read select transistor, and a program select transistor disposed on the second active area. During read operation, the state “1” bit current is the transistor “on” current, while the state “0” bit current is the transistor “off” current.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of U.S. application Ser. No. 17/474,030, filed on Sep. 13, 2021, which is a continuation application of U.S. application Ser. No. 16/846,424, filed on Apr. 13, 2020. The contents of these applications are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure relates generally to the field of semiconductor technology. More particularly, the present disclosure relates to a three-transistor (3T) one-time programmable (OTP) memory device.

2. Description of the Prior Art

As known in the art, non-volatile memory retains stored information even after power is removed from the non-volatile memory circuit. Some non-volatile memory designs permit reprogramming, while other designs only permit one-time programming. Thus, one form of non-volatile memory is a One-Time Programmable (OTP) memory.
An OTP memory may contain an antifuse. An antifuse functions oppositely to a fuse by initially being nonconductive. When programmed, the antifuse becomes conductive. To program an antifuse, a dielectric layer such as an oxide is subjected to a high electric field to cause dielectric breakdown or oxide rupture. After dielectric breakdown, a conductive path is formed through the dielectric and thereby makes the antifuse become conductive.
To read the memory cell, a current passing through the ruptured or unruptured oxide is typically required. However, some ruptured oxides could be in a soft breakdown condition. The leakage current of the oxide in soft breakdown condition could be small. Therefore, a complicate sensing amplifier is often needed to compare the source side and drain side gate oxide leakage currents.

SUMMARY OF THE INVENTION

It is one objective of the present disclosure to provide a three-transistor (3T) one-time programmable (OTP) memory unit cell in order to solve the deficiencies or shortcomings of the prior art.
One aspect of the invention provides a one-time programmable memory unit cell including a substrate comprising thereon a first active area and a second active area isolated from the first active area, a read select transistor disposed on the first active area, a data storage transistor disposed on the first active area and serially connected to the read select transistor, and a program select transistor disposed on the second active area. The read select transistor comprises a first gate, a first gate dielectric layer between the first gate and the substrate, a first drain region in the substrate on one side of the first gate, and a first source region in the substrate on an opposing side of the first gate.
The data storage transistor comprises a second gate, a second gate dielectric layer between the second gate and the substrate, a second drain region in the substrate on one side of the second gate, a second source region in the substrate on an opposing side of the second gate, and a channel region between the second drain region and the second source region. The second drain region merges with the first source region of the read select transistor. The second gate comprises a main gate portion directly above the channel region, a first extension gate portion and a second extension gate portion on two opposite sidewalls of the main gate portion, respectively. The main gate portion, the first extension gate portion and the second extension gate portion constitute a gate electrode of the data storage transistor. The second gate dielectric layer comprises a first portion between the drain region and the first extension gate portion, a second portion between the channel region and the main gate portion, and a third portion between the source region and the second extension gate portion. The first portion and the third portion are thinner than the second portion.
The program select transistor comprises a third gate, a third gate dielectric layer between the third gate and the substrate, a third drain region in the substrate on one side of the third gate, and a third source region in the substrate on the other side of the third gate. The third drain region is electrically coupled to the second gate of the data storage transistor.
According to some embodiments, the one-time programmable memory unit cell further includes a first dielectric spacer and a second dielectric spacer on the first extension gate portion and the second extension gate portion, respectively.
According to some embodiments, the first dielectric spacer and the second dielectric spacer are situated directly on the first portion and the third portion of the gate dielectric layer, respectively.
According to some embodiments, the first extension gate portion of the gate electrode is situated directly on the first portion of the gate dielectric layer and the second extension gate portion of the gate electrode is situated directly on the third portion of the gate dielectric layer.
According to some embodiments, the one-time programmable memory unit cell further includes a first vertical PN junction disposed between the drain region and the channel region and proximate to a top surface of the substrate, wherein the first vertical PN junction is situated directly underneath the main gate portion of the gate electrode; and a second vertical PN junction disposed between the source region and the channel region and proximate to the top surface of the substrate, wherein the second vertical PN junction is situated directly underneath the main gate portion of the gate electrode.
According to some embodiments, the first gate, the second gate, and the third gate comprise a single polysilicon layer or a metal gate.
According to some embodiments, the data storage transistor has a gate-to-source/drain breakdown voltage lower than a gate-to-channel breakdown voltage and a gated source/drain junction breakdown voltage.
According to some embodiments, the substrate is a P type silicon substrate, wherein the first drain region, the first source region, the second drain region, the second source region, the third drain region, and the third source region are N⁺ doping regions.
According to some embodiments, the program select transistor is constructed on a triple well structure comprising a deep N well in the P type silicon substrate and a P well isolated from the P type silicon substrate by the deep N well.
According to some embodiments, the substrate comprises a silicon-on-insulator (SOI) substrate.
According to some embodiments, the third source region is electrically coupled to ground.
According to some embodiments, the second active area is disposed in close proximately to the first active area.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:

FIG. 1 is a cross section of a semiconductor memory cell in accordance with one embodiment of the invention;

FIG. 2 is a cross section of a semiconductor memory cell in accordance with another embodiment of the invention, wherein a triple well is employed;

FIG. 3 is a schematic diagram showing an exemplary semiconductor memory array composed of the semiconductor memory cell as depicted in FIG. 1 ;

FIG. 4 shows the selected memory cell for the program “1” operation in the semiconductor memory array;

FIG. 5 is a cross section of the selected data storage transistor during the program “1” operation;

FIG. 6 shows the selected memory cell for the program “0” operation in the semiconductor memory array;

FIG. 7 is a cross section of the selected data storage transistor during the program “0” operation;

FIG. 8 is a cross section of the data storage transistor with “1” state during read operation;

FIG. 9 is a cross section of the data storage transistor with “0” state during read operation; and

FIG. 10 to FIG. 17 are schematic diagrams showing an exemplary method for fabricating a MOS transistor having lower gate-to-source/drain breakdown voltage according to one embodiment of the invention.

DETAILED DESCRIPTION

Advantages and features of embodiments may be understood more readily by reference to the following detailed description of preferred embodiments and the accompanying drawings. Embodiments may, however, be embodied in many different forms and should not be construed as being limited to those set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey exemplary implementations of embodiments to those skilled in the art, so embodiments will only be defined by the appended claims. Like reference numerals refer to like elements throughout the specification.
Embodiments are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). Thus, these embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the embodiments.
It will be appreciated that although some conductivity types have been used for illustrative purposes, the invention may be practiced with opposite conductivity types. For example, an NMOS transistor in one embodiment may be replaced with a PMOS transistor in another embodiment without departing from the spirit and scope of the invention.
The present invention pertains to a MOS transistor having lower gate-to-source/drain breakdown voltage and OTP memory devices using such MOS transistor. The OTP memory devices may comprise a plurality of three-transistor (3T) bit cell structures in the OTP memory array. The OTP memory array utilizes the channel current, instead of ruptured or unruptured dielectric leakage current, for read operations. This invention has a great advantage over the prior art because the state “1” bit current is the transistor “on” current that is consistently high without too much variation other than those caused by manufacture process fluctuation, while the state “0” bit current is the very small transistor “off” current.
One aspect of the invention provides a semiconductor device including at least an OTP unit cell. A programming path for programming the OTP unit cell is different from a reading path for reading the OTP unit cell. According to some embodiments, the OTP unit cell comprises a programmable MOS transistor that is electrically programmed to “1” state or “0” state. According to some embodiments, the programmable MOS transistor is programmed to the “1” state by rupturing a gate dielectric layer between a gate and a drain of the MOS transistor. According to some embodiments, the programmable MOS transistor is programmed to “0” state by rupturing the gate dielectric layer between the gate and a source of the MOS transistor. According to some embodiments, the gate of the programmable MOS transistor is switched between ground and floating by a switching MOS transistor.
FIG. 1 is a cross section of a semiconductor memory cell (or OTP unit cell) in accordance with one embodiment of the invention. According to one embodiment of the invention, the illustrated semiconductor memory cell may be a 3T bit cell structure that is included in an OTP memory array. As shown in FIG. 1 , the semiconductor memory cell (or OTP unit cell) 1 comprises a read select transistor T_RSthat is in series connection with a data storage transistor T_DSfor storing a digit “1” or a digital “0” data. The read select transistor Tits and the data storage transistor T_DSmay be constructed on the first active area 101 that is isolated by a first trench isolation structure TI₁. The first active area 101 may be defined on a semiconductor substrate 100 having a first conductivity type, for example, P type. According to one embodiment, for example, the semiconductor substrate 100 may be a silicon substrate or a silicon-on-insulator (SOI) substrate, but not limited thereto.
The read select transistor Tits may be used to “select” a memory cell for reading. According to one embodiment of the invention, the read select transistor T_RScomprises a first gate G₁, a first gate dielectric layer OX₁between the first gate G₁and the semiconductor substrate 100, a first drain region D₁in the semiconductor substrate 100 on one side of the first gate G₁, and a first source region S₁in the semiconductor substrate 100 on the other side of the first gate G₁. According to one embodiment of the invention, the read select transistor Tits may be an NMOS transistor, and the first drain region D₁and the first source region S₁may be N⁺ doping regions. The first gate G₁may be a single polysilicon (or single poly) layer or a metal gate.
According to one embodiment of the invention, the data storage transistor T_DScomprises a second gate G₂, a second gate dielectric layer OX₂between the second gate G₂and the semiconductor substrate 100, a second drain region D₂in the semiconductor substrate 100 on one side of the second gate G₂, a second source region S₂in the semiconductor substrate 100 on the other side of the second gate G₂, and a channel region CH between the second drain region D₂and the second source region S₂. According to one embodiment of the invention, the data storage transistor T_DSmay be an NMOS transistor, and the second drain region D₂and the second source region S₂may be N⁺ doping regions. Likewise, the second gate G₂may be a single polysilicon layer or a metal gate. Therefore, the read select transistor T_RSand the data storage transistor T_DSconstitute two serially connected NMOS transistors on the first active area 101. The N⁺ doping region 132 between the first gate G₁and the second gate G₂in the semiconductor substrate 100 is commonly shared by the read select transistor T_RSand the data storage transistor T_DS.
According to one embodiment of the invention, the portions 204 and 206 of the second gate dielectric layer OX₂that are situated directly between and the second gate G₂and, respectively the second drain region D₂and the second source region S₂are thinner than the portion 202 of the second gate dielectric layer OX₂that is situated directly between the channel region CH and the second gate G₂. Therefore, the second gate dielectric layer OX₂has different thicknesses, thereby achieving a lower gate-to-source/drain breakdown voltage of the data storage transistor T_DS.
Please refer to FIG. 16 for the detailed MOS transistor structure. FIG. 16 is a cross section of an exemplary MOS transistor suited for the data storage transistor having lower gate-to-source/drain breakdown voltage according to one embodiment of the invention, wherein like layers, elements or regions are designated by like numeral numbers or labels. As shown in FIG. 16 , the MOS transistor T comprises a semiconductor substrate 100, a drain region 104 and a source region 106 in the semiconductor substrate 100, a channel region CH between the drain region 104 and the source region 106, a gate electrode 210 disposed on the channel region CH, a gate dielectric layer 200 between the gate electrode 210 and the semiconductor substrate 100. The gate dielectric layer 200 has different thicknesses. According to one embodiment of the invention, the portions 204 and 206 of the gate dielectric layer 200 that are situated directly between the gate electrode 210 and, respectively, the drain region 104 and the source region 106 are thinner than the portion 202 of the gate dielectric layer 200 that is situated directly between the channel region CH and the gate electrode 210.
According to one embodiment of the invention, the gate electrode 210 comprises a main gate portion 212 disposed directly above the channel region CH and two extension gate portions 214 and 216 disposed on two opposite sidewalls of the main gate portion 212. The extension gate portion 214 of the gate electrode 210 is situated directly on the portion 204 of the gate dielectric layer 200 and the extension gate portion 216 of the gate electrode 210 is situated directly on the portion 206 of the gate dielectric layer 200. The extension gate portion 214 of the gate electrode 210 is in direct contact with the portion 204 of the gate dielectric layer 200 and the extension gate portion 216 of the gate electrode 210 is in direct contact with the portion 206 of the gate dielectric layer 200. According to one embodiment of the invention, the main gate portion 212, the extension gate portion 214, and the extension gate portion 216 of the gate electrode 210 may be composed of doped polysilicon, silicide, or metal, but is not limited thereto.
The outer surface of the extension gate portion 214 of the gate electrode 210 is covered with a dielectric spacer 224 and the outer surface of the extension gate portion 216 of the gate electrode 210 is covered with a dielectric spacer 226. According to one embodiment of the invention, for example, the dielectric spacers 224 and 226 may comprise silicon nitride, silicon oxynitride or silicon oxide, but is not limited thereto. According to one embodiment of the invention, an end surface 204 a of the portion 204 may be aligned with an outer surface of the dielectric spacer 224 and an end surface 206 a of the portion 206 may be aligned with an outer surface of the dielectric spacer 226. According to one embodiment of the invention, the dielectric spacer 224 may be situated on the portion 204 of the gate dielectric layer 200 and the dielectric spacer 226 may be situated on the portion 206 of the gate dielectric layer 200.
According to one embodiment of the invention, the MOS transistor T further comprises a self-aligned silicide (or salicide) layer 232 on the gate electrode 210, a salicide layer 234 on the drain region 104, and a salicide layer 236 on the source region 106. According to one embodiment of the invention, salicide layers 232, 234 and 236 may comprise NiSi, CoSi, TiSi, or WSi, but is not limited thereto. According to one embodiment of the invention, the salicide layer 234 is contiguous with the end surface 204 a of the portion 204, and the salicide layer 236 is contiguous with the end surface 206 a of the portion 206.
According to one embodiment of the invention, the vertical PN junctions 104 a and 106 a, which are proximate to the top surface of the semiconductor substrate 100 and are between the channel region CH and, respectively, the drain region 104 and the source region 106 are situated directly underneath the main gate portion 212 of the gate electrode 210. By providing such configuration, a higher gated source/drain junction breakdown voltage can be provided. According to one embodiment of the invention, the MOS transistor T has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and the gated source/drain junction breakdown voltage.
Adverting to FIG. 1 , the semiconductor memory cell 1 further comprises a program select transistor T_PSthat is used to “select” a memory cell for programming. The program select transistor T_PSis constructed on the second active area 102 that is isolated by a second trench isolation structure TI 2. The second active area 102 may be disposed in close proximately to the first active area 101. According to one embodiment of the invention, the program select transistor T_PScomprises a third gate G₃, a third gate dielectric layer OX₃between the third gate G₃and the semiconductor substrate 100, a third drain region D₃in the semiconductor substrate 100 on one side of the third gate G₃, and a third source region S₃in the semiconductor substrate 100 on the other side of the third gate G₃. The third drain region D₃is electrically coupled to the second gate G₂.
According to one embodiment of the invention, the program select transistor T_PSmay be an NMOS transistor, and the third drain region D₃and the third source region S₃may be N⁺ doping regions. Likewise, the third gate G₃may be a single polysilicon layer or a metal gate.
In another embodiment, as shown in FIG. 2 , the semiconductor memory cell 1 a comprising the read select transistor T_RS, the data storage transistor T_DS, and the program select transistor T_PSmay be constructed on a triple well structure comprising a deep N well 110 in the P type semiconductor substrate (P Substrate) 100 and a P well 120 isolated from the P type semiconductor substrate 100 by the deep N well 110. During program or read operations, the P well may be biased to a predetermined P well voltage through a P well pickup region (not shown in this figure). It is understood that the illustrated transistors in FIG. 1 and FIG. 2 may further comprise other elements such as spacers on sidewalls of the gates or lightly doped drain (LDD) regions merged with the heavily doped source/drain regions, which are not explicitly shown in the figures for the sake of simplicity.
According to one embodiment of the invention, during operation, the first drain region D₁is electrically coupled to a bit line voltage V_BL, the first source region S₁and the second drain region D₂(i.e., the N⁺ doping region 132) are electrically floating, the second source region S₂is electrically coupled to a source line voltage V_SL, the third source region S₃is electrically coupled to ground (GND), the first gate G₁is electrically coupled to a read select voltage V_Rsel, and the third gate G₃is electrically coupled to a program select voltage V_Psel.
FIG. 3 is a diagram showing an exemplary semiconductor memory array composed of the semiconductor memory cell as depicted in FIG. 1 . It is understood that although only a 2×3 cell array are shown in FIG. 3 , the semiconductor memory array may be an arbitrary N by M array comprising memory cells arranged in N rows and M columns, where N and M are arbitrary numbers. For example, the memory cell MC₀at the crosspoint of the row Ro and the column Co comprises the read select transistor T_RS, the data storage transistor T_DS, and the program select transistor T_PSas described in FIG. 1 . The first drain region D₁of the read select transistor T_RSis electrically connected to a bit line BL₀, the second source region S₂of the data storage transistor T_DSis electrically connected to a source line SL₀, the first gate G₁of the read select transistor T_RSis electrically connected to a read select line R_sel0, and the third gate G₃of the program select transistor T_PSis electrically connected to a program select line P_sel0.
Please refer to Table 1 below, FIG. 4 , FIG. 5 , and briefly to FIG. 1 and FIG. 2 . FIG. 4 shows the selected memory cell (or bit unit) of the semiconductor memory array. FIG. 5 is a cross section of the selected data storage transistor T_DSduring the program “1” operation. Table 1 shows exemplary bias conditions for programming digital “1” to the selected semiconductor memory cell in FIG. 4 .

TABLE 1

Program “1” Condition

	Terminal	Bias Voltage

	Selected P_Sel, V_Psel	1-3 V
	Unselected P_Sel	0 V
	Selected R_Sel, V_Rsel	3-10 V
	Selected BL, V_BL	3-10 V or Ramp up from 0 V till
		breakdown
	Unselected BL	0 V or Floating
	V_SL	0 V or Floating
	V_PW	0 V or Floating
	V_PSub/V_DNW	0 V or Floating

According to one embodiment of the invention, to program the selected bit unit to “1” state, the following bias conditions may be implemented:

- (i) a program select voltage V_Pselof about 1-3V is applied to the selected program select line P_sel(selected P_sel) to turn on the program select transistor T_PS;
- (ii) a high enough read select voltage V_Rselranging between, for example, 3-10V may be applied to the selected read select line R_sel(selected R_sel);
- (iii) all the unselected program select lines P_sel(unselected P_sel) and unselected read select lines R_sel(unselected R_sel) are connected to ground GND (or 0 V);
- (iv) the semiconductor substrate 100 (e.g., P Substrate) is usually connected to ground (V_PSub=0 V), and for the triple well structures as set forth in FIG. 2 , the deep N well 110 is connected to ground (V_DNW=0V) while the P well 120 may be floating or connected to ground (V_PW=0V or floating);
- (v) all the source lines SL and unselected bit lines BL are floating or connected to ground (0V); and
- (vi) the selected bit line voltage V_BLis ramped up, preferred to be through a current limiter to prevent overloading the bit line voltage supply circuit, until a sudden increase in current A and a sudden drop in voltage across the second gate dielectric layer OX₂, indicating dielectric breakdown B, in FIG. 5 , directly above the second drain region D₂of the selected data storage transistor T_DS.

Alternatively, the dielectric breakdown B may be caused by simply applying a pre-set bit line voltage V_BLthat is higher than gate dielectric breakdown voltage (i.e., portion 204 OX₂breakdown voltage), to the selected bit line, which is also preferred to be done through a current limiter to prevent overloading the bit line voltage supply circuit.
It is one technical feature of the invention that to write digital “1”, only the thinner portion 204 of the second gate dielectric layer OX₂that is adjacent to the second drain region D₂(i.e. drain side dielectric) is ruptured, while the portion 206 of the second gate dielectric layer OX₂that is adjacent to the second source region S₂(i.e. source side dielectric) and the portion 202 directly over the channel region CH (i.e. channel dielectric) are remained intact.
Preferably, the data storage transistor T_DSmay have source junction breakdown voltage and drain junction breakdown voltage, which are higher than the gate dielectric breakdown voltage of the data storage transistor. However, this is not necessary for the embodiments with triple well structures as described in FIG. 2 . Further, the gate dielectric breakdown voltage and the junction breakdown voltage of the read select transistor T_RSare both higher than the gate dielectric breakdown voltage of the data storage transistor T_DS. This can be achieved by using thicker gate dielectric or cascoding two transistors for the read select transistor T_RS.
Please refer to Table 2 below, FIG. 6 , FIG. 7 , and briefly to FIG. 1 and FIG. 2 . FIG. 6 shows the selected memory cell (or bit unit) in the semiconductor memory array. FIG. 7 is a cross section of the selected data storage transistor T_DSduring the program “0” operation. Table 2 shows exemplary bias conditions for programming digital “0” to the selected semiconductor memory cell in FIG. 6 .

TABLE 2

Program “0” Condition

	Terminal	Bias Voltage

	Selected P_Sel, V_Psel	1-3 V
	All R_Sel	0 V or don't care
	Unselected P_Sel,	0 V
	Selected SL, V_SL	3-10 V or Ramp up from 0 V till
		breakdown
	Unselected SL	0 V or Floating
	All BL, V_BL	0 V or Floating
	P-Well, V_PW	0 V or Floating
	Others, V_PSub/V_DNW	0 V or Floating

According to one embodiment of the invention, to program the selected bit unit to “0” state, the following bias conditions may be implemented:

- (i) a program select voltage V_Pselof about 1-3V is applied to the selected program select line P_sel(selected P_sel) to turn on the program select transistor T_PS;
- (ii) all the unselected program select lines P_sel(unselected P_sel) are connected to ground (or 0 V);
- (iii) all the read select lines R_selare connected to 0 V or don't care;
- (iv) the semiconductor substrate 100 (e.g., P Substrate) is usually connected to ground (0 V), and for the triple well structures as set forth in FIG. 2 , the deep N well 110 is connected to ground (V_DNW=0 V) while the P well 120 may be floating or connected to ground (V_PW=0 V or floating);
- (v) all the bit lines BL and unselected source lines SL are floating or connected to ground; and
- (vi) the selected source line voltage V_SLis ramped up, preferred to be through a current limiter to prevent overloading the source line voltage supply circuit, until a sudden increase in current A and a sudden drop in voltage across the second gate dielectric layer OX₂, indicating dielectric breakdown B, in FIG. 7 , directly on the second source region S₂of the selected data storage transistor T_DS.

Alternatively, the dielectric breakdown B may be caused by simply applying a pre-set source line voltage V_SLthat is higher than gate dielectric breakdown voltage (i.e., portion 206 of OX₂breakdown voltage), to the selected source line, which is also preferred to be through a current limiter to prevent overloading the source line voltage supply circuit.
It is another technical feature of the invention that to write digital “0”, only the portion 206 of the second gate dielectric layer OX₂that is adjacent to the second source region S₂(i.e. source side dielectric) is ruptured, while the portion 204 of the second gate dielectric layer OX₂that is adjacent to the second drain region D₂(i.e. drain side dielectric) and the portion 202 directly over the channel region CH (i.e. channel dielectric) are remained intact.
Please refer to Table 3 below, FIG. 8 and FIG. 9 . FIG. 8 is a cross section of the data storage transistor T_DSwith “1” state during read operation. FIG. 9 is a cross section of the data storage transistor T_DSwith “0” state during read operation. Table 3 shows exemplary bias conditions for reading data storage transistor T_DS.
To read a memory cell, the following exemplary bias conditions may be implemented:

- (i) all the program select lines P sel are connected to ground (0 V) to turn off all program select transistors T_PSso that all the second gates G₂of the data storage transistors T_DSare isolated from the outside bias. Therefore, voltage of the second gate G₂of the data storage transistors T_DSis the same as that of second drain region D₂if the dielectric breakdown B, caused during the programming procedure, is on the drain side, and the same as that of second source region S₂if the dielectric breakdown B is on the source side;
- (ii) a read select voltage V_Rselof about 1-3V is applied to the selected read select lines R_selso that drain of the selected data storage transistors T_DSis connected to the selected bit line BL to which a bit line voltage V_BLof 0.5-2V is applied; and
- (iii) all the other terminals are connected to ground (0 V).

TABLE 3

Read Bias Condition

	Terminal	Bias Voltage

	All P_Sel	0 V
	Selected R_Sel	1-3 V
	Unselected R_Sel,	0 V
	Selected BL	0.5-2 V
	Unselected BL	0 V or Floating
	All SL	0 V
	P-Well	0 V
	Others	0 V

Under the aforesaid read bias conditions, the data storage transistors T_DShas a high channel current CL if the dielectric breakdown B is on the drain side because the gate voltage is high, same as the voltage applied to the second drain region D₂, and the data storage transistors T_DS(“1” state) is turned on, as shown in FIG. 8 . On the other hand, for the data storage transistors T_DSin “0” state, there is no channel current (or only an insignificant amount of off-current) because the voltage coupled to the second gate G₂is low, same as the voltage applied to the second source region S₂, and the data storage transistors T_DS(“0” state) is turned off, as shown in FIG. 9 . Therefore, the read current path is not through the ruptured dielectric, but is through the channel region CH of the data storage transistor T_DS.
According to some embodiments, all the isolated second gates G₂of the data storage transistors T_DSmay be pre-charged by turning on all read select transistors T_Rsimultaneously and applying 0.5-2V to all bit lines and 0 V to all source line for a short period of time (e.g., 3 ms) prior to reading the entire OTP memory array. This can prevent those soft breakdown bits from errors due to slow charging.
FIG. 10 to FIG. 17 are schematic diagrams showing an exemplary method for fabricating a MOS transistor having lower gate-to-source/drain breakdown voltage according to one embodiment of the invention, wherein like layers, elements or regions are designated by like numeral numbers or labels.
As shown in FIG. 10 , a semiconductor substrate 100 such as a P type silicon substrate is provided. A gate dielectric layer 200 such as silicon dioxide (SiO₂), silicon oxynitride (SiON) or hafnium dioxide (HfO₂), or the combination of two or more is deposited on the semiconductor substrate 100. According to one embodiment, the gate dielectric layer 200 may have a thickness of about 2-20 nm, but is not limited thereto. A first conductive layer 210 a such as N-doped polysilicon, silicide or metal is then deposited on the gate dielectric layer 200. For example, the first conductive layer 210 a is an N-doped polysilicon layer. According to one embodiment, the first conductive layer 210 a may have a thickness of about 80-200 nm, but is not limited thereto. Optionally, a cap nitride layer 230 may be deposited on the first conductive layer 210 a. For example, the cap nitride layer 230 may be a silicon nitride layer and may have a thickness of about 5-10 nm.
It will be appreciated that although some conductivity types have been used for illustrative purposes, the invention may be practiced with opposite conductivity types.
Subsequently, as shown in FIG. 11 , a photoresist pattern PR is formed on the cap nitride layer 230 to define gate area. An anisotropic etching process 500 is then performed to remove the cap nitride layer 230 and the first conductive layer 210 a not covered by the photoresist pattern PR, thereby forming a main gate portion 212. At this point, the gate dielectric layer 200 is substantially not etched.
As shown in FIG. 12 , the remaining photoresist pattern PR is removed. An ion implantation process 600 is then performed to implant N type dopants into the semiconductor substrate 100, thereby forming N⁺ drain region 104 and N⁺ source region 106. According to one embodiment, the N⁺ drain region 104 and N⁺ source region 106 may be formed with graded junction, which may be formed by using, for example, doubly diffused method, for higher junction breakdown voltage.
As shown in FIG. 13 , an etching process is performed to remove an upper portion of the gate dielectric layer 200, thereby forming a thinner portions 204 and 206 on the N⁺ drain region 104 and N⁺ source region 106, respectively. The portions 204 and 206 may be thinned down to thickness of 30-70% of the original thickness. According to one embodiment, the etching process may be a wet etching process, but is not limited thereto. It is understood that in some embodiments the ion implantation process 600 in FIG. 12 may be performed after gate dielectric thinning down.
As shown in FIG. 14 , a second conductive layer 210 b such as N-doped polysilicon, silicide or metal is deposited on the semiconductor substrate 100. The second conductive layer 210 b conformally covers the main gate portion 212 and the thinner portions 204 and 206. The second conductive layer 210 b is in direct contact with the sidewalls of the main gate portion 212. For example, the second conductive layer 210 b is an N-doped polysilicon layer. According to one embodiment, the second conductive layer 210 b may have a thickness of about 20-100 nm.
As shown in FIG. 15 , an anisotropic etching process 700 is then performed to etch the second conductive layer 210 b, thereby forming extension gate portions 214 and 216 on the opposite sidewalls of the main gate portion 212. The extension gate portion 214 is situated directly on the portion 204 of the gate dielectric layer 200 and the extension gate portion 216 of the gate electrode 210 is situated directly on the portion 206 of the gate dielectric layer 200.
As shown in FIG. 16 , the cap nitride layer 230 is removed, optionally. After the removal of the cap nitride layer 230, the top surface of the main gate portion 212 is revealed. Subsequently, a dielectric spacer 224 and a dielectric spacer 226 are formed on the gate dielectric layer 200 and the extension gate portions 214 and 216 of the gate electrode 210, respectively. Removal of cap nitride layer 230 can also be achieved during formation of spacer 224 and spacer 226. The formation of the dielectric spacers 224 and 226 may involve conformal deposition of a spacer material layer and anisotropic etch of the spacer material layer. In some embodiments, the cap nitride layer 230 is not removed prior to the conformal deposition of the spacer material layer, and the cap nitride layer 230 can be removed during anisotropic etch of the spacer material layer.
The outer surface of the extension gate portion 214 of the gate electrode 210 is covered with the dielectric spacer 224 and the outer surface of the extension gate portion 216 of the gate electrode 210 is covered with the dielectric spacer 226. According to one embodiment of the invention, for example, the dielectric spacers 224 and 226 may comprise silicon nitride, silicon oxynitride or silicon oxide, but is not limited thereto. According to one embodiment of the invention, an end surface 204 a of the portion 204 is aligned with an outer surface of the dielectric spacer 224 and an end surface 206 a of the portion 206 is aligned with an outer surface of the dielectric spacer 226.
A self-aligned silicidation process is then performed to form a salicide layer 232 on the gate electrode 210, a salicide layer 234 on the drain region 104, and a salicide layer 236 on the source region 106. According to one embodiment of the invention, salicide layers 232, 234 and 236 may comprise NiSi, CoSi, TiSi, or WSi, but is not limited thereto. According to one embodiment of the invention, the salicide layer 234 is contiguous with the end surface 204 a of the portion 204, and the salicide layer 236 is contiguous with the end surface 206 a of the portion 206. According to one embodiment of the invention, the salicide layer 234 is not in direct contact with the dielectric spacer 224, and salicide layer 236 is not in direct contact with the dielectric spacer 226.
According to one embodiment of the invention, the vertical PN junctions 104 a and 106 a proximate to the top surface of the semiconductor substrate 100 are situated directly underneath the main gate portion 212 of the gate electrode 210. By providing such configuration, a higher gated source/drain junction breakdown voltage can be provided. According to one embodiment of the invention, the MOS transistor T has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and the gated source/drain junction breakdown voltage.
As shown in FIG. 17 , an interlayer dielectric (ILD) layer 240 is then deposited on the semiconductor substrate 100. The ILD layer 240 covers the MOS transistor T. Subsequently, a contact plug 244 and a contact plug 246 may be formed in the ILD layer 240. An interconnect structure 254 and an interconnect structure 256 may be formed on the ILD layer 240. The interconnect structure 254 is electrically connected to the drain region 104 through the contact plug 244. The interconnect structure 256 is electrically connected to the source region 106 through the contact plug 246.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

What is claimed is:

1. A one-time programmable memory unit cell, comprising:

a substrate comprising thereon a first active area and a second active area isolated from the first active area;

a read select transistor disposed on the first active area, wherein the read select transistor comprises a first gate, a first gate dielectric layer between the first gate and the substrate, a first drain region in the substrate on one side of the first gate, and a first source region in the substrate on an opposing side of the first gate;

a data storage transistor disposed on the first active area and serially connected to the read select transistor, wherein the data storage transistor comprises a second gate, a second gate dielectric layer between the second gate and the substrate, a second drain region in the substrate on one side of the second gate, a second source region in the substrate on an opposing side of the second gate, and a channel region between the second drain region and the second source region, wherein the second drain region merges with the first source region of the read select transistor, wherein the second gate comprises a main gate portion directly above the channel region, a first extension gate portion and a second extension gate portion on two opposite sidewalls of the main gate portion, respectively, wherein the main gate portion, the first extension gate portion and the second extension gate portion constitute a gate electrode of the data storage transistor, and wherein the second gate dielectric layer comprises a first portion between the drain region and the first extension gate portion, a second portion between the channel region and the main gate portion, and a third portion between the source region and the second extension gate portion, wherein the first portion and the third portion are thinner than the second portion; and

a program select transistor disposed on the second active area, wherein the program select transistor comprises a third gate, a third gate dielectric layer between the third gate and the substrate, a third drain region in the substrate on one side of the third gate, and a third source region in the substrate on the other side of the third gate, wherein the third drain region is electrically coupled to the second gate of the data storage transistor.

2. The one-time programmable memory unit cell according to claim 1 further comprising:

a first dielectric spacer and a second dielectric spacer on the first extension gate portion and the second extension gate portion, respectively.

3. The one-time programmable memory unit cell according to claim 2, wherein the first dielectric spacer and the second dielectric spacer are situated directly on the first portion and the third portion of the gate dielectric layer, respectively.

4. The one-time programmable memory unit cell according to claim 1, wherein the first extension gate portion of the gate electrode is situated directly on the first portion of the gate dielectric layer and the second extension gate portion of the gate electrode is situated directly on the third portion of the gate dielectric layer.

5. The one-time programmable memory unit cell according to claim 1 further comprising:

a first vertical PN junction disposed between the drain region and the channel region and proximate to a top surface of the substrate, wherein the first vertical PN junction is situated directly underneath the main gate portion of the gate electrode; and

a second vertical PN junction disposed between the source region and the channel region and proximate to the top surface of the substrate, wherein the second vertical PN junction is situated directly underneath the main gate portion of the gate electrode.

6. The one-time programmable memory unit cell according to claim 1, wherein the first gate, the second gate, and the third gate comprise a single polysilicon layer or a metal gate.

7. The one-time programmable memory unit cell according to claim 1, wherein the data storage transistor has a gate-to-source/drain breakdown voltage lower than a gate-to-channel breakdown voltage and a gated source/drain junction breakdown voltage.

8. The one-time programmable memory unit cell according to claim 1, wherein the substrate is a P type silicon substrate, wherein the first drain region, the first source region, the second drain region, the second source region, the third drain region, and the third source region are N⁺ doping regions.

9. The one-time programmable memory unit cell according to claim 8, wherein the program select transistor is constructed on a triple well structure comprising a deep N well in the P type silicon substrate and a P well isolated from the P type silicon substrate by the deep N well.

10. The one-time programmable memory unit cell according to claim 1, wherein the substrate comprises a silicon-on-insulator (SOI) substrate.

11. The one-time programmable memory unit cell according to claim 1, wherein the third source region is electrically coupled to ground.

12. The one-time programmable memory unit cell according to claim 1, wherein the second active area is disposed in close proximately to the first active area.