CN115101478A - Anti-fuse unit, anti-fuse memory device and method of manufacturing the same - Google Patents
Anti-fuse unit, anti-fuse memory device and method of manufacturing the same Download PDFInfo
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- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
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Abstract
The invention provides an anti-fuse unit, an anti-fuse memory device and a manufacturing method thereof, wherein the manufacturing method of the anti-fuse memory device comprises the following steps: providing a substrate; forming an anti-fuse grid structure on the first well region; forming a patterned mask layer to cover the anti-fuse grid structure and the first well regions on two sides of the anti-fuse grid structure; performing a lightly doped ion implantation process; and removing the first mask layer, and executing a source-drain ion implantation process to form source-drain doped regions in the first well regions on two sides of the anti-fuse gate structure, wherein the source-drain doped regions on two sides of the anti-fuse gate structure are penetrated in the first well regions. In the invention, the source-drain doped regions are directly formed by not forming the source-drain lightly doped regions in the well regions at the two sides of the anti-fuse gate structure, and the source-drain doped regions are utilized to form punch-through to increase reading current, so that the defects caused by smaller reading current are reduced, the manufacturing yield is improved, and compared with other solutions, the anti-fuse gate structure has the effects of simplicity, practicability and low cost.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to an antifuse cell, an antifuse memory device, and methods of manufacturing the same.
Background
Memory devices can be generally classified into volatile memory devices and nonvolatile memory devices. The nonvolatile memory device may be further classified into a Read Only Memory (ROM), a one-time programmable memory (OTP memory), and a rewritable memory. Among them, the otp memory can be classified into a fuse type (fuse type) and an antifuse type (anti-fuse type).
Antifuse memory devices are widely used for their preferred performance, and their small memory cells are usually composed of an antifuse cell and a select transistor. The operating principle of the antifuse memory is to store data 1 or 0 depending on whether the antifuse gate dielectric layer is broken down.
Specifically, as shown in fig. 1, a storage region 10a ' and a logic region 10b ' are disposed on a substrate 10 ', an anti-fuse unit 21 ' and a selection tube 22 ' connected in series are formed on a well region of the storage region 10a ', and a logic unit 23 ' is formed on a well region of the logic region 10b ', where the anti-fuse unit 21 ', the selection tube 22 ' and the logic unit 23 ' are standard transistors with different specifications, taking the anti-fuse unit 21 ' as an example, a gate structure of the anti-fuse unit 21 ' is located on the well region, and a source-drain doped region 43 ', a source-drain lightly doped region 41 ' and a pocket injection region 42 ' are disposed in the well region on both sides of the gate structure of the anti-fuse unit 21 '.
However, the above-described antifuse memory has a problem that yield is reduced due to a defect that a read current is small, and a conventional solution to this problem is costly, thereby seriously affecting market competitiveness of the antifuse memory device.
Disclosure of Invention
An object of the present invention is to provide an antifuse cell, an antifuse memory device, and a method of manufacturing the same, which solve the disadvantages caused by a small read current at a low cost.
To solve the above technical problem, the present invention provides a method for manufacturing an antifuse memory device, comprising: providing a substrate, wherein the substrate comprises a storage area with a first well region and a logic area with a second well region;
forming an anti-fuse grid structure on the first well region, and forming a logic grid structure on the second well region;
forming a patterned mask layer, wherein the patterned mask layer covers the anti-fuse grid structure and the first well regions on two sides of the anti-fuse grid structure;
performing a light doping ion implantation process to form source and drain light doping regions in the second well regions on two sides of the logic gate structure;
and removing the patterned mask layer, and executing a source-drain ion implantation process to form source-drain doped regions in the first well regions on two sides of the anti-fuse gate structure, wherein the source-drain doped regions on two sides of the anti-fuse gate structure form punch-through in the first well region.
Optionally, the lightly doped ion implantation process includes lightly doped ion implantation in a direction perpendicular to the surface of the substrate and lightly doped ion implantation in a direction oblique to the surface of the substrate.
Optionally, after removing the patterned mask layer and before performing the source-drain ion implantation process, a sidewall structure is formed on sidewalls of the antifuse gate structure and the logic gate structure.
Optionally, the width of the antifuse gate structure is smaller than the width of the logic gate structure.
Optionally, the width of the antifuse gate structure is less than or equal to 0.12 microns.
Optionally, a selection pipe gate structure is further formed on the storage region, and a width of the selection pipe gate structure is greater than a width of the antifuse gate structure.
Optionally, the lightly doped ion implantation process and the source-drain ion implantation process are performed on the first well regions on both sides of the select gate structure.
Optionally, the source-drain ion implantation process is performed on the first well regions on both sides of the select gate structure.
In accordance with another aspect of the present invention, there is also provided an antifuse memory device fabricated using the method of fabricating an antifuse memory device as described above.
Based on another aspect of the present invention, there is also provided an antifuse cell, comprising: the semiconductor device comprises a substrate, a first semiconductor layer and a second semiconductor layer, wherein a well region is arranged on the substrate; the anti-fuse grid structure is arranged on the well region; and the source-drain doped regions are positioned in the well regions at two sides of the anti-fuse gate structure, and the source-drain doped regions at two sides of the anti-fuse gate structure are penetrated in the first well region.
In summary, in the present invention, before the lightly doped ion implantation process, a patterned mask layer is formed to cover the antifuse gate structure and the first well regions on both sides of the antifuse gate structure, so that the first well regions on both sides of the antifuse gate structure do not form the source-drain lightly doped regions, and after the source-drain ion implantation process, the source-drain doped regions on both sides of the antifuse gate structure penetrate through the first well region under the antifuse gate structure, so that not only a large current can be easily formed in programming to improve the programming efficiency of the antifuse memory device, but also a read current is increased when data is readable, so that the process difficulty of the antifuse memory device in the read current aspect is correspondingly reduced under the same design standard, and further, defects caused by a smaller read current are reduced, thereby improving the yield. Meanwhile, compared with other solutions, the embodiment has the effects of simplicity, practicability and low cost.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention. Wherein:
FIG. 1 is a schematic diagram of a prior art antifuse memory device;
FIG. 2 is a flow chart of a method for fabricating an antifuse memory device according to an embodiment of the present application;
FIGS. 3a to 3e are schematic structural diagrams corresponding to a method for manufacturing an antifuse memory device according to an embodiment of the present invention;
fig. 4 is a flowchart of a method for manufacturing an antifuse memory device according to a second embodiment of the present application.
In fig. 1:
10' -a substrate; 10 a' -storage region; 10 b' -logic region; 21' -an antifuse cell; 22' -selection tube; 23' -logic gate cells; 41' -source drain lightly doped region; 42' -pocket implant region; 43' -source and drain doped regions.
In fig. 3a to 3 e:
10-a substrate; 10 a-a storage area; 10 b-logical area; 11-a first well region; 12-a second well region; 21-an antifuse gate structure; 21 a-an antifuse gate dielectric layer; 21 b-antifuse control gate layer; 22-select gate structure; 22 a-selecting a tube gate dielectric layer; 22 b-select tube control gate layer; 23-a logic gate structure; 23 a-logic gate dielectric layer; 23 b-a logic control gate layer; 31 — a first mask layer; 41-a first source drain lightly doped region; 42-a second source drain lightly doped region; 43-source drain doped region; 44-side wall structure; 45-the punch-through area.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, features defined as "first," "second," and "third" may explicitly or implicitly include one or at least two of the features unless the content clearly dictates otherwise.
Example one
Fig. 2 is a flowchart of a method for manufacturing an antifuse memory device according to an embodiment of the present disclosure.
As shown in fig. 1, a method for manufacturing an antifuse memory device according to one embodiment includes:
s01: providing a substrate, wherein the substrate comprises a storage area with a first well region and a logic area with a second well region;
s02: forming an anti-fuse grid structure and a selection pipe grid structure on the first well region, and forming a logic grid structure on the second well region;
s03: forming a first mask layer, wherein the first mask layer covers the anti-fuse grid structure and the first well regions on two sides of the anti-fuse grid structure;
s04: executing a light doping ion implantation process to form source drain light doping areas in the first well areas on two sides of the selection tube gate structure and the second well areas on two sides of the logic gate structure; and the number of the first and second groups,
s05: and removing the first mask layer, and executing a source-drain ion implantation process to form source-drain doped regions in the first well regions on two sides of the anti-fuse gate structure, wherein the source-drain doped regions on two sides of the anti-fuse gate structure are penetrated in the first well regions.
Fig. 3a to 3d are schematic structural diagrams corresponding to corresponding steps of a method for manufacturing an antifuse memory device according to an embodiment of the present invention, and the method for manufacturing an antifuse memory device according to the embodiment will be described in detail with reference to fig. 3a to 3 d.
Referring to fig. 3a, step S01 is executed to provide a substrate 10, in which the substrate 10 includes a storage region 10a having a first well region 11 and a logic region 10b having a second well region.
The substrate 10 may be any suitable semiconductor substrate 10, such as a silicon-based semiconductor or a silicon-on-insulator (SOI) substrate 10. An epitaxial layer may also be formed on the surface of the substrate 10, and subsequent device structures are formed in the epitaxial layer. A memory region 10a and a logic region 10b defined by an isolation structure (e.g., STI structure) are formed on the substrate 10, the memory region 10a is used to form an antifuse memory cell, and the logic region 10b is used to form a logic cell. A first well region 11 formed by ion implantation is formed in the storage region 10a, and a second well region 12 formed by ion implantation is formed in the logic region 10b, and the conductivity type of the well region is opposite to that of the source-drain structure of the transistor (including the antifuse unit, the select transistor, and the logic unit) to form electrical isolation.
In this embodiment, taking the substrate 10 as a silicon substrate and the transistors as NMOS transistors as an example, the doping types of the substrate 10 and the epitaxial layer are both P-type, and the conductivity types of the first WELL region 11 and the second WELL region 12 are the same and are both P-type (P-WELL).
Referring to fig. 3b, step S02 is executed to form an antifuse gate structure 21 and a select transistor gate structure 22 over the first well region 11 of the logic region 10b, and form a logic gate structure 23 over the second well region 12 of the logic region 10 b.
Gate structures corresponding to the transistors are formed on the first well region 11 and the second well region 12, the gate structures include a gate dielectric layer and a gate conductive layer on the gate dielectric layer, for example, an antifuse gate structure 21 and a select gate structure 22 are formed on the first well region 11, and a logic gate structure 23 is formed on the second well region 12. The antifuse gate structure 21 includes an antifuse gate dielectric layer 21a and an antifuse control gate layer 21b, the selection transistor gate structure 22 includes a selection transistor gate dielectric layer 22a and a selection transistor control gate layer 22b, and the logic gate structure 23 includes a logic gate dielectric layer 23a and a logic control gate layer 23 b.
Moreover, the gate structure may have different parameters according to design (e.g., operating voltage) requirements, such as the length of the conductive channel under the gate structure (the width of the gate structure) and the thickness of the gate dielectric layer. In the embodiment, the antifuse gate structure 21 may be a low voltage cell (lower than 3.3V), the selection pipe gate structure 22 may be a high voltage cell (greater than 3.3V), and the logic gate structure 23 may be a low voltage cell, and accordingly, the width of the antifuse gate structure 21 is smaller than that of the selection pipe gate structure 22, and the thickness of the antifuse gate dielectric layer 21a is smaller than that of the selection pipe gate dielectric layer 22 a. Those skilled in the art know the formation method of the gate structure of the transistor, and the detailed description thereof is omitted here.
Referring to fig. 3c, step S03 is performed to form a first mask layer 31, wherein the first mask layer 31 covers the anti-fuse gate structure 21 and the first well 11 on both sides of the anti-fuse gate structure 21.
The first mask layer 31 may be any mask layer suitable for serving as an ion implantation barrier layer, and may have a single layer structure or at least two layers, and may further include an amorphous carbon layer, a silicon oxide layer, or the like in addition to a photoresist layer. The first mask layer 31 (patterned mask layer) covers the anti-fuse gate structure 21 and the first well region 11 on two sides of the anti-fuse gate structure 21, and is used for preventing the covered region from being ion-implanted in the source-drain lightly doped ion implantation process.
As shown in fig. 3c, the anti-fuse gate structure 21 is adjacent to (connected to) the select transistor gate structure 22, the first well region 11 at two sides of the anti-fuse gate structure 21 may include a first region and a second region, the first well region 11 at a side of the anti-fuse gate structure 21 away from the select transistor gate structure 22 may be the first region, and the first well region 11 at a side of the anti-fuse gate structure 21 close to the select transistor gate structure 22 may be the second region, that is, the second region is a connection region (common region) between the anti-fuse gate structure 21 and the select transistor gate structure 22. The first mask layer 31 covers the first region and the anti-fuse gate structure 21, and extends to cover a portion of the second region, so as to perform a source-drain lightly doped ion implantation process on the select transistor. The dimension or proportion of the first masking layer 31 covering the second region can be calculated accordingly according to the design parameters of the selected tube, and in this embodiment, the first masking layer 31 can cover, for example, to an intermediate position of the second region.
Referring to fig. 3d, step S04 is performed to perform a lightly doped ion implantation process using the first mask layer 31 as a mask to form source and drain lightly doped regions (LDD) in the first well region 11 at two sides of the select gate structure 22 and the second well region 12 at two sides of the logic gate structure 23.
Preferably, the lightly doped ion implantation process may include lightly doped ion implantation in a direction perpendicular to the substrate surface and lightly doped ion implantation in a direction inclined to the substrate surface, the first source/drain lightly doped regions 41 with a certain depth (relatively shallow) may be formed in the first well region 11 and a portion of the second well region 12 on both sides of the selection gate structure 22 and both sides of the logic gate structure 23 by the lightly doped ion implantation in the direction perpendicular to the substrate surface, and the second source/drain lightly doped regions 42 (pocket implantation regions) may be formed in the first well region 11 and a portion of the second well region 12 on both sides of the selection gate structure 22 and under the logic gate structure 23 by the lightly doped ion implantation in the direction inclined to the substrate surface. The ion implantation type of the lightly doped ion implantation process is opposite to that of the corresponding well region, and the ion concentration of the first source drain lightly doped region 41 and the second source drain lightly doped region 42 is lower than that of the corresponding well region. It is understood that due to the existence of the first mask layer 31, the first well region 11 (including the first region and the second region) on both sides of the anti-fuse gate structure 21 does not form a source/drain lightly doped region.
Referring to fig. 3e, step S05 is performed to remove the first mask layer 31 and perform a source/drain ion implantation process to form source/drain doped regions 43 in the first well region 11 at two sides of the anti-fuse gate structure 21, where the source/drain doped regions 43 form a punch-through in the first well region 11 under the anti-fuse gate structure 21.
The specific forming process may include, for example: first, removing the first mask layer 31, then, forming a sidewall structure 44 on the sidewall of the gate structure (including the anti-fuse gate structure 21, the select gate structure 22 and the logic gate structure 23), and then, performing a source-drain ion implantation process on the substrate 10 to form a source-drain doped region 43 of each transistor; then, an annealing process is performed.
The sidewall structure 44 may be a single-layer ON structure or a multi-layer ON structure, and the ON structure may be a silicon oxide layer and a silicon nitride layer. The conductivity type of the doped ions in the source-drain ion implantation process is opposite to that of the corresponding well region, and the ion implantation concentration is higher and the depth is deeper (the junction depth is deeper than the depth of the first source-drain lightly doped region 41). Taking the first well region 11 and the second well region 12 in this embodiment as P-type as an example, the source-drain ion implantation process may be performed in the storage region 10a and the logic region 10b synchronously, and the ion type of the source-drain ion implantation process is N-type. The annealing process may be a rapid thermal annealing process or a laser annealing process, etc.
It should be noted that, in this embodiment, since the source/drain lightly doped regions are not formed under the anti-fuse gate structure 21, the source-drain doped regions 43 on both sides of the anti-fuse gate structure 21 are made to communicate with the depletion layer of the first well region 11 of the anti-fuse gate structure 21 to form punch-through, i.e., the conductive channel under antifuse gate structure 21, forms a punch-through region 45, which makes it easier to form a high current breakdown antifuse gate dielectric layer 21a, to improve the programming efficiency of the antifuse memory device and, more importantly, to increase the read current when data is readable, therefore, the process difficulty of the anti-fuse memory device is correspondingly reduced under the same design standard (specification requirement), the fault tolerance rate of the anti-fuse memory device is improved, and the defects caused by smaller read current are further reduced, so that the yield is improved. In addition, the PN junction formed by the source-drain doped region 43 and the first well region 11 can also be used to prevent current leakage from the substrate, thereby reducing current.
Preferably, the length of the conductive channel of the anti-fuse unit (the width of the anti-fuse gate structure) is also reduced as much as possible when the design allows, for example, the width of the anti-fuse gate structure is at least smaller than that of the logic gate structure, so that the source and drain of the anti-fuse unit can be penetrated by using the short channel effect while the source and drain of the logic unit are prevented from being penetrated. In a specific embodiment, when the width of the antifuse gate structure is less than or equal to 0.12 μm, a source-drain ion implantation process is performed on the antifuse cell, so that a source-drain punch-through of the antifuse cell can be formed.
Example two
Fig. 4 is a flowchart of a method for manufacturing an antifuse memory device according to a second embodiment of the present application.
As shown in fig. 4, the method for manufacturing an antifuse memory device according to the present embodiment includes:
s01: providing a substrate, wherein the substrate comprises a storage area with a first well region and a logic area with a second well region;
s02: forming an anti-fuse grid structure and a selection pipe grid structure on the first well region of the logic region, and forming a logic grid structure on the second well region of the logic region;
s03: forming a second mask layer, the second mask layer covering the storage region;
s04: executing a light doping ion implantation process to form a source-drain light doping area in a second well area of the logic gate structure;
s05: and removing the second mask layer, and executing a source-drain ion implantation process to form source-drain doped regions in the first well regions on two sides of the anti-fuse gate structure, wherein the source-drain doped regions on two sides of the anti-fuse gate structure are penetrated in the first well regions.
The manufacturing method provided by this embodiment is substantially the same as the manufacturing method provided by the first embodiment, and only differs in step S03. In this embodiment, the second mask plate covers the entire storage region, including the antifuse gate structure, the selection transistor gate structure, and the first well regions on both sides of the antifuse gate structure and the selection transistor gate structure, so that a source-drain lightly doped region is not formed in the first well regions on both sides of the antifuse gate structure and the selection transistor gate structure. Therefore, the source-drain doped regions on two sides of the anti-fuse grid structure are communicated with the depletion layer of the first well region to form punch-through. It should be understood that, due to the fact that the channel length of the selection tube is large, even if the source and drain lightly doped regions are not formed in the first well region on the two sides of the gate structure of the selection tube, the source and drain doped regions of the selection tube cannot be penetrated through.
EXAMPLE III
The third embodiment provides an antifuse memory device fabricated using the method of fabricating an antifuse memory device as described above. The anti-fuse memory device comprises a storage region and a logic region, wherein an anti-fuse unit and a selection tube are formed on the storage region, a logic unit is formed on the logic region, and a source-drain doped region (a source-drain structure) of the anti-fuse unit is penetrated in a channel below a gate structure of the anti-fuse unit so as to increase the reading current of the anti-fuse unit.
Example four
In a fourth embodiment, an antifuse cell is provided, where the antifuse cell includes a substrate, an antifuse gate structure, and a source-drain doped region. The substrate is provided with a well region, the anti-fuse grid structure is arranged on the well region, the source-drain doped regions are positioned in the well region on two sides of the anti-fuse grid structure, and the source-drain doped regions of the anti-fuse unit form punch-through in the well region under the anti-fuse grid structure.
In summary, in the present invention, before the lightly doped ion implantation process, a patterned mask layer is formed to cover the antifuse gate structure and the first well regions on both sides of the antifuse gate structure, so that the first well regions on both sides of the antifuse gate structure do not form the source-drain lightly doped regions, and after the source-drain ion implantation process, the source-drain doped regions on both sides of the antifuse gate structure penetrate through the first well region under the antifuse gate structure, so that not only a large current can be easily formed in programming to improve the programming efficiency of the antifuse memory device, but also a read current is increased when data is readable, so that the process difficulty of the antifuse memory device in the read current aspect is correspondingly reduced under the same design standard, and further, defects caused by a smaller read current are reduced, thereby improving the yield. Meanwhile, compared with other solutions, the embodiment has the effects of simplicity, practicability and low cost.
The above description is only for the purpose of describing the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are intended to fall within the scope of the appended claims.
Claims (10)
1. A method of fabricating an antifuse memory device, comprising:
providing a substrate, wherein the substrate comprises a storage area with a first well region and a logic area with a second well region;
forming an anti-fuse grid structure on the first well region, and forming a logic grid structure on the second well region;
forming a graphical mask layer, wherein the graphical mask layer covers the anti-fuse grid structure and the first well regions on two sides of the anti-fuse grid structure;
performing a light doping ion implantation process to form source and drain light doping regions in the second well regions on two sides of the logic gate structure;
and removing the patterned mask layer, and executing a source-drain ion implantation process to form source-drain doped regions in the first well regions on two sides of the anti-fuse gate structure, wherein the source-drain doped regions on two sides of the anti-fuse gate structure form punch-through in the first well region.
2. The method of claim 1, wherein the lightly doped ion implantation process comprises lightly doped ion implantation in a direction perpendicular to a surface of the substrate and lightly doped ion implantation in a direction oblique to the surface of the substrate.
3. The method of claim 1, wherein a sidewall structure is formed on sidewalls of the antifuse gate structure and the logic gate structure after the patterned mask layer is removed and before the source-drain ion implantation process is performed.
4. The method of claim 1, wherein the antifuse gate structure has a width less than a width of the logic gate structure.
5. The method of claim 4, wherein the antifuse gate structure has a width less than or equal to 0.12 μm.
6. The method of any of claims 1-5, further comprising forming a select pipe gate structure over the memory region, wherein the select pipe gate structure has a width greater than a width of the antifuse gate structure.
7. The method of claim 6, wherein the lightly doped ion implantation and the source/drain ion implantation are performed on the first well regions on both sides of the select gate structure.
8. The method of claim 6, wherein the source and drain ion implantation is performed on the first well regions on both sides of the select gate structure.
9. An antifuse memory device manufactured using the method of manufacturing an antifuse memory device according to any one of claims 1 to 8.
10. An antifuse cell, comprising:
the semiconductor device comprises a substrate, a first semiconductor layer and a second semiconductor layer, wherein a well region is arranged on the substrate;
the anti-fuse grid structure is arranged on the well region;
and the source-drain doped regions are positioned in the well regions at two sides of the anti-fuse gate structure, and the source-drain doped regions at two sides of the anti-fuse gate structure are penetrated in the first well region.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115332257A (en) * | 2022-10-13 | 2022-11-11 | 长鑫存储技术有限公司 | Anti-fuse unit and anti-fuse array |
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| CN115332257A (en) * | 2022-10-13 | 2022-11-11 | 长鑫存储技术有限公司 | Anti-fuse unit and anti-fuse array |
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