CN100582676C - Correction circuit for encoder signal - Google Patents

Abstract

An encoder signal correcting circuit with high position detecting precision can correct the phase error with simple arithmetic operating when the frequency of the two-phase sine signal is high. The position detector includes the following components: a peak detector which detects the peak value of the output signal of the AD transducer; an excursion/amplitude correcting circuit which corrects the error of the excursion and the vibration amplitude and generates (A2) signal and (B2) signal with the detected peak value; a phase error detector which detects the intersection value between the (A2) signal and the (B2) signal; a phase correcting circuit which calculates the correction coefficient of the (A2) signal and the (B2) signal; and a position data converting circuit which switches the sine signal of A phase and B phase to the position data, the position detector also is arranged with the following components: a speed detector which detects the speed with the frequency or position data of the A phase and B phase sine signals; and a correction judging circuit which switches the update of the correction value to the excursion, vibration amplitude and phase to be effective or ineffective.

Description

Correction circuit for encoder signal

technical field

The present invention relates to a circuit for correcting offset, amplitude, and phase of two-phase sinusoidal signals in an encoder for obtaining high resolution by interpolating two-phase sinusoidal signals in quadrature.

Background technique

Generally, the position detection of a rotary (or linear) encoder is formed by a light-emitting element, a light-receiving element, and a rotating body (or moving body) that forms a grid-like slit between them, and the resolution is determined by the grid-like The seam interval is determined. Therefore, the slit interval is reduced in order to improve the resolution, but there is a limit to the improvement of the resolution by this method because of the machining accuracy or the diffraction phenomenon of light.

Therefore, in recent years, the following method has been generally carried out: generating sinusoidal analog signals of A and B phases with a phase difference of 90 degrees synchronized with the signal between the slots of the rotating body (or moving body), and performing interpolation processing on the analog signals The final signal and the signal obtained through the above-mentioned slit are combined to improve the resolution.

In order to further increase the resolution of the encoder, it is necessary to increase the resolution of the interpolation process, that is, by increasing the resolution of an AD converter that converts an analog signal into a digital signal, the overall resolution can be increased. This AD converter can be built in a microcomputer (micro computer) or LSI, but the resolution of the built-in AD converter is 10bit, and the accuracy is generally poor. In order to further improve the resolution, a single AD converter is required. device IC.

There are parallel and serial methods for the interface between the AD converter IC and the microcomputer or LSI, but the serial method is more effective in terms of miniaturization and cost. However, the serial method has a problem that the sampling cycle of transmission data becomes longer. For example, when the sampling cycle of the AD converter is long, when the frequency of the two-phase sinusoidal signal increases, the number of detections per cycle decreases, and it is difficult to accurately perform the interpolation processing required to improve the accuracy of the interpolation process. Correction of offset, amplitude, and phase.

As a way to solve these problems, for example, in Japanese Patent Application Laid-Open No. 7-218288, a method is adopted in which the attenuation coefficient of the amplitude of the two-phase sinusoidal signal when the frequency becomes higher is stored in memory in advance, and the amplitude correction factor is changed. amount to compensate for attenuation. However, although this method can correct the attenuation of the 2-phase sinusoidal signal, if the sampling period becomes longer and the frequency of the 2-phase sinusoidal signal becomes higher, the maximum or minimum value cannot be detected correctly, and an error occurs in the correction value. .

10 is a diagram showing detection waveforms of maximum and minimum values when the frequency of two-phase sinusoidal signals is high, and FIG. 11 is a diagram showing waveforms of intersections of two-phase sinusoidal signals detected for detecting phase error amounts. When the frequency is high, the transformed sinusoidal signal becomes stepped as shown in Fig. 10 and Fig. 11 due to the influence of the long conversion sampling period of the AD converter 2, so it is difficult to correctly detect the maximum/minimum value and phase error.

In a state including the maximum value/minimum value and a phase error, the waveform corrected for the two-phase sinusoidal signal becomes a distorted waveform as shown in FIG. 12 . In the case of such a high frequency, even if the amplitude attenuation coefficient is corrected, errors occur in correction values of offset, amplitude, and phase, and the accuracy of interpolation processing deteriorates.

Contents of the invention

The encoder signal correction circuit of the present invention is used in an encoder signal processing circuit and has the following structure. The encoder signal processing circuit includes an AD converter, which converts the quadrature A-phase and B-phase sinusoidal signals into digital data, and generates A1 signals and B1 signals; a peak detector, which detects the maximum value and sum of the A1 signals and B1 signals Minimum value; offset/amplitude correction circuit, using the maximum value and minimum value detected by the peak detector, calculate the correction value of offset and amplitude, correct the offset and amplitude, generate A2 signal and B2 signal; phase error detection The device detects the phase error amount of the A2 signal and the B2 signal; the phase correction circuit calculates the phase correction value according to the phase error amount, and generates the A3 signal and the B3 signal whose phase difference becomes 90 degrees; the position data conversion circuit obtains the A3 signal from the A3 signal and B3 signals are converted into position data, and the correction circuit of the encoder signal includes: a speed detector, which detects the speed according to the frequency or position data of the A phase and the B phase; The update of the phase correction value is enabled or disabled.

In the speed detector, the speed is detected according to the difference between the detection frequency or position data of phase A and phase B. In the correction judgment circuit, when the speed exceeds the set speed once or several times in a row, it is judged to be high speed. When the number of consecutive times and more than the number of times judged as high speed is below the set speed, it is judged as low speed, and at the speed judged as high speed, the correction value of offset and amplitude, and the correction value of phase The update of the correction value of the offset and the amplitude and the correction value of the phase are made valid at the speed judged to be low.

According to the encoder signal correction circuit of the present invention, even if the offset, amplitude, and phase of the two-phase sinusoidal signal fluctuate due to aging changes, these offsets can be corrected with high precision, and the two-phase sinusoidal signal In the case of high frequency, the correction circuit of the encoder signal will not be affected by the sparse sampling period.

Description of drawings

Fig. 1 is a block diagram of an encoder circuit in a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of an operation waveform of the peak detector in the first embodiment.

3 is an explanatory diagram of an operation waveform of the phase error detector in the first embodiment.

FIG. 4 is an explanatory diagram of a result of interpolation processing of a sinusoidal signal when the correction determination circuit is not used when the number of samples in one cycle of the sinusoidal signal is 14. FIG.

FIG. 5 is an explanatory diagram of a result of interpolation processing on a sinusoidal signal when the number of samples in one cycle of the sinusoidal signal is 14 in the first embodiment.

Fig. 6 is a block diagram of an encoder circuit in the second embodiment.

FIG. 7 is an explanatory diagram of a method of the speed detector switching detection method of the second embodiment.

FIG. 8 is an explanatory diagram of an update cycle setting method in detection method 1 of the second embodiment.

Fig. 9 is a block diagram of an encoder circuit in a third embodiment.

FIG. 10 is an explanatory diagram of maximum/minimum values when detecting a high frequency in a conventional example.

FIG. 11 is an explanatory diagram of a phase error when detecting a high frequency in a conventional example.

FIG. 12 is an explanatory diagram of a sinusoidal signal waveform corrected in a state including errors in a conventional example.

Detailed ways

(first embodiment)

The encoder signal phase correction circuit of the present invention will be described using FIGS. 1 to 5 . 1 is a block diagram showing an encoder signal processing circuit including offset/amplitude correction and phase correction, FIG. 2 shows an operation waveform of a peak detector, and FIG. 3 shows an operation waveform of a phase error detector.

In FIG. 1 , the simulated A0 signal and B0 signal among the original signals output from the encoder are A-phase and B-phase sinusoidal signals having a phase difference of 90 degrees. Generally, it is composed of a light-emitting element, a light-receiving element and a slit plate.

LEDs or lasers are used as light-emitting elements, and photodiodes or phototransistors are used as light-receiving elements. The slit plate is made of glass or resin material that transmits light, and a grid-shaped mask that cuts off light is placed on the slit plate. The light-receiving element is configured so that the light from the light-emitting element passes through the slit plate. Since the slit plate is provided on the rotary body of the encoder, it is formed into a grid-like shape of the slit plate, so that when it is rotated from The light-receiving element outputs a sinusoidal waveform.

The AD converter 2 converts the analog signals A0 and B0 output from the encoder into digital signals. Since the amplitude of the analog signal output from the encoder is several hundreds of mV, it is amplified by an amplifier or the like by a factor of ten or so, converted into a voltage corresponding to the input range of the AD converter 2, and used to improve the accuracy of the digital signal.

The peak detector 15 detects the maximum value/minimum value of the A1 signal and the B1 signal which are the output signals of the AD converter 2 . FIG. 2 shows an operation waveform of the peak detector 15, and the method of detecting the maximum value/minimum value will be described using this figure.

In FIG. 2 , the |A1| signal and the |B1| signal are signals obtained by converting the absolute values of the A1 signal and the B1 signal, respectively. Intersection points of the |A1| signal and the |B1| signal are detected to generate intersection point signals 18a, 18b, 18c, and 18d. As shown in FIG. 2 , the intersection signal divides one period into Region I to Region IV. Region I is a region for detecting the maximum value of the A1 signal, and Region II is a region for detecting the minimum value of the B1 signal. , the region III is set to detect the minimum value of the A1 signal, and the region IV is set to detect the maximum value of the B1 signal.

The operation of the area I is described. First, when the intersection signal 18a is detected, the previous value and the current value of the A1 signal are compared. When the current value is large, the latch data 16a (max) is updated; The latch data 16a(max) is updated. This operation is repeated in the section of the area I, and when the intersection signal 18b is detected, the latch data 16a(max) is determined as the maximum value of the A1 signal. Since the operations of the area II, area III, and area IV are the same as those of the area I, they are omitted. In this way, the maximum value/minimum value of the A1 signal and the B1 signal can be detected.

The offset/amplitude correction circuit 4 uses the maximum value/minimum value signal 16 detected by the peak detector 15 to normalize the A1 signal and the B1 signal to remove the offset and the amplitude.

Using the maximum/minimum value signal 16, the offset (OS_DETa, OS_DETb) of the A1 signal and the B1 signal can be obtained according to Equation 1. In addition, if the corrected offset value is OS_LEVEL, and the offset-removed signal is A1d signal and B1d signal, then the offset can be removed according to Equation 2.

$\left.\begin{array}{c}\mathrm{Ald}=\mathrm{Al}-\mathrm{OS}\_\mathrm{DETa}+\mathrm{OS}\_\mathrm{LEVEL}\\ \mathrm{Bld}=\mathrm{Bl}-\mathrm{OS}\_\mathrm{DETb}+\mathrm{OS}\_\mathrm{LEVEL}\end{array}\right\}$ ...... (Formula 2)

Using the maximum/minimum value signal 16, the amplitude values (PP_DETa, PP_DETb) of the A1 signal and the B1 signal can also be obtained according to Equation 3. In addition, if the normalized magnitude of the amplitude is K, the A2 signal and the B2 signal whose offset and amplitude errors are corrected can be obtained according to Equation 4.

$\left.\begin{array}{c}A2=\mathrm{Ald}\&times;K/\mathrm{PP}\_\mathrm{<figure-callout\; id="2"\; label="DETa\; B"\; filenames="C2007101472040014H1.png,C2007101472040018H1.png"\; state="\{\{state\}\}">DETa</figure-callout>}& \\ B2=\mathrm{Bld}\&times;K/\mathrm{PP}\_\mathrm{DETb}\end{array}\right\}$ ...... (Formula 4)

The phase correction module 9 is made up of a phase correction circuit 6 and a phase error detector 7, and performs the following functions: the phase error of the A2 signal and the B2 signal that have been corrected for offset/amplitude is detected by the phase error detector 7, and the phase error is determined according to the phase error The error amount detected by the detector 7 is used by the phase correction circuit 6 to output the A3 signal and the B3 signal having a phase difference of 90 degrees using the A correction signal and the B correction signal for correcting the phase error of the A2 signal and the B2 signal.

The details of this operation are described using FIG. 3 . FIG. 3 is an example of a B2d signal in which the phase of only the B2 signal is advanced by α radians based on the A2 signal. The amplitude is normalized to K by the offset/amplitude correction circuit 4, so the amplitude of the A2 signal and the B2d signal becomes K.

The phase error detector 7 detects the size of the intersection of the A2 signal and the B2d signal when the intersection signals 18a, 18b, 18c, and 18d are detected, and calculates and derives the phase correction amount based on the intersection value. The A2 signal and the B2d signal can be expressed as in Equation 5. At this time, the intersection of the A2 signal and the B2d signal intersects at the (π/4-α/2) radian and (5π/4-α/2) radian, and the size of the intersection becomes Ksin(π/4-α/2 ), Ksin(5π/4-α/2).

Since they are equal in magnitude, the phase error α/2 can be obtained from Equation 6 when C45=Ksin(π/4-α/2) and C225=Ksin(5π/4-α/2). In addition, since Equation 6 calculates the B correction signal based on the A2 signal, it is calculated based on the formula of sin-1, but it is obvious that it can also be calculated based on the formula of cos ^-1 based on the B2d signal.

$\left.\begin{array}{c}A2=K\sin \mathrm{\&theta;}\\ B2d=K\cos (\mathrm{\&theta;}+\mathrm{\&alpha;})\end{array}\right\}$ ......(Formula 5)

$\left.\begin{array}{c}\mathrm{\&alpha;}/2=\mathrm{\&pi;}/4-{\sin }^{-1}(C45/K)\\ \mathrm{\&alpha;}/2=\mathrm{\&pi;}/4-{\sin }^{-1}(C225/K)\end{array}\right\}$ ...(Formula 6)

In addition, the phase correction circuit 6 can correct the phase error according to Equation 7 and Equation 8. Among them, Kp1 and Kp2 are phase correction gains for obtaining the A correction signal and the B correction signal, and the phase correction gains are set so that the phase difference between the A3 signal and the B3 signal becomes 90 degrees.

A3＝A2+Kp1·B2d＝Ksinθ+Kp1·Kcos(θ+α) ......(Formula 7)

B3＝B2d+Kp2·A2＝Kcos(θ+α)+Kp2·Ksinθ ......(Formula 8)

Next, a method of calculating Kp1 and Kp2 will be described. In Equation 7, when θ=-α/2, it is only necessary to make the A3 signal 0, so Kp1 can be obtained according to Equation 9.

$\left.\begin{array}{c}0=K\sin (-\mathrm{\&alpha;}/2)+\mathrm{<figure-callout\; id="1"\; label="Kp"\; filenames="C2007101472040018H1.png,C2007101472040019H2.png"\; state="\{\{state\}\}">Kp</figure-callout>}1\&Center\; Dot;K\cos (\mathrm{\&alpha;}/2)\\ \mathrm{<figure-callout\; id="1"\; label="Kp"\; filenames="C2007101472040018H1.png,C2007101472040019H2.png"\; state="\{\{state\}\}">Kp</figure-callout>}1=\mathrm{the\; tan}(\mathrm{\&alpha;}/2)\end{array}\right\}$ ...... (Formula 9)

In addition, in Equation 8 as well, when θ=π/2−α/2, it is only necessary to set B3 to 0, so Kp2 can be obtained from Equation 10.

$\left.\begin{array}{c}0=K\cos (\mathrm{\&pi;}/2+\mathrm{\&alpha;}/2)+\mathrm{<figure-callout\; id="2"\; label="Kp"\; filenames="C2007101472040014H1.png,C2007101472040018H1.png"\; state="\{\{state\}\}">Kp</figure-callout>}2\&Center\; Dot;K\sin (\mathrm{\&pi;}/2-\mathrm{\&alpha;}/2)\\ \mathrm{<figure-callout\; id="2"\; label="Kp"\; filenames="C2007101472040014H1.png,C2007101472040018H1.png"\; state="\{\{state\}\}">Kp</figure-callout>}2=\mathrm{the\; tan}(\mathrm{\&alpha;}/2)\end{array}\right\}$ ......(Formula 10)

Since Kp1 and Kp2 obtained from Equation 9 and Equation 10 can be represented by the same equation, the burden of calculation processing is reduced by half. The A2 signal and the B2 signal (B2d signal) can be obtained by calculating α/2 according to the formula 6, and the phase correction gain can be calculated according to the formula 9 or 10. By using the formula 7 and the formula 8, the A3 signal and the phase offset can be obtained by using the formula 8. B3 signal.

Next, the magnitudes of the phase-corrected A3 signal and B3 signal will be described. The maximum values of the amplitudes of Equation 7 and Equation 8 are the points of θ=π/2-α/2 and θ=-α/2 respectively, so if these are brought into Equation 7 and Equation 8, then A3 signal and B3 signal become Equation 11 and Equation 12 can be corrected with the same magnitude as shown in FIG. 3 . Since there are two intersection points in one cycle of the two-phase signal, Kp obtained at each intersection point may be averaged and used.

$\left.\begin{array}{c}A3=K\sin (\mathrm{\&pi;}/2-\mathrm{\&alpha;}/2)+\mathrm{Kp}\&Center\; Dot;K\cos (\mathrm{\&pi;}/2+\mathrm{\&alpha;}/2)\\ =K\cos (\mathrm{\&alpha;}/2)-\mathrm{Kp}\&Center\; Dot;K\sin (\mathrm{\&alpha;}/2)\end{array}\right\}$ ...... (Formula 11)

$\left.\begin{array}{c}B3=K\cos (\mathrm{\&alpha;}/2)+\mathrm{Kp}\&Center\; Dot;K\sin (-\mathrm{\&alpha;}/2)\\ =K\cos (\mathrm{\&alpha;}/2)-\mathrm{Kp}\&Center\; Dot;K\sin (\mathrm{\&alpha;}/2)\end{array}\right\}$ ......(Formula 12)

Next, the position data conversion circuit 10 will be described. Using the A3 signal and the B3 signal having a phase difference of 90 degrees, it can be easily converted into position data (interpolated angle data) θIP (14) using Equation 13.

θIP＝tan ^-1 (A3/B3)...(Formula 13)

Next, the correction value updating circuit 23 of the present invention will be described. The correction value update circuit 23 is composed of a speed detector 21 and a correction determination circuit 22 . The speed detector 21 outputs the detected speed 19 based on the frequency of the two-phase sinusoidal signal. The input sinusoidal signal A0 signal or B0 signal is compared with their respective central values and converted into a rectangular wave, and the time between the edges of the rectangular wave is measured by the counter to detect the cycle, and the frequency can be calculated according to the detected value. Also, the speed can be calculated and output according to the calculated frequency.

As another method, the position data 14 is sampled in a certain cycle, and the speed can be detected by taking a difference from the data at the time of the previous update every cycle. Correction determination circuit 22 first receives the detected speed 19 output from speed detector 21, and when the detected speed exceeds a certain set speed more than 2 consecutive times, it is judged to be high speed; If it is not exceeded more than once, it is judged as low speed.

Here, the number of times A determined to be high speed and the number B of times determined to be low speed are set to be different times, and the number of times A is set to 1 or more times, and the number of times B is set to be higher than the number of times A. In this way, it is possible to achieve a stable determination operation that prevents frequent switching between high speed and low speed near the set frequency.

In addition, the speed set here may have a hysteresis characteristic, and the speed for switching from high speed to low speed may be set lower than the speed for switching from low speed to high speed, so that a stable determination operation can be achieved.

Next, in order not to update the correction values of the offset, amplitude, and phase when the speed 19 is determined to be high speed, the correction value update signal 20 (for example, when the update of the correction value is disabled, L signal) is output to the peak detector 15 and the phase error detector 7.

In addition, in order to update the correction values of the offset, amplitude, and phase when it is determined that the speed is low, a correction value update signal 20 (for example, an H signal when the update of the correction value is enabled) is output. to peak detector 15 and phase error detector 7. The speed at which the correction value update signal is switched (the speed at which the speed is determined to be high or low) is set to a value at which the correction value can be accurately detected.

The standard of setting is that if the speed is set so that 72 divisions (sampling every 5 degrees) or more can be detected during one cycle of the two-phase sinusoidal signal, the error of the correction value can be suppressed to be small. When the 2-phase sinusoidal signal is likely to fluctuate due to the influence of temperature, power supply voltage, or noise, the position detection accuracy of the encoder will deteriorate, but the number of divisions (for example, sampling every 10 degrees) can be set smaller .

Figures 4 and 5 show the results of interpolation processing on 2-phase sinusoidal signals when the number of samples in one cycle of the sinusoidal signal is 14. In one cycle, the sampling of the AD converter 2 is 14 times.

FIG. 4 shows the case where there is no correction judgment circuit in the conventional method, and FIG. 5 shows waveforms when the correction judgment circuit of the present invention is provided and update of the correction value is disabled. In the conventional method, detection of the correction value cannot be performed normally, so the difference between samples varies, but it can be substantially constant in the method of the present invention.

As described above, with the circuit configuration and arithmetic processing of the first embodiment, even if the offset, amplitude, and phase of the two-phase sinusoidal signal fluctuate due to aging changes, these deviations can be corrected with high precision, and the two-phase When the frequency of the sinusoidal signal is high, it is a high-resolution encoder that will not be affected by the sparse sampling period.

(second embodiment)

A second embodiment of the present invention will be described using FIGS. 6 to 8 . The difference from the first embodiment is that the speed detection method is switched between low speed and high speed, which will be described in detail.

6 is a block diagram of the second embodiment, and the correction value determination circuit 22 outputs a speed determination signal 30 representing a state of high speed (for example, a high level signal)/low speed (for example, a low level signal) to the speed determination circuit 22 through the speed determination. detector 21.

7 is a diagram showing a method for switching the detection method by the speed detector. The speed determination signal 30 is judged to be high level (high speed) when the detection speed exceeds the set speed Vc for two or more consecutive speed update cycles. When it falls below Vc four times, it is judged as low level (low speed).

The speed detector uses the detection method 1 of sampling the position data 14 at a certain period during the period when the speed determination signal is at a low level, and detects the speed according to the difference between samples; The detection method 2 of the time detection speed of the edge interval of the rectangular wave generated by the B0 signal and the respective center values.

This is because the detection method 2 detects the speed by detecting the time interval between the edges of the A0 signal and the B0 signal, so the update cycle of the speed changes according to the frequency, and the update cycle becomes longer as the speed decreases, and the responsiveness of the speed determination signal However, in the detection method 1, the update cycle can be determined arbitrarily, and the update cycle is constant regardless of the speed. Therefore, by using the detection method 1 at low speeds, the speed determination signal at low speeds will not be lost. Responsiveness, a stable output is obtained.

Also, set the update cycle of detection method 1 so that the same speed as the update cycle of detection method 1 and detection method 2 becomes the set speed Vc, so that the responsiveness when switching from low speed to high speed and the speed when switching from high speed to low speed With the same responsiveness, a more stable speed judgment signal output can be obtained.

The setting method of the update period of detection method 1 is demonstrated using FIG. 8. FIG. The curve A-Ad in Fig. 8 shows that the update period of the detection method 2 is Tu2[s], when the speed is set to V[r/min], and the number of edges of the A0 signal and B0 signal in one rotation is set to P, it can be calculated according to Formula 14 to find out.

Tu2＝1/(V/60×P) ......(Formula 14)

The straight line B-Bd is the update period of detection method 1, and the update period is Tu1[s]. Tu1 is set according to Equation 15 so that the speed at the intersection point C of the curve A-Ad and the straight line B-Bd becomes the set speed Vc, so that the update cycle of detection method 1 and detection method 2 on Vc becomes the same cycle.

Tu1＝1/(Vc/60×P) ......(Formula 15)

As described above, by switching the speed detection method of the speed detector 21 of the second embodiment between low speed and high speed, a stable speed determination signal can be obtained, enabling or invalidating of the stable correction value can be switched more accurately, Therefore, it is possible to obtain a high-resolution encoder that is resistant to aging changes and is not affected by the sparseness of the sampling period when the frequency of the 2-phase sinusoidal signal is high.

(third embodiment)

A third embodiment of the present invention will be described using FIG. 9 . The difference from the second embodiment is that the correction determination circuit 22 has two types of set speeds for determination, and this will be described in detail.

The correction determination circuit 22 can individually set a signal to enable or disable updating of the correction value of the offset and amplitude, and the correction value of the phase. When the speed becomes higher, the frequency of the two-phase sinusoidal signals A0 and B0 becomes higher, and the sampling period of the AD converter 2 becomes longer, so the detection interval becomes thinner.

Since the A1 signal and the B1 signal of the two-phase sinusoidal signal detected by the peak detector 15 have little change in magnitude around the peak value, they are hardly affected by the sparseness of the sampling period. Therefore, in the correction determination circuit 22, the first setting speed for updating the correction value for determining the offset and the amplitude can be set relatively high.

For example, even with an offset of ±8 degrees, the peak is only attenuated by 1%. In a system where a 1% variation is allowable, the number of samples per cycle of the two-phase sinusoidal signal can be allowed up to a frequency of 22.5 (360/16). The phase correction value detects the intersection point of the A2 signal and the B2 signal of the two-phase sinusoidal signals, and when the value of the intersection point varies by 1%, the range of the angle becomes ±0.6 degrees. Therefore, in the correction determination circuit 22 , the second set speed for updating the correction value for determining the phase is set lower than the first set frequency.

As described above, by adopting two configurations in which the set speed in the correction determination circuit 22 of the third embodiment is separately set for offset and amplitude correction and for phase correction, it is possible to reduce the sinusoidal signal of two phases. Since the amplitude of the A0 signal and B0 signal fluctuates, it is possible to obtain a high-resolution encoder that is resistant to aging changes and is not affected by the sparseness of the sampling period when the frequency of the 2-phase sinusoidal signal is high.

(fourth embodiment)

A fourth embodiment of the present invention will be described. The difference from the first to third embodiments is that the correction determination circuit 22 is configured to determine which of the correction value of the offset and the amplitude correction value or the correction value of the phase is to be valid or invalid, and this is performed in detail. illustrate.

In a system in which the frequencies of the A0 signal and the B0 signal of the two-phase sinusoidal signals are low, as described above, amplitude fluctuations can be ignored, so there is no problem in always enabling the update of the offset and amplitude correction values. At this time, only whether the update of the correction value of the phase correction is enabled or disabled is detected.

In addition, in a linear scale or the like, there may be cases where the amount of phase shift is determined by the accuracy of the grid-shaped slit plate. In this case, the phase correction circuit 6 does not perform phase correction processing, but only performs the shift sum Amplitude correction is sufficient. The correction determination circuit 22 only needs to determine whether the update of the offset and amplitude correction values is valid or invalid.

As described above, it can be obtained that the correction determination circuit 22 may also be configured to determine whether the update of the offset and amplitude correction values is valid or invalid, and whether the update of the phase correction value is valid or invalid, which update is valid or invalid, because It is a high-resolution encoder that is not affected by the sparseness of the sampling period when the frequency of the two-phase sinusoidal signal is high, and the cost can be reduced because the circuit scale can be kept small.

In addition, in the first to fourth embodiments, the two-phase signal is described as a sine wave, but the phase of a pseudo sine wave or a triangular wave having distortion in the waveform can be corrected with the same configuration.

Claims (4)

1. A correction circuit for an encoder signal, used in an encoder signal processing circuit, The encoder signal processing circuit includes: an AD converter, which converts the orthogonal A-phase and B-phase sinusoidal signals into digital data, and generates A1 signals and B1 signals; a peak detector, which detects the A1 signals and the B1 signals The maximum value and the minimum value; the offset/amplitude correction circuit uses the maximum value and the minimum value detected by the peak detector to calculate the correction of the offset and the amplitude according to the error of the offset and the amplitude value, correcting the offset and the amplitude, thereby generating the A2 signal and the B2 signal; the phase error detector, detecting the phase error amount of the A2 signal and the B2 signal; the phase correction circuit, according to the phase error by the The phase error amount detected by the detector is used to obtain a phase correction value, and generate an A3 signal and a B3 signal with a phase difference of 90 degrees; a position data conversion circuit converts the A3 signal and the B3 signal into a position data, It is characterized in that the correction circuit of the encoder signal includes: a speed detector detecting a speed based on the frequency of the A-phase and the B-phase or the position data; and a correction determination circuit that enables or disables updating of the correction value of the offset and amplitude, and the correction value of the phase, In the speed detector, the speed is detected based on the detection frequency of the A phase and the B phase or the difference of the position data, In the correction determination circuit, When the speed exceeds the set speed once or several times in succession, it is judged as high speed, When the speed is below the set speed for a number of consecutive times more than the number of times judged to be high speed, it is judged to be low speed, At a speed judged to be high speed, the update of the correction value of the offset and amplitude and the correction value of the phase is disabled; at a speed judged to be low, the correction value of the offset and amplitude The update of the correction value and the correction value of the phase is enabled. 2. The correcting circuit of encoder signal as claimed in claim 1, is characterized in that, The speed detector samples the position data at regular intervals at a speed judged to be a low speed by the correction judging circuit, and detects a speed based on a difference in position data between samples; The detection frequency of the A phase and the B phase is used to detect the speed. 3. the correction circuit of encoder signal as claimed in claim 1, The correction determination circuit sets a setting speed at which updating of the correction value of the offset and amplitude is valid or invalid as a first setting speed; and sets a setting speed at which updating of the correction value of the phase is valid or invalid. The constant speed is set to the second set speed. 4. the correction circuit of encoder signal as claimed in claim 1, The correction determination circuit enables or disables updating of a correction value of one of the offset/amplitude correction circuit and the phase correction circuit.

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