CN100582676C - Correction circuit for encoder signal - Google Patents

Abstract

An encoder signal correcting circuit with high position detecting precision can correct the phase error with simple arithmetic operating when the frequency of the two-phase sine signal is high. The position detector includes the following components: a peak detector which detects the peak value of the output signal of the AD transducer; an excursion/amplitude correcting circuit which corrects the error of the excursion and the vibration amplitude and generates (A2) signal and (B2) signal with the detected peak value; a phase error detector which detects the intersection value between the (A2) signal and the (B2) signal; a phase correcting circuit which calculates the correction coefficient of the (A2) signal and the (B2) signal; and a position data converting circuit which switches the sine signal of A phase and B phase to the position data, the position detector also is arranged with the following components: a speed detector which detects the speed with the frequency or position data of the A phase and B phase sine signals; and a correction judging circuit which switches the update of the correction value to the excursion, vibration amplitude and phase to be effective or ineffective.

Description

The correcting circuit of code device signal

Technical field

The present invention relates to handle and obtain in the high-resolution scrambler the sinusoidal signal of 2 phases of quadrature being carried out interpolation, proofread and correct the circuit of the skew of sinusoidal signal of 2 phases and amplitude, phase place.

Background technology

Generally formed the position probing of the scrambler of rotary-type (perhaps line style) by light-emitting component and photo detector and the rotary body (perhaps moving body) that formed cancellate seam (slit) between them, resolution is determined at interval by cancellate seam.Therefore, reduced seam at interval in order to improve resolution, but because machining precision or optical diffraction phenomenon improve resolution with this method and have restriction.

So, generally carry out following method in recent years: A, the B sinusoidal simulating signal mutually that generates the signal Synchronization between the seam with rotary body (perhaps moving body) with 90 phase differential of spending, to carry out the signal after interpolation is handled and the signal that obtains by above-mentioned seam synthesizes to this simulating signal, thereby improve resolution.

In order further to improve the resolution of scrambler, need to improve the resolution that interpolation is handled, promptly simulating signal is transformed to the resolution of the AD transducer of digital signal, thereby can improves whole resolution by improving.This AD transducer can be built in micro computer (micro computer) or LSI, but by the resolution of built-in AD transducer high more also be 10bit, in addition, general precision is poor, in order further to improve resolution, needs to use the AD transducer IC of monomer.

The interface of AD transducer IC and micro computer or LSI has parallel mode and serial mode, but considers that aspect miniaturization or cost serial mode is more effective.But there is the elongated problem of sampling period that sends data in serial mode.For example, under long situation of sampling period of AD transducer, when the frequency gets higher of the sinusoidal signal of 2 phases, the detection number in each cycle reduces, and is difficult to carry out accurately in order to improve the correction of the required skew of precision that interpolation handles, amplitude, phase place.

As the mode that addresses these problems, for example in the flat 7-218288 communique of Japanese Patent Application Laid-Open, take this method: the attenuation coefficient of the amplitude of the sinusoidal signal of 2 phases during with frequency gets higher is stored in the storer in advance, changes the correction of amplitude amount with the compensate for attenuation amount.But though this method can be proofreaied and correct the damping capacity of the sinusoidal signal of 2 phases, if the sampling period is elongated, during the frequency gets higher of the sinusoidal signal of 2 phases, can not correctly detect maximal value or minimum value, corrected value produces error.

Figure 10 is illustrated in the frequency of sinusoidal signal of the 2 phases maximal value when high and the figure of the detection waveform of minimum value, and Figure 11 is the figure of waveform of the intersection point of the expression sinusoidal signal that detects 2 phases for the margin of error of detected phase.When frequency was higher, because of the long influence of transformed samples cycle of showing AD transducer 2, the sinusoidal signal of conversion became stepped as Figure 10 and Figure 11, so be difficult to correctly detect maximum/minimum and phase error.

Under the state that comprises maximum/minimum and phase error, the waveform that the sinusoidal signal of 2 phases is proofreaied and correct becomes the waveform of distortion as shown in figure 12.Under the situation of so high frequency, produce following problem: even carried out the correction of amplitude damping factor, also produce error in the corrected value of skew, amplitude, phase place, the precision that interpolation is handled worsens.

Summary of the invention

The correcting circuit of code device signal of the present invention is used for encoder signal processing circuit, has following structure.This encoder signal processing circuit comprises, the AD transducer is transformed to numerical data with B sinusoidal signal mutually mutually with the A of quadrature, generation A1 signal and B1 signal; Peak detctor, the maximal value and the minimum value of detection A1 signal and B1 signal; Skew/amplitude correction circuit uses by maximal value and minimum value that peak detctor detected, obtains the corrected value of skew and amplitude, proofreaies and correct skew and amplitude, generates A2 signal and B2 signal; Phase error detector, the amount of phase error of detection A2 signal and B2 signal; Phase-correcting circuit according to amount of phase error, is obtained the corrected value of phase place, generates A3 signal and B3 signal that phase differential becomes 90 degree; The position data translation circuit is a position data from A3 signal and B3 signal transformation, and the correcting circuit of this code device signal comprises: speed detector, according to A phase and B frequency or position data mutually, detection speed; Proofread and correct decision circuit, be made as the renewal of the corrected value of the corrected value of skew and amplitude and phase place effective or invalid.

In the speed detector, according to A mutually with B mutually the detection frequency or the difference of position data, detection speed is proofreaied and correct in the decision circuit, speed once or continuous several times become setting speed when above, be judged to be at a high speed, is setting speed when following in speed in continuous several times and than being judged as at a high speed number of times often, is judged to be low speed, and, on the speed that is being judged as at a high speed, it is invalid that the renewal of the corrected value of the corrected value of skew and amplitude and phase place is made as; Be judged as on the speed of low speed, the renewal of the corrected value of skew and the corrected value of amplitude and phase place is being made as effectively.

Correcting circuit according to code device signal of the present invention, even can obtain the skew of the sinusoidal signal of 2 phases or amplitude, phase place change because timeliness changes, also can proofread and correct these side-play amounts accurately, and under the frequency condition with higher of the sinusoidal signal of 2 phases, can be because of the correcting circuit of the sparse and affected code device signal in sampling period yet.

Description of drawings

Fig. 1 is the block scheme of the encoder circuit in first embodiment of the present invention.

Fig. 2 is the key diagram of the action waveforms of the peak detctor in first embodiment.

Fig. 3 is the key diagram of the action waveforms of the phase error detector in first embodiment.

Fig. 4 is that the hits in the one-period of sinusoidal signal is under 14 the situation, and sinusoidal signal is carried out the result's that interpolation handles key diagram when proofreading and correct decision circuit to not using.

Fig. 5 is in first embodiment, and the hits in the one-period of sinusoidal signal is under 14 the situation, and the offset of sinusoidal signal carries out the result's that interpolation handles key diagram.

Fig. 6 is the block scheme of the encoder circuit in second embodiment.

Fig. 7 is the key diagram of method of the speed detector switching detection method of second embodiment.

Fig. 8 is the key diagram of the update cycle establishing method in the detection method 1 of second embodiment.

Fig. 9 is the block scheme of the encoder circuit in the 3rd embodiment.

The key diagram of the maximum/minimum when Figure 10 is a detection high-frequency in example in the past.

The key diagram of the phase error when Figure 11 is a detection high-frequency in example in the past.

Figure 12 is the key diagram of the sinusoidal signal waveform proofreaied and correct under the state that comprises error in the example in the past.

Embodiment

(first embodiment)

Use Fig. 1 to Fig. 5, the phase-correcting circuit of code device signal of the present invention is described.Fig. 1 is the block scheme that expression comprises the encoder signal processing circuit of skew/correction of amplitude, phase correction, and Fig. 2 is the action waveforms of expression peak detctor, and Fig. 3 is the action waveforms of expression phase error detector.

In Fig. 1, the A0 signal of from the original signal of scrambler output, simulating and B0 signal be have 90 degree phase differential A mutually with B sinusoidal signal mutually.Generally be to constitute by light-emitting component and photo detector and seam plate.

Light-emitting component uses LED or laser, and photo detector uses photodiode or phototransistor.The seam plate is to be made by the glass or the resin material that see through light, and the cancellate mask by light is set on the seam plate.Be configured to, photo detector accepts the light of self-emission device via the seam light that plate saw through, and because of the seam plate is set on the rotary body of scrambler, so be formed the cancellate shape of seam plate, makes when rotated from photo detector sine wave output shape.

AD transducer 2 will be a digital signal from simulating signal A0 signal, the B0 signal transformation of scrambler output.Because of the amplitude from the simulating signal of scrambler output is hundreds of mV, so use amplifier etc. to amplify tens times, utilize after being transformed to the voltage of the input range (range) that meets AD transducer 2, then can improve the precision of digital signal.

The output signal that peak detctor 15 detects AD transducer 2 is the maximum/minimum of A1 signal, B1 signal.Fig. 2 represents the action waveforms of peak detctor 15, uses this figure that the detection method of maximum/minimum is described.

In Fig. 2, | the A1| signal and | the B1| signal is respectively with the signal of A1 signal and the conversion of B1 signal absolute value.Detect | the A1| signal and | the intersection point of B1| signal generates intersection point signal 18a, 18b, 18c, 18d.As illustrated in fig. 2, this intersection point signal is divided into area I～area I V with one-period, in area I is to be made as the peaked zone of detecting the A1 signal, at area I I is the zone that is made as the minimum value that detects the B1 signal, at area I II is the zone that is made as the minimum value that detects the A1 signal, is to be made as the peaked zone of detecting the B1 signal at area I V.

The action of declare area I, at first, when detecting intersection point signal 18a, relatively the last sub-value of A1 signal and this sub-value, when this sub-value was big, renewal latch data 16a (max) in this sub-value hour, did not upgrade latch data 16a (max).Repeat this action in the interval of area I, when detecting intersection point signal 18b, determine the maximal value of latch data 16a (max) as the A1 signal.Because of the action of area I I, area I II, area I V identical with area I, so omit.Like this, can detect the maximum/minimum of A1 signal, B1 signal.

Skew/amplitude correction circuit 4 uses the maximum/minimum signal 16 that is detected by peak detctor 15, the normalization that A1 signal and B1 signal are removed skew and amplitude.

Use maximum/minimum signal 16, can obtain the skew (OS_DETa, OS_DETb) of A1 signal and B1 signal according to formula 1.In addition, if with the off-set value of proofreading and correct be made as OS_LEVEL, the signal removed after the skew is made as A1d signal and B1d signal, then can remove skew according to formula 2.

$\left.\begin{array}{c}\mathrm{Ald}=\mathrm{Al}-\mathrm{OS}\_\mathrm{DETa}+\mathrm{OS}\_\mathrm{LEVEL}\\ \mathrm{Bld}=\mathrm{Bl}-\mathrm{OS}\_\mathrm{DETb}+\mathrm{OS}\_\mathrm{LEVEL}\end{array}\right\}$ ... (formula 2)

Use maximum/minimum signal 16, also can obtain the amplitude (PP_DETa, PP_DETb) of A1 signal and B1 signal according to formula 3.In addition, if when the normalization size of amplitude is made as K, can obtain the A2 signal and the B2 signal of the error of having proofreaied and correct skew and amplitude according to formula 4.

$\left.\begin{array}{c}\mathrm{<figure-callout\; id="2"\; label="A"\; filenames="C2007101472040014H1.png,C2007101472040018H1.png"\; state="\{\{state\}\}">A</figure-callout>}2=\mathrm{Ald}\&times;K/\mathrm{PP}\_\mathrm{<figure-callout\; id="2"\; label="DETa\; B"\; filenames="C2007101472040014H1.png,C2007101472040018H1.png"\; state="\{\{state\}\}">DETa</figure-callout>}& \\ B2=\mathrm{Bld}\&times;K/\mathrm{PP}\_\mathrm{DETb}\end{array}\right\}$ ... (formula 4)

Phase correction module 9 is to be made of phase-correcting circuit 6 and phase error detector 7, carry out following effect: detect by phase error detector 7 and be corrected the A2 signal of skew/amplitude, the phase error of B2 signal, according to the margin of error that is detected by phase error detector 7, use A correction signal, the B correction signal that the phase error of A2 signal, B2 signal is proofreaied and correct by phase-correcting circuit 6, output has A3 signal, the B3 signal of the phase differential of 90 degree.

Use Fig. 3 that the details of this action is described.Fig. 3 is to be benchmark with the A2 signal, and only the phase place of B2 signal has become in advance the example of the B2d signal of α orphan's degree.Amplitude is normalized to the K size by skew/amplitude correction circuit 4, so the amplitude of A2 signal, B2d signal becomes K.

Phase error detector 7 detects the size of the intersection point of A2 signal when detecting intersection point signal 18a, 18b, 18c, 18d, B2d signal, according to this intersection value calculation process and derive the phase correction amount.A2 signal, B2d signal can be represented like that suc as formula 5.The A2 signal of this moment, the intersection point of B2d signal intersect at (π/4-α/2) lonely degree, (5 π/4-α/2) lonely degree, and the size of its intersection point becomes Ksin (π/4-α/2), Ksin (5 π/4-α/2).

Because of mutual equal and opposite in direction, so when being made as C45=Ksin (π/4-α/2), C225=Ksin (5 π/4-α/2), can obtain phase error/2 according to formula 6.In addition, factor 6 is to be that benchmark is obtained the B correction signal with the A2 signal, thus calculate according to the formula of sin-1, but can be benchmark with the B2d signal also obviously, according to cos ^-1Formula and obtain.

$\left.\begin{array}{c}A2=K\sin \mathrm{\&theta;}\\ B2d=K\cos (\mathrm{\&theta;}+\mathrm{\&alpha;})\end{array}\right\}$ ... (formula 5)

$\left.\begin{array}{c}\mathrm{\&alpha;}/2=\mathrm{\&pi;}/4-{\sin }^{-1}(C45/K)\\ \mathrm{\&alpha;}/2=\mathrm{\&pi;}/4-{\sin }^{-1}(C225/K)\end{array}\right\}$ ... (formula 6)

In addition, phase-correcting circuit 6 can come the phase calibration error according to formula 7, formula 8.Wherein, Kp1, Kp2 are the phase correction gains that is used to obtain A correction signal, B correction signal, set the phase correction gain, so that the phase differential of A3 signal and B3 signal becomes 90 degree.

A3=A2+Kp1B2d=Ksin θ+Kp1Kcos (θ+α) ... (formula 7)

B3=B2d+Kp2A2=Kcos (θ+α)+Kp2Ksin θ ... (formula 8)

The method of obtaining of Kp1 and Kp2 then, is described.In formula 7, because of θ=-α/2 o'clock, as long as make the A3 signal become 0, so Kp1 can obtain according to formula 9.

$\left.\begin{array}{c}0=K\sin (-\mathrm{\&alpha;}/2)+\mathrm{<figure-callout\; id="1"\; label="Kp"\; filenames="C2007101472040018H1.png,C2007101472040019H2.png"\; state="\{\{state\}\}">Kp</figure-callout>}1\&CenterDot;K\cos (\mathrm{\&alpha;}/2)\\ \mathrm{<figure-callout\; id="1"\; label="Kp"\; filenames="C2007101472040018H1.png,C2007101472040019H2.png"\; state="\{\{state\}\}">Kp</figure-callout>}1=\tan (\mathrm{\&alpha;}/2)\end{array}\right\}$ ... (formula 9)

In addition, equally in formula 8, because of in θ=pi/2-α/2 o'clock, as long as make B3 become 0, so Kp2 can obtain according to formula 10.

$\left.\begin{array}{c}0=K\cos (\mathrm{\&pi;}/2+\mathrm{\&alpha;}/2)+\mathrm{<figure-callout\; id="2"\; label="Kp"\; filenames="C2007101472040014H1.png,C2007101472040018H1.png"\; state="\{\{state\}\}">Kp</figure-callout>}2\&CenterDot;K\sin (\mathrm{\&pi;}/2-\mathrm{\&alpha;}/2)\\ \mathrm{<figure-callout\; id="2"\; label="Kp"\; filenames="C2007101472040014H1.png,C2007101472040018H1.png"\; state="\{\{state\}\}">Kp</figure-callout>}2=\tan (\mathrm{\&alpha;}/2)\end{array}\right\}$ ... (formula 10)

Because of the Kp1 that obtained according to formula 9 and formula 10 and Kp2 can be represented by cotype mutually, so the burden of computing reduces by half.A2 signal, B2 signal (B2d signal) are obtained α/2 according to formula 6, obtain the phase correction gain according to formula 9 or formula 10, can obtain having proofreaied and correct A3 signal, the B3 signal of the side-play amount of phase place by use formula 7 and formula 8.

Then, the A3 signal of having proofreaied and correct phase place, the size of B3 signal are described.The maximal value of the amplitude of formula 7 and formula 8 be respectively θ=pi/2-α/2, θ=-point of α/2, so these are brought into formula 7 and formula 8, then A3 signal, B3 signal become formula 11 and formula 12, can proofread and correct with identical size as shown in Figure 3.In the one-period of 2 phase signals, there are two intersection points, use so also can average to handle to the Kp that obtains at each intersection point.

$\left.\begin{array}{c}A3=K\sin (\mathrm{\&pi;}/2-\mathrm{\&alpha;}/2)+\mathrm{Kp}\&CenterDot;K\cos (\mathrm{\&pi;}/2+\mathrm{\&alpha;}/2)\\ =K\cos (\mathrm{\&alpha;}/2)-\mathrm{Kp}\&CenterDot;K\sin (\mathrm{\&alpha;}/2)\end{array}\right\}$ ... (formula 11)

$\left.\begin{array}{c}B3=K\cos (\mathrm{\&alpha;}/2)+\mathrm{Kp}\&CenterDot;K\sin (-\mathrm{\&alpha;}/2)\\ =K\cos (\mathrm{\&alpha;}/2)-\mathrm{Kp}\&CenterDot;K\sin (\mathrm{\&alpha;}/2)\end{array}\right\}$ ... (formula 12)

Then, position data conversion circuit 10 is described.Use has A3 signal, the B3 signal of the phase differential of 90 degree, and use formula 13 then can easily be transformed to position data (angle-data of interpolation) θ IP (14).

θ IP=tan ^-1(A3/B3) ... (formula 13)

Then, corrected value refresh circuit 23 of the present invention is described.Corrected value refresh circuit 23 is made of speed detector 21 and correction decision circuit 22.Speed detector 21 is according to the frequency output detection speed 19 of the sinusoidal signal of 2 phases.The sinusoidal signal A0 signal or the B0 signal of input are compared and be transformed to square wave with separately central value, the time of the marginating compartment of square wave is measured by counter, thus sense cycle, can be according to detected value computing frequency.And, can be according to being come computing and output speed by the frequency of computing.

As other method, positional data 14 is sampled in some cycles, and the difference of the data when upgrading with last time by obtaining in each cycle can detection speed.Proofread and correct decision circuit 22 and at first accept, compare continuously when surpassing more than 2 times at detection speed with certain setting speed, be judged to be at a high speed from the detection speed 19 of speed detector 21 outputs; Compare continuously when surpassing more than 4 times at detection speed with setting speed, be judged to be low speed.

Wherein, be made as different number of times with being judged to be number of times A at a high speed with the number of times B that is judged to be low speed, number of times A is set at more than 1 time, number of times B is set at the number of times greater than number of times A.Like this, can become the stable acts of determination of the frequent switching that has prevented near the high speed/low speed setpoint frequency.

In addition, also can make here the speed of setting have hysteresis characteristic, compare with switch to speed at a high speed from low speed, will must be low from the speed setting that switches to low speed at a high speed, can become stable acts of determination like this.

Then, for speed 19 being judged to be under the situation at a high speed, be not offset the renewal with the corrected value of amplitude and phase place, corrected value update signal 20 (for example, be made as in the renewal with corrected value be the L signal under the invalid situation) is outputed to peak detctor 15 and phase error detector 7.

In addition, in order to be judged to be under the situation of low speed, be offset the renewal with the corrected value of amplitude and phase place, corrected value update signal 20 (for example, be made as in the renewal with corrected value be the H signal under the effective situation) is outputed to peak detctor 15 and phase error detector 7.The speed (judgement speed is the speed of high speed/low speed) of switching the corrected value update signal is set at the value that can correctly detect corrected value.

The benchmark of setting is, speed setting is cut apart more than (per 5 degree samplings) for can detect 72 during the one-period of the sinusoidal signal of 2 phases, then the error of corrected value can be suppressed less.In the sinusoidal signal of 2 phases because temperature or supply voltage, The noise and easily under the situation of change, though the position detection accuracy of scrambler can worsen, can with cut apart number set (for example, per 10 degree are sampled) less.

Fig. 4 and Fig. 5 are that to be illustrated in hits in the one-period of sinusoidal signal be under 14 times the situation, the sinusoidal signal of 2 phases is carried out the result that interpolation is handled, all be under the high frequency operating state, in the one-period of sine wave, AD transducer 2 be sampled as 14 times situation.

Fig. 4 is the situation of not proofreading and correct decision circuit in previous methods, and Fig. 5 is provided with correction decision circuit of the present invention, and the renewal of corrected value is made as waveform under the invalid situation.The detection of corrected value can not normally be carried out in previous methods, disperses so the difference between sampling exists, but can be roughly certain in the method for the invention.

As mentioned above, circuit structure and calculation process by first embodiment, even can obtain the skew of the sinusoidal signal of 2 phases or amplitude, phase place change because timeliness changes, also can proofread and correct these deviations accurately, and under the frequency condition with higher of the sinusoidal signal of 2 phases, can be because of the sparse and affected high-resolution scrambler in sampling period yet.

(second embodiment)

Use Fig. 6 to Fig. 8, second embodiment of the present invention is described.Different with first embodiment is when low speed and the detection method of switch speed during high speed, and this is elaborated.

Fig. 6 is the structural drawing of second embodiment, and corrected value decision circuit 22 is judged by speed will represent that the speed decision signal 30 of the state of (for example, high level signal)/low speed (for example, low level signal) outputs to speed detector 21 at a high speed.

Fig. 7 is the figure of expression by the method for speed detector switching detection method, speed decision signal 30 detection speed continuous more than 2 times the Velocity Updating cycle become setting speed Vc when above, be judged to be high level (at a high speed),, be judged to be low level (low speed) becoming Vc for continuous 4 times when following.

Speed detector is to use with some cycles positional data 14 during the speed decision signal is low level and samples, according to the detection method 1 of the Differential Detection speed between sampling; During high level, be to use the detection method 2 of basis by the time detecting speed of the marginating compartment of A0 signal and B0 signal and the square wave that central value generated separately.

This be because, detection method 2 is the time detection speeds by the marginating compartment that detects A0 signal and B0 signal, so the update cycle according to frequency speed changes, along with speed reduce and the update cycle elongated, the response variation of speed decision signal, but in detection method 1, can at random determine the update cycle, update cycle does not rely on speed and becomes certain cycle, so by when low speed, using detection method 1, thereby the response of the speed decision signal when can not can lose low speed obtains stable output.

And, set the update cycle of detection method 1, so that detection method 1 speed identical with the update cycle of detection method 2 becomes setting speed Vc, thereby the response when low speed switches to high speed is identical with response when switching to low speed at a high speed, can obtain the output of more stable speed decision signal.

Use Fig. 8 that the establishing method of the update cycle of detection method 1 is described.Curve A-Ad of Fig. 8 is that the update cycle of detection method 2 is Tu2[s], speed is made as V[r/min], when once the A0 signal in the rotation and the number of edges of B0 signal are made as P, can obtain according to formula 14.

Tu2=1/ (V/60 * P) ... (formula 14)

Straight line B-Bd is the update cycle of detection method 1, and the update cycle is Tu1[s].Set Tu1 according to formula 15 so that the speed of the intersection point C of curve A-Ad and straight line B-Bd becomes setting speed Vc, thereby the update cycle of detection method on the Vc 1 and detection method 2 become the identical cycle.

Tu1=1/ (Vc/60 * P) ... (formula 15)

As mentioned above, by the speed detection method of the speed detector 21 of second embodiment is switched when the low speed and during high speed, can obtain stable speed decision signal, can more correctly switch the effective or invalid of stable corrected value, therefore can obtain ageing resistance changes, and under the frequency condition with higher of the sinusoidal signal of 2 phases, can be because of the sparse and affected high-resolution scrambler in sampling period yet.

(the 3rd embodiment)

Use Fig. 9, the 3rd embodiment of the present invention is described.Different with second embodiment is, has 2 kinds of setting speeds that are used to judge proofreading and correct decision circuit 22, and this is elaborated.

Proofread and correct decision circuit 22 can set individually respectively the corrected value that makes skew and amplitude and phase place corrected value be updated to effective or invalid signal.When speed uprises, the sinusoidal signal A0 signal of 2 phases and the frequency gets higher of B0 signal, the sampling period of AD transducer 2 is long, so assay intervals is sparse.

For A1 signal, the B1 signal of the sinusoidal signal of 2 phases that detect at peak detctor 15, because of the variation of the size of the value around the peak value less, so be difficult to be subjected to the sparse influence that produces in sampling period.Therefore, can be in proofreading and correct decision circuit 22, set the 1st setting speed that is used to determine to be offset with the renewal of the corrected value of amplitude than the highland.

For example, even produce the side-play amount of ± 8 degree, peak value also just decays 1%.In can allowing the system of 1% change, the hits in each cycle of the sinusoidal signal of 2 phases can be allowed to become till 22.5 (360/16) the frequency.The corrected value of phase place detects the A2 signal of sinusoidal signal of 2 phases and the intersection point of B2 signal, changes at 1% o'clock in this intersection value, and the scope of angle becomes ± 0.6 degree.Therefore, in proofreading and correct decision circuit 22, compare, set the 2nd setting speed of the renewal of the corrected value that is used to determine phase place than the lowland with the 1st setpoint frequency.

As mentioned above, to be set at 2 kinds of structures that skew and correction of amplitude usefulness and phase correction are used at the setting speed in the correction decision circuit 22 of the 3rd embodiment individually by adopting, can reduce the sinusoidal signal A0 signal of 2 phases, the amplitude change of B0 signal, so can obtain ageing resistance changes, and under the high situation of the frequency of the sinusoidal signal of 2 phases, can be because of the sparse and affected high-resolution scrambler in sampling period.

(the 4th embodiment)

The 4th embodiment of the present invention is described.Different with first to the 3rd embodiment is, proofreaies and correct decision circuit 22 and constitutes, and judgement will be offset renewal with which corrected value of the corrected value of the corrected value of amplitude or phase place and be made as effectively or invalid, and it is described in detail.

In the lower system of the frequency of the A0 signal of the sinusoidal signal of 2 phases and B0 signal, as previously mentioned, can ignore the change of amplitude, so will be offset and the renewal of the corrected value of amplitude be made as all the time effectively also no problem.At this moment, only the renewal of the corrected value of detected phase correction is made as effectively or is invalid.

In addition, in lineal scale element (linear scale) etc., have the situation of the side-play amount of phase place by the precision decision of cancellate seam plate, at this moment, phase-correcting circuit 6 does not carry out phase correction to be handled, and only is offset with correction of amplitude to get final product.Being updated to effectively and invalid getting final product of the corrected value of 22 judgement skews of correction decision circuit and amplitude.

As mentioned above, can obtain proofreading and correct that decision circuit 22 can constitute also that being updated to of the corrected value of judging skew and amplitude is effective or invalid, phase correcting value be updated in effective or invalid which be updated to effective or invalid, because can make circuit scale suppress lessly, so can reduce cost, ageing resistance changes, and under the high situation of the frequency of the sinusoidal signal of 2 phases, can be because of the sparse and affected high-resolution scrambler in sampling period.

In addition,, 2 phase signals are illustrated as sine wave, but also can carry out the correction of phase place to pseudo sine wave, the triangular wave that has distortion at waveform with identical structure from first embodiment to the, four embodiments.

Claims (4)

1. the correcting circuit of a code device signal is used for encoder signal processing circuit,

This encoder signal processing circuit comprises: the AD transducer is transformed to numerical data with B sinusoidal signal mutually mutually with the A of quadrature, generation A1 signal and B1 signal; Peak detctor detects the maximal value and the minimum value of described A1 signal and described B1 signal; Skew/amplitude correction circuit, use according to the error of skew and amplitude, is obtained the corrected value of skew and amplitude by described maximal value and described minimum value that described peak detctor detected, proofread and correct described skew and described amplitude, thereby generate A2 signal and B2 signal; Phase error detector detects the amount of phase error of described A2 signal and described B2 signal; Phase-correcting circuit according to by the detected described amount of phase error of described phase error detector, is obtained the corrected value of phase place, generates A3 signal and B3 signal that phase differential becomes 90 degree; The position data translation circuit is a position data from described A3 signal and described B3 signal transformation,

It is characterized in that the correcting circuit of this code device signal comprises:

Speed detector is according to described A phase and described B frequency or described position data mutually, detection speed; And

Proofread and correct decision circuit, the renewal of the corrected value of the corrected value of described skew and amplitude and described phase place is made as effective or invalid,

In the described speed detector, according to described A mutually with described B mutually the detection frequency or the difference of described position data, detection speed,

In the described correction decision circuit,

Described speed once or continuous several times become setting speed when above, be judged to be at a high speed,

Is setting speed when following in described speed in continuous several times and than being judged as at a high speed number of times often, is judged to be low speed,

On the speed that is being judged as at a high speed, it is invalid that the renewal of the corrected value of the corrected value of described skew and amplitude and described phase place is made as; Be judged as on the speed of low speed, the renewal of the corrected value of the corrected value of described skew and amplitude and described phase place is being made as effectively.

2. the correcting circuit of code device signal as claimed in claim 1 is characterized in that,

Described speed detector is judged to be on the speed of low speed at described correction decision circuit, at certain intervals described position data is sampled, and comes detection speed according to the position data difference between sampling; Being judged to be on the speed at a high speed, come detection speed with described B detection frequency mutually mutually according to described A.

3. the correcting circuit of code device signal as claimed in claim 1,

Described correction decision circuit is made as effective or invalid setting speed with the renewal of the corrected value of described skew and amplitude and is made as the 1st setting speed; The renewal of the corrected value of described phase place is made as effective or invalid setting speed is made as the 2nd setting speed.

4. the correcting circuit of code device signal as claimed in claim 1,

Described correction decision circuit is made as the renewal of the corrected value of one of them correcting circuit of described skew/amplitude correction circuit and described phase-correcting circuit effective or invalid.

Images