JP2011064459A - Correction circuit of encoder signal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a correction circuit of an encoder signal, capable of outputting interpolation division data having no deviation without generating a gap in a correction value, even when update of the correction value is switched from an invalid state into a valid state, with respect to a two-phase analog sine wave including periodical fluctuations in the offset, amplitude and phase. <P>SOLUTION: An encoder for outputting position data 14a from an analog sinusoidal wave signal of orthogonal A-phase and B-phase has a constitution which includes a correction value calculating section 20; a speed determining section 21 for outputting a speed determination flag 21a; a correction value update determining section for invalidating a correction value update flag 22a, when the speed determination flag 21a has a high speed, and validating the correction value update flag when the speed determining flag has a low speed and an operation correction value 20a agrees with a signal correction value 23a; and a correction value update section 23 for updating by the operation correction value 20a, the signal correction value 23a used for signal correction in the valid case in accordance with the correction value update flag 22a, and holding the signal correction value, without updating in an invalid case. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method of correcting offset, amplitude, and phase of a two-phase analog sine wave signal in an encoder that obtains high resolution by interpolating and processing orthogonal two-phase analog sine wave signals.

In rotary optical encoders generally used in motor control,
When a light receiving element such as a photodiode receives light output from a light source such as an infrared LED, the amount of transmitted light is increased or decreased depending on the relative position between the slit pattern on the surface of the light receiving element and the slit plate attached to the rotating shaft. The orthogonal two-phase analog signal output by the photoelectric conversion of the element is subjected to pulse conversion by a comparator, and the position information is detected by counting up / down the pulse.

  As a method for increasing the resolution of this type of encoder, there is a method of increasing the pulse count by reducing the slit pattern interval. However, with this method, it is difficult to achieve high resolution because of limitations in slit processing accuracy and interference of light between adjacent slits.

  Therefore, in recent years, by changing the slit shape, the amount of received light is adjusted to make the analog signal a sine wave, and interpolating between the pulse counts by interpolation division processing using orthogonal two-phase analog sine wave signals makes it possible to increase the resolution. The method of aiming at is becoming mainstream. Since complex interpolation processing is required in actual interpolation division processing, an analog sine wave signal is converted into a digital signal by an AD converter, and interpolation division data is generated by using inverse conversion of a trigonometric function by digital signal processing. To do.

  At this time, in order to perform accurate inverse conversion, offset, amplitude, and phase correction is necessary for the digital signal. For example, the instantaneous value y1 of y when x = 0 for the two-phase sine waves x and y. , Y2 and storage means for storing the instantaneous values x1, x2 of x when y = 0 and the instantaneous values x3, x4 of x when | x | = | y |, and x1, x2, y1, An error calculating means for calculating an amplitude error, a phase error, and a DC offset from y2, x3, and x4, and correcting the two-phase sine wave signal using these detected errors to obtain an ideal two-phase sine wave signal. An error correction means for obtaining, and a position detection unit for detecting the rotation angle by tan inverse transformation from the ideal two-phase sine wave obtained in this way, and the storage means is configured such that the moving speed of the moving body is a predetermined value. In the above case, y1, y2, x1, x2, x3, x Is maintained without updating, and when the moving speed of the moving body is equal to or lower than the predetermined value, y1, y2, x1, x2, x3, and x4 are respectively set to x = 0, y = 0 and At this time, a position detecting device with an error correction function is proposed which is updated and stored sequentially at a time when | x | = | y |. (For example, see Patent Document 1)

JP-A-5-256638

The method of Patent Document 1 is effective in reducing the error of the instantaneous value due to the limitation of the sampling frequency of the AD converter and the calculation cycle. However, the orthogonal two-phase analog sine wave signal normally input to the AD converter contains periodic fluctuations in offset, amplitude, and phase due to eccentricity and inclination when the slit plate is attached. A gap occurs when updating is started (validated) from a state where updating of values is stopped (invalid). Further, since the same gap is included in the correction value calculated from the instantaneous value, the interpolation division data (position data) generated from the corrected signal is shifted stepwise. For example, if such a step-like deviation occurs in the position data of an encoder used for motor control, the detection speed varies and torque pulsates, causing abnormal noise.

  In order to solve the above-described problems, the present invention provides an AD converter that AD-converts A-phase and B-phase analog sine wave signals (A0 and B0) and outputs A1 and B1, and normalizes A1 and B1. A signal correction unit that corrects the digital sine wave signals A2 and B2 having a quadrature phase difference, an interpolation conversion unit that converts A2 and B2 into interpolation division data, and pulses A0, B0, and an origin signal (Z0). An encoder comprising a pulse count unit that outputs a pulse count value by performing conversion and UP / DOWN counting, and a position data synthesis unit that outputs position data by synthesizing the pulse count value and the interpolated divided data. A correction value calculation unit for calculating a correction value for correcting A1 and B1 and generating a calculation correction value, and setting with hysteresis characteristics for the set speed 1 and the set speed 1 in advance When the detection speed is higher than the set speed 1 compared to the detection speed calculated from the time variation of the position data, the speed is determined to be high, and when the detection speed is lower than the set speed 2 at high speed, the speed is determined to be low. A speed determination unit that outputs a speed determination flag; a correction value update determination unit that outputs a correction value update flag that enables / disables updating of a signal correction value used for correction of A1 and B1 by the signal correction unit; A correction value update unit that updates the signal correction value with the calculated correction value when enabled according to a correction value update flag, and holds the signal correction value without updating when disabled, the correction value update determination unit The correction value update flag is disabled when the speed determination flag is high speed, and the correction value update flag is enabled when the speed determination flag is low speed and the calculated correction value and the signal correction value match. To have.

  The correction value update determination unit further includes a position data latch unit that outputs position data when the correction value update flag becomes invalid from valid to invalid, and the correction value update determination unit corrects when the speed determination flag is high. The value update flag is disabled, the speed determination flag is low, and the correction value update flag is enabled when the calculation correction value and the signal correction value match or when the position data and the latch position data match. It is good also as composition to make.

  According to the encoder signal correction circuit of the first aspect of the present invention, the correction value update is switched from invalid to valid for a two-phase analog sine wave in which the offset, amplitude, and phase include periodic fluctuations. However, the correction of the encoder signal that is not affected by the eccentricity or inclination of the slit plate can be performed without generating a gap in the correction value, and can output a signal that outputs smooth interpolated division data (position data) without deviation. A circuit can be provided.

  According to the encoder signal correction circuit of the second aspect, when the correction value calculated by the change of the ambient temperature or the like does not coincide with the correction value held by invalidating the update. In addition, by enabling the update when the position data when the correction value is held after a certain time and the current position data match, it is possible to avoid a state where the update remains invalid and is not released, and stable signal correction can be performed. An encoder signal correction circuit can be provided.

1 is a block diagram of an encoder position detection circuit according to a first embodiment of the present invention. Block diagram of an encoder position detection circuit in Embodiment 2 of the present invention

Example 1
The encoder signal correction circuit according to the present invention will be described below with reference to FIG.

  FIG. 1 is a block diagram of an encoder position detection circuit, which includes an AD conversion unit 10, a signal correction unit 11, an interpolation conversion unit 12, a pulse count unit 13, a position data synthesis unit 14, a correction value calculation unit 20, and a speed determination unit. 21, a correction value update determination unit 22, and a correction value update unit 23.

  A0, B0, and Z0 are A-phase and B-phase analog original signals and analog origin signals output from an optical system circuit (not shown). The optical system circuit includes a light emitting element, a light receiving element, and a slit plate. A0 and B0 are sinusoidal signals having a phase difference of 90 degrees, and Z0 is a signal indicating the origin position of the encoder. The light emitting element is an LED or a laser beam, the light receiving element is a photodiode or a phototransistor, and the surface of the light receiving element has a lattice slit pattern. The slit plate is made of glass or a resin material that transmits light, and a lattice-like mask that blocks light is provided on the slit plate. The light from the light emitting element is arranged to receive the light transmitted by the light receiving element through the slit plate. The slit plate is installed on the rotating shaft of the encoder, and the relative position between the slit pattern and the slit plate changes when rotating. A slit is formed so that a pulse indicating the sine wave waveform and the origin position is output from the light receiving element.

  The AD converter 10 converts A0 and B0 into digital signals by sampling at a fixed period, and outputs A1 and B1. Since the amplitude of the analog signal output from the actual optical system circuit is several hundred mV, it is amplified by a factor of ten using an amplifier or the like and converted to a voltage that matches the input range of the AD converter 10 for use. Thus, the accuracy of the digital signal can be increased. Alternatively, the converted digital signal may be averaged a plurality of times or subjected to digital filter processing to output a signal in which the influence of noise is reduced.

  Here, in the digitally converted A1 and B1, offsets deviate from the center value due to amplifier variations and AD converter conversion errors, the amplitude differs from the full signal range, and the phase difference deviates from quadrature (90 degrees). Therefore, signal normalization and orthogonalization are required for the next conversion by the interpolation conversion unit 12 to the accurate interpolation division data 12a, so that the signal correction unit 11 corrects A1 and B1.

  The signal correction unit 11 corrects A1 and B1 with a signal correction value 23a including an offset correction value, an amplitude correction value, and a phase correction value output from a correction value update unit 23, which will be described later, and the offset and amplitude are normalized. A2 and B2 having quadrature phase difference are output. In order to normalize A1 and B1, offset correction cancels the offset by adding an offset correction value to each of A1 and B1, and amplitude correction multiplies the signal whose offset is canceled by the amplitude correction value. By doing so, it becomes the amplitude of the full range. Further, the phase is orthogonalized by performing phase shift processing using the phase correction value on the two normalized signals.

  The interpolation conversion unit 12 outputs interpolation division data 12a by performing inverse transformation (inverse sine transformation or inverse tangent transformation) of a trigonometric function on A2 and B2 having a normalized quadrature phase difference.

  The pulse count unit 13 converts A0, B0, and Z0 into binary pulses by a comparison amplifier such as a comparator, performs UP / DOWN counting with a binary pulse of A0 and B0, and uses a binary pulse of Z0. A pulse count value 13a for clearing the count to zero is output.

The position data synthesizing unit 14 synthesizes the phase of the pulse count value 13a and the interpolated divided data 12a to interpolate between the counts of the pulse count values with the interpolated divided data, and outputs high-resolution position data 14a. When performing phase synthesis, there is a discrepancy between the count change timing of the pulse count unit and the change timing of the interpolated divided data due to the sampling period of the AD conversion unit and the calculation delay of the correction processing. By doing so, continuous position data can be output.

  The correction value calculation unit 20 detects the offset value / amplitude value of each of A1 and B1 and the phase difference between A1 and B1, and generates a calculation correction value 20a for correcting A1 and B1. For the detection of the offset value and the amplitude value, the maximum value and the minimum value within one cycle of the input A1 and B1 are detected, the offset value is obtained by averaging, and the amplitude value is detected by taking the difference. . The reverse sign of the difference between the detected offset value and the center value of the signal range is set as an offset correction value, and the reciprocal of the detected amplitude value is set as an amplitude correction value. The phase difference is detected by performing inverse sine transformation on the intersection value after once normalizing A1 and B1. The difference between the detected phase difference and the value obtained by inverse sine transformation of the normalized sine wave having a quadrature phase difference is defined as a phase correction value. These offset correction value, amplitude correction value, and phase correction value are combined and output as a calculation correction value 20a. The speed determination unit 21 calculates a detection speed from the position data 14a, compares the predetermined set speed 1 and the set speed 2 with each other, determines high speed / low speed, and outputs a speed determination flag 21a (for example, H level when high speed, L level at low speed). In the calculation of the detection speed, the position data 14a output from the position data synthesizing section 14 is sampled at a cycle that is an integral multiple of the sampling in the AD conversion section, and the detection speed is calculated from the position data difference between the samplings. As another method for calculating the detection speed, a method is also used in which analog signals A0 and B0 output from the optical system circuit are converted into binary pulses by a comparison amplifier such as a comparator, and the speed is calculated from the time of the pulse edge interval. May be. At this time, a stable detection speed can be obtained by averaging the detection speed a plurality of times or performing digital filter processing. The set speed 1 may be set to a speed at which the accuracy of the calculation correction value 20a is not allowed due to the sampling period of the analog sine wave by the AD conversion unit 10 or the calculation delay in the signal processing of the correction value calculation unit 20, and the detection speed is set. When the speed is 1 or more, it is determined that the speed is high, and the speed determination flag 21a is output at H level. Also, the setting speed 2 is a speed obtained by lowering the setting value by giving a hysteresis characteristic to the setting speed 1, and the hysteresis width does not frequently switch between high speed and low speed when switching from low speed to high speed at the setting speed 1. The range may be set, and it is determined that the detected speed is equal to or lower than the set speed 2, and the speed determination flag 21a is output at the L level.

  The correction value update determination unit 22 outputs a correction value update flag 22a that validates / invalidates the update of the correction value used in the signal correction unit 11 according to the speed determination flag 21a, the calculation correction value 20a, and the correction value 23a (for example, a valid value). (H level when disabled, L level when disabled). When the speed determination flag 21a is at the H level (high speed), the correction value update is invalidated, and the correction value update flag 22a is output at the L level. Further, when the speed determination flag is L level (low speed) and the calculation correction value 20a and the correction value 23a coincide with each other, update of the correction value is validated, and the correction value update flag 22a is output at H level. Here, in the case of determining a match, it does not include an error due to AD conversion sampling or a calculation error of the calculation correction value 20a. ) And a match is determined when the difference between the calculation correction value 20a and the signal correction value 23a is less than or equal to the width. Note that in a state where high speed / low speed are not fixed, such as immediately after power-on, the correction value update is made effective (H level), whereby the signal correction value 23a is updated by the correction value update unit 23 described later, and stable correction is performed. Processing can be performed.

  The correction value update unit 23 updates and outputs the calculation correction value 20a generated by the correction value calculation unit 20 as the signal correction value 23a in the case of H level (correction value update valid) according to the correction value update flag 22a. If the correction value update is invalid), the signal correction value 23a is not updated and the value at that time is held and output.

As described above, even when the update of the correction value is switched from invalid to valid for the two-phase analog sine wave including the cyclic fluctuation in the offset, amplitude, and phase by the position detection circuit and the correction process of the first embodiment, Since the update value (calculation correction value) calculated at that time is the same as the correction value (signal correction value) used in signal correction, there is no switching gap and smooth interpolation without deviation. Signal correction for outputting the divided data (position data) can be performed, and an encoder that is not affected by the eccentricity or inclination of the slit plate can be obtained.

(Example 2)
A second embodiment of the present invention will be described with reference to FIG.

  The position data latch unit 24 is different from that of the first embodiment, and the correction value update determination unit 23 is different in a method for determining whether the correction value update is valid / invalid. The difference will be described.

  The position data latch unit 24 detects a falling edge of the correction value update flag 22a, that is, a change point of the correction value update from valid (H level) to invalid (L level), and when the edge is detected, the position data synthesis unit 14 is output as latch position data 24a. By doing this, it is possible to detect the position data when the correction value update becomes invalid from valid.

  The correction value update determination unit 22 validates (H level) / invalidates the update of the correction value used in the signal correction unit 11 according to the speed determination flag 21a, the calculation correction value 20a, the correction value 23a, the position data 14a, and the latch position data 24a ( The correction value update flag 22a to be set to (L level) is output. When the speed determination flag 21a is at the H level (high speed), the correction value update is invalidated, and the correction value update flag 22a is output at the L level. Further, when the speed determination flag is L level (low speed) and the calculation correction value 20a and the correction value 23a coincide with each other, update of the correction value is validated, and the correction value update flag 22a is output at H level. Furthermore, the position data 14a when the speed determination flag changes from H level (high speed) to L level (low speed) is held, and the position data changes by a certain amount (for example, the rotation type) while the correction value update is valid from there. When the encoder is rotated once), the correction value update is validated when the position data 14a and the latch position data 24a coincide with each other, and the correction value update flag 22a is output at the H level. Here, even when it is determined that the position data 14a and the latch position data 24a coincide with each other, the coincidence determination has a width similar to the calculation correction value 20a and the signal correction value 23a.

  As described above, when the position correction circuit 20 according to the second embodiment and the correction process make the correction value update invalid and the signal correction value 23a that is held does not match the calculation correction value 20a due to a change in ambient temperature or the like. In addition, the correction value update is enabled when the position data matches the position data (latch position data) when the correction value is held after a certain time, thereby avoiding the state where the correction value update remains invalid and cannot be released. And an encoder capable of performing stable signal correction can be obtained.

  The correction value update valid / invalid switching may be performed by operating the offset / amplitude / phase independently, or by operating a plurality of correction values together, or by validating one of the correction values. When switching / invalidity, the validity / invalidity of other correction values may be switched at the same time.

  In addition, although the two-phase analog original signal in the first and second embodiments has been described as a sine wave, a pseudo sine wave and a triangular wave whose waveform is distorted can be corrected with the same configuration.

  The encoder signal phase correction circuit of the present invention is useful not only for motor control devices but also for devices equipped with an encoder for obtaining high-resolution position information.

DESCRIPTION OF SYMBOLS 10 AD conversion part 11 Signal correction part 12 Interpolation conversion part 12a Interpolation division | segmentation data 13 Pulse count part 13a Pulse count value 14 Position data synthetic | combination part 14a Position data 20 Correction value calculating part 20a Calculation correction value 21 Speed determination part 21a Speed determination Flag 22 Correction value update determination unit 22a Correction value update flag 23 Correction value update unit 23a Signal correction value A0, B0 A phase, B phase analog original signal Z0 Analog origin signal A1, B1 A phase, B phase signal after digital conversion A2 , B2 A-phase and B-phase signals after signal correction

Claims (2)

A / D conversion unit that AD-converts analog A-phase and B-phase analog sine wave signals (A0 and B0) and outputs A1 and B1, and a digital sine wave signal A2 having a quadrature phase difference in which A1 and B1 are normalized And a signal correction unit that corrects to B2, an interpolation conversion unit that converts A2 and B2 into interpolation division data, A0, B0, and origin signal (Z0) are pulse-converted and pulsed by UP / DOWN counting Correction for correcting A1 and B1 in an encoder including a pulse count unit that outputs a count value and a position data synthesis unit that outputs position data by synthesizing the pulse count value and the interpolated divided data A correction value calculation unit for calculating a value and generating a calculation correction value, a preset speed 1 and a preset speed 2 having hysteresis characteristics with respect to the preset speed 1 and setting the time of the position data A speed determination unit that determines that the detected speed is higher than the set speed 1 compared to the detected speed calculated from the conversion amount, and determines that the detected speed is lower when the detected speed is lower than the set speed 2 at high speed and outputs a speed determination flag; A correction value update determination unit for outputting a correction value update flag for validating / invalidating update of the signal correction value used for correction of A1 and B1 by the signal correction unit; A correction value updating unit that updates the signal correction value with the calculation correction value, and retains the signal correction value without updating if invalid, and the correction value update determination unit includes the correction value update unit when the speed determination flag is high. A correction circuit for an encoder signal, wherein the correction value update flag is invalidated, and the speed determination flag is low, and the correction value update flag is validated when the calculation correction value and the signal correction value coincide with each other. A position data latch unit that outputs position data when the correction value update flag becomes invalid from valid to invalid is further provided, and the correction value update determination unit updates the correction value when the speed determination flag is high speed. The flag is disabled, the speed determination flag is low, and the correction value update flag is enabled when the calculation correction value and the signal correction value match or when the position data and the latch position data match. An encoder signal correction circuit characterized by that.