CN100578756C - Technique for preparing thin extensive integrated injection logic using phosphorus-buried technique - Google Patents
Technique for preparing thin extensive integrated injection logic using phosphorus-buried technique Download PDFInfo
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- CN100578756C CN100578756C CN200810025560A CN200810025560A CN100578756C CN 100578756 C CN100578756 C CN 100578756C CN 200810025560 A CN200810025560 A CN 200810025560A CN 200810025560 A CN200810025560 A CN 200810025560A CN 100578756 C CN100578756 C CN 100578756C
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Abstract
The thin epitaxial integrated injection logic manufacturing process using phosphorus burying technology is a process method for manufacturing integrated injection logic (I<2>L) compatible with general thin epitaxial shallow base, the invention carries out an extra phosphorus burying layer injection in front of epitaxial via PWELL design, in order to enhance the concentration of transmission area and greatly improve the performance of I<2>L. The thin epitaxial integrated injection logic manufacturing process using phosphorus burying technology only add once photo-etching and injection, but not the photo-etching design and annealing process. In the invention, material sheet of the I<2>L manufactured by the thin epitaxial integrated injection logic process using phosphorus burying technology is P-type <111> crystallographic direction, resistance rate is 10 to 20 Omega.cm.
Description
Technical field
The present invention is a kind of integrated injection logic (I that is used to make compatible conventional thin epitaxy shallow base region knot
2L) process belongs to semiconductor integrated technology field.
Background technology
Along with the continuous development and progress of electronic technology, the low-voltage of integrated circuit is used more and more widely.Promote the continuous development of semiconductor fabrication, the extension of bipolar semiconductor technology (Bipolar) is more and more thinner thereupon, and base junction depth is also more and more shallow.More bipolar technology and complementary metal oxide semiconductors (CMOS) (CMOS) now occur and be integrated in the BICMOS technique platform that same technique platform is produced.Carry out the processing of analog signal with bipolar device, make the processing of digital signal of the CMOS (Complementary Metal Oxide Semiconductor) device.But BICMOS technique platform operation is complicated more a lot of than the bipolar process of routine, and cost will exceed more than the twice.For a lot of common circuit, wherein digital signal is not a lot, adopts complicated expensive BICMOS technique platform just very unreasonable.If adopt integrated injection logic (I compatible in the conventional bipolar process
2L) just quite reasonable.
Integrated injection logic (the I of compatibility in the present this bipolar process
2L) manufacturing technology is at thick extension (extension is greater than 5uM), under the situation of dark base junction depth (greater than the 1uM junction depth), the comparative maturity that has developed.The front is already mentioned the same, and along with the continuous reduction of voltage, present extension has been thinned to about 4uM mostly, and under thin like this extension condition, base junction depth also shoals accordingly and is 0.8um, the making integrated injection logic (I of compatibility in the bipolar process
2L) just become very difficult.The conventional thin epitaxy shallow junction technology that process technology before continuing to use under the thick extension condition changes over is made I
2L, otherwise amplification is too little, and test also has only several times under the little electric current; Withstand voltage too low, can only accomplish about 1.5 volts (V).Amplify and withstand voltage very difficult balance, and just reach optimum balance at last, amplify and also can only arrive 2-8 (100uA test down), withstand voltage 1.5V, and be not very stable, the repeatability that at every turn processes is not fine, is not suitable for very much a large amount of volume productions.
Summary of the invention
Technical problem: the purpose of this invention is to provide about a kind of 4uM under (applicable to 3.5uM to 5uM extension condition) extension condition, make high-performance integrated injection logic (I compatible in the bipolar process
2The semiconducter process of manufacturing technology L).This technology by increasing a photoetching and injection, is made high-performance integrated injection logic (I in bipolar process under the prerequisite that does not increase reticle and annealing process
2L).It is low to have cost, and the performance height is made the simple advantage of control.
Technical scheme: from domain, I
2The layout design of L is with the domain under the thick outer deepening base condition.The centre is the collector electrode that do emitter region (N+), and the trap of P type (PWELL) is done the base, and the periphery is that dark phosphorus (DN) adds the emitter region and does emitter.It below the whole zone antimony buried regions district.This layout design under the deepening base junction depth bar, is easy to realize outside thick.When extension is thinned to 4uM left and right sides condition, bury the I of thin epitaxy shallow junction technology making according to the antimony of routine
2The L performance becomes very poor, and very unstable, device architecture figure such as figure one.Conventional antimony buries thin epitaxy shallow junction technology flow process such as figure two.The present invention does a volume for ground phosphorus buried regions injects by using the PWELL version before extension, improve emitter region concentration, has improved I greatly
2The performance of L.The manufacture craft of the thin epitaxy shallow junction integrated injection logic of employing phosphorus-buried technique does not increase reticle and annealing process.Only increase a photoetching and injection.
The present invention adopts the thin epitaxy shallow junction integrated injection logic technology of phosphorus-buried technique to make I
2The material piece of L is P type＜100〉crystal orientation, resistivity is 10～20 Ω cm, technological process is (is example with the 4uM extension) shown in figure three,
Method flow process specific as follows, the related process parameter:
A. feed intake: P type, crystal orientation＜100,
B. antimony buries photoetching, corrosion; Carve I
2The antimony in L zone buries window,
C. antimony buries injection: inject energy 60KeV, implantation dosage 2.6E15; Impurity is antimony, with I
2L injects antimony in the zone,
D. antimony buries annealing: annealing conditions is 1200 ℃, 300 minutes N
2+ 120 minutes O
2,
E. phosphorus buries photoetching, corrosion; Carve I
2The phosphorus in L zone buries window, adopts I herein
2The P trap version of L,
F. phosphorus buries injection: inject energy 120KeV, implantation dosage 4E14; Impurity is phosphorus, with I
2Phosphorus is injected in zone under the P trap of L,
G. boron buries photoetching, injection: injection zone is the peripheral zone that is used for forming isolation,
H. boron buries annealing: 1200 ℃ of 30 minutes N of annealing conditions
2,
I. extension: N type extension, thickness 4 μ m, resistivity 0.7 Ω cm,
The photoetching of j.P trap, injection: injection zone is I
2The base of L, the injection energy is 150KeV, and dosage is 4.5E12, and impurity is boron, and this injects and forms I
2The base of L,
K. dark phosphorescence is carved, injected: injection zone is I
2The emitter region of L, the injection energy is 80KeV, and dosage is 8E15, and impurity is phosphorus, and this injects and forms I
2The emitter region of the side direction of L,
L. dark phosphorus annealing: 1150 ℃ of 80 minutes N
2,
M. isolate photoetching, injection: injection zone is the peripheral zone that is used for forming isolation, and this injects with previous boron and buries the formation isolation,
N. isolate annealing: 1100 ℃ of 40 minutes N
2,
O. dense boron photoetching, injection: injection zone is I
2L base week makes a circle, and is used for forming I
2The ohmic contact regions of L base, the injection energy is 60KeV, and dosage is 4.5E14, and impurity is boron,
P. base annealing: 980 ℃ of 30 minutes N
2,
Q. emitter region photoetching, injection: injection zone is I
2The emitter region of L, collector region, the injection energy is 80KeV, and dosage is 5E15, and impurity is phosphorus, and this injects and forms I
2The collector region of the side direction of L and the ohmic contact of emitter region,
R. emitter region annealing: 900 ℃ of 20 minutes N
2,
S. contact hole photoetching, corrosion: adopt the method etching of dry method+wet method, with formation surface of good state,
T. a sputtered aluminum: 0.8 μ m Al-Si,
U. pressure point photoetching, etching: carve the pressure point zone.
Under this technique platform, the final phosphorus that forms buries I
2The L vertical structure is shown in figure four, and basic single tube parameter is as follows: amplify (β) 30～50/Ic=100uA, BVceo=2.0～3.0V.
Beneficial effect: under the same layout design, the 4uM left and right sides extension that adopts conventional technological process to make, the I of the base junction depth about 0.8uM
2L, poor performance.Under the best conditions, I
2L can only accomplish to amplify 2-8 (100uA down test), about withstand voltage 1.5V, and batch between fluctuation bigger.After the present invention has adopted the phosphorus buried regions, I
2L can accomplish to amplify 30～50 (100uA is tests down), between withstand voltage 2.0～3.0V, and also very stable, repeatability is fine.
The present invention has adopted the technology of phosphorus buried regions, does not increase reticle, does not increase cost like this.And not increasing extra high-temperature annealing process, complete compatibility is general bipolar thin epitaxy shallow base region junction depth technology now.Has I
2The L device performance is good, and technology is simple, and is compatible high, the characteristics that cost is low.
Description of drawings
Fig. 1 is the I that adopts routine techniques to make
2The vertical structure of L device.
Fig. 2 is the manufacture craft flow process that adopts the thin epitaxy shallow junction integrated injection logic of routine techniques.
Fig. 3 is the manufacture craft flow process that adopts the thin epitaxy shallow junction integrated injection logic of phosphorus-buried technique.
Fig. 4 is the I that adopts phosphorus-buried technique to make
2The vertical structure of L device.
Embodiment
The embodiment of the manufacture craft of the thin epitaxy shallow junction integrated injection logic of employing phosphorus-buried technique is following to be example with the 4uM extension):
1. feed intake: P type, crystal orientation＜100 〉
2. oxidation: thickness
3. antimony buries photoetching, corrosion; Carve I
2The antimony in L zone buries window.
4. antimony buries injection: inject energy 60KeV, implantation dosage 2.6E15; Impurity is antimony, with I
2L injects antimony in the zone.
5. antimony buries annealing: annealing conditions is 1200 ℃ of 300 minutes N
2+ 120 minutes O
2
6. phosphorus buries photoetching, corrosion; Carve I
2The phosphorus in L zone buries window, adopts I herein
2The P trap version of L
7. phosphorus buries injection: inject energy 120KeV, implantation dosage 4E14; Impurity is phosphorus, with I
2Phosphorus is injected in zone under the P trap of L.
8. boron buries photoetching, injection: injection zone injects energy 80KeV for the peripheral zone that is used for forming isolation, and implantation dosage 2.4E14, impurity are boron.
9. boron buries annealing: 1200 ℃ of 30 minutes N of annealing conditions
2
10. extension: N type extension, thickness 4 μ m, resistivity 0.7 Ω cm
11.P trap photoetching, injection: injection zone is I
2The base of L, the injection energy is 150KeV, and dosage is 4.5E12, and impurity is boron, and this injects and forms I
2The base of L
12. dark phosphorescence is carved, injected: injection zone is I
2The emitter region of L, the injection energy is 80KeV, and dosage is 8E15, and impurity is phosphorus, and this injects and forms I
2The emitter region of the side direction of L
13. dark phosphorus annealing: 1150 ℃ of 80 minutes N
2
14. isolate photoetching, injection: injection zone is the peripheral zone that is used for forming isolation, and the injection energy is 60KeV, and dosage is 2E15, and impurity is boron, and this injection is buried to form with previous boron and isolated
15. isolate annealing: 1100 ℃ of 40 minutes N
2
16. base photoetching, injection: injection zone is the base of peripheral bipolar device
17. dense boron photoetching, injection: injection zone is I
2L base week makes a circle, and is used for forming I
2The ohmic contact regions of L base.The injection energy is 60KeV, and dosage is 4.5E14, and impurity is boron
18. base annealing: 980 ℃ of 30 minutes N
2This annealing conditions is the annealing conditions of present conventional thin epitaxy shallow base region knot
19. emitter region photoetching, injection: injection zone is I
2The emitter region of L, collector region.The injection energy is 80KeV,
20. dosage is 5E15, impurity is phosphorus, and this injects and forms I
2The collector region of the side direction of L and the ohmic contact of emitter region
21. emitter region annealing: 900 ℃ of 20 minutes N
2
22. contact hole photoetching, corrosion: adopt the method etching of dry method+wet method, to form the surface of good state
A 23. sputtered aluminum: 0.8 μ m Al-Si
24. the pressure point photoetching, etching: carve the pressure point zone
Claims (1)
1. manufacture method that adopts the thin epitaxy shallow junction integrated injection logic of phosphorus-buried technique is characterized in that this method is specific as follows:
A. feed intake: P type, crystal orientation＜100,
B. antimony buries photoetching, corrosion: carve I
2The antimony in L zone buries window,
C. antimony buries injection: inject energy 60KeV, implantation dosage 2.0E15～2.6E15; Impurity is antimony, with I
2L injects antimony in the zone,
D. antimony buries annealing: annealing conditions is 1200 ℃, 300 minutes N
2+ 120 minutes O
2,
E. phosphorus buries photoetching, corrosion: carve I
2The phosphorus in L zone buries window, adopts I herein
2The P trap version of L,
F. phosphorus buries injection: inject energy 130～150KeV, implantation dosage 3.5E14～4.5E14; Impurity is phosphorus, with I
2Phosphorus is injected in zone under the P trap of L,
G. boron buries photoetching, injection: injection zone is the peripheral zone that is used for forming isolation,
H. boron buries annealing: annealing temperature is 1200 ℃, feeds N
2Time be 25～35 minutes,
I. extension: N type extension, thickness 3.5～5.0 μ m, resistivity 0.7～0.8 Ω cm,
The photoetching of j.P trap, injection: injection zone is I
2The base of L, the injection energy is 130～150KeV, and dosage is 3.5E12～5.5E12, and impurity is boron, and this injects and forms I
2The base of L,
K. dark phosphorescence is carved, injected: injection zone is I
2The emitter region of L, the injection energy is 50～70KeV, and dosage is 8E15～1E16, and impurity is phosphorus, and this injects and forms I
2The emitter region of the side direction of L,
L. dark phosphorus annealing: annealing temperature is 1150 ℃, feeds N
2Time be 70～80 minutes,
M. isolate photoetching, injection: injection zone is the peripheral zone that is used for forming isolation, and this injects with previous boron and buries the formation isolation,
N. isolate annealing: annealing temperature is 1100 ℃, feeds N
2Time be 40～50 minutes,
O. dense boron photoetching, injection: injection zone is I
2L base week makes a circle, and is used for forming I
2The ohmic contact regions of L base, the injection energy is 50～70KeV, and dosage is 2.5E14～6.5E14, and impurity is boron,
P. base annealing: annealing temperature is 980 ℃～1000 ℃, feeds N
2Time be 25～35 minutes,
Q. emitter region photoetching, injection: injection zone is I
2The emitter region of L, collector region, the injection energy is 60KeV～80KeV, and dosage is 4E15～6E15, and impurity is phosphorus, and this injects and forms I
2The collector region of the side direction of L and the ohmic contact of emitter region,
R. emitter region annealing: annealing temperature is 880 ℃～910 ℃, feeds N
2Time be 20～30 minutes,
S. contact hole photoetching, corrosion: adopt the method etching of dry method+wet method, with formation surface of good state,
T. a sputtered aluminum: sputter thickness is the Al-Si of 0.6～1.0 μ m,
U. pressure point photoetching, etching: carve the pressure point zone.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4459606A (en) * | 1974-12-27 | 1984-07-10 | Tokyo Shibaura Electric Co., Ltd. | Integrated injection logic semiconductor devices |
| US5016079A (en) * | 1989-11-30 | 1991-05-14 | Honeywell Inc. | Integrated injection logic gate with heavily doped diffusion |
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2008
- 2008-04-29 CN CN200810025560A patent/CN100578756C/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4459606A (en) * | 1974-12-27 | 1984-07-10 | Tokyo Shibaura Electric Co., Ltd. | Integrated injection logic semiconductor devices |
| US5016079A (en) * | 1989-11-30 | 1991-05-14 | Honeywell Inc. | Integrated injection logic gate with heavily doped diffusion |
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Assignee: Fujian Fushun Microelectronic Co., Ltd. Assignor: Wuxi Youda Electronics Co., Ltd. Contract record no.: 2010350000311 Denomination of invention: Technique for preparing thin extensive integrated injection logic using phosphorus-buried technique Granted publication date: 20100106 License type: Exclusive License Open date: 20081001 Record date: 20101223 |