CN100555586C - 减少在氮离子注入时产生多晶硅化金属空洞的方法 - Google Patents

减少在氮离子注入时产生多晶硅化金属空洞的方法 Download PDF

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CN100555586C
CN100555586C CNB2005101296723A CN200510129672A CN100555586C CN 100555586 C CN100555586 C CN 100555586C CN B2005101296723 A CNB2005101296723 A CN B2005101296723A CN 200510129672 A CN200510129672 A CN 200510129672A CN 100555586 C CN100555586 C CN 100555586C
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杨令武
陈光钊
骆统
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Macronix International Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate

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Abstract

一种半导体元件工艺的方法，包含：在晶圆衬底上提供第一层，在该第一层上提供多晶硅层，在该多晶硅层内注入氮离子，在多晶硅层上形成金属硅化物层，以及形成源极/漏极区。

Description

减少在氮离子注入时产生多晶硅化金属空洞的方法
技术领域
本发明涉及一种半导体元件的工艺方法，更具体的说，涉及利用离子注入以消除金属硅化物空隙形成的方法。
背景技术
在现今集成电路中(“ICs”)，为了降低成本，缩小外观大小是一项重要的因素，而存取数据的速度也是同等的重要。记忆型集成电路的速度取决于字线的速度。在半导体产业致力于减小集成电路的大小时，字线的宽度也被缩小了，然而却造成了字线电阻的增大。众所周知，高电阻字线会降低速度，即会使记忆型集成电路速度下降。
因此，为了制造高效能集成电路，低电阻字线是关键所在。在传统金属氧化半导体(“MOS”)集成电路中，多晶硅用于取代铝(Al)当作栅极材料。然而，其缺点是多晶硅比铝拥有更高的电阻，虽然可以用掺杂的方式降低电阻，但是不管掺杂的浓度再高，多晶硅的电阻仍是很大。为了降低电阻，可以在多晶硅上或是在互补性氧化金属半导体晶体管形成后的栅极上沉积一层金属，只有部分沉积到多晶硅层的金属层会和多晶硅作用形成金属硅化物。而形成金属硅化物的过程是会自行校准的，因而称作自行校准硅化技术。通过金属硅化层在多晶硅栅极上的形成，使得金属硅化物电阻明显的降低。常见用于形成金属硅化物结构的金属包含了钛、钨、钼、钴等，然而并不局限于此。
金属硅化物形成后会紧接着高温退火韧化，以更进一步的降低其电阻，然而，快速退火会造成硅原子由多晶硅层扩散到金属硅化物栅极上，这种扩散会在金属硅化物和多晶硅的界面间造成空隙，并对集成电路操作造成不利的影响。
发明内容
本发明提供一种集成电路元件工艺的方法，其包含：在晶圆衬底上覆盖第一层后，再把多晶硅层加在该第一层上，并在该多晶硅层内注入氮离子，再在该多晶硅化物层上形成金属硅化物层，以及形成源极和漏极区域。
此外，本发明还提供集成电路元件工艺的方法，其包含：定义晶圆衬底，将该晶圆衬底上覆上第一层后，在该第一层上覆第二层，并在该第二层内注入氮离子，使该第二层上形成金属硅化物层，在该金属硅化物层上提供光刻胶层，在该光刻胶层上定义图案，将该第二层和该金属硅化物层蚀刻后，至少形成一个栅极，而该栅极上至少有一个侧壁。去除该光刻胶层。注入杂质到该晶圆衬底内，以定义源极和漏极区域，以及沿着该至少一个栅极的侧壁至少形成一个间隙壁。
本发明其它的特色和优点除如下所述外，部分内容在描述中即显而易见，或者也可以在实施本发明时得到，尤其是权利要求中所提出的元件及其组合，更可以理解和达到本发明的特色与优点。
此外，必须了解的是无论是先前的描述或以下的详述，都是范例和说明之用，并不限制权利要求所述的发明。
说明书的附图，阐明了本发明的实施例与描述，用以解释本发明的原则。
附图说明
图1至图4为工艺剖面图，与本发明的实施例一致。
具体实施方式
参考数据将会被详细地列在本发明的实施例内容里，并加以图示说明，而相同的数字指的是图形相同或相似处。
本发明提供一种半导体元件的工艺方法，以减少或去除多晶硅化物空隙的形成。图1至图4为工艺剖面图，与本发明的实施例一致。如图1所示，本发明方法始于定义晶圆衬底10，然后将第一层12覆在晶圆衬底10上。第一层12含有场隔离结构，可由氧化硅层所组成，其功能就像绝缘体。第二层14形成在第一层12之上，可由多晶硅所组成。第二层14形成后，将氮离子16注入其中，以给予导电的特性。氮离子能量在15至50Kev之间，剂量约为1E14至5E14/cm-2。而氩、硅、锗也可以用作掺杂剂。氮离子被注入在距表面不远的多晶硅处，在快速退火后，由于氮离子会延迟晶粒生长，多晶硅将会变成非结晶状态。
注入的氮离子会延迟第二层14多晶硅晶粒生长，因此和传统多晶硅层相比，晶粒大小小了许多。由于晶粒减小的现象明显的降低了甚至预防了之后金属硅化物工艺上硅原子的扩散，因此可减小或消除多晶硅层上的空隙。
一种可参考的清除方式，可以用以移除在第二层14上形成的原生氧化层。稀释的氢氟酸常被用来移除此原生氧化层，以确保第二层14拥有良好的吸附力，使另一层更易覆在其上。
根据图2，将钛或是钨等耐火的金属，沉积在第二层14之上，在退火的步骤后，会形成热稳定的金属硅化物或金属硅化物层18。光刻胶层20再覆在金属硅化物层18之上。图3说明了以传统光刻法定义光刻胶层20上的图形，再蚀刻出由多晶硅层14和金属硅化物层18组成的栅极22，而光刻胶层20则被去除了，而第二次的杂质离子注入24定义出源极和漏极区26。依据先前的技术，杂质的使用是根据不同类型的MOS电晶体来决定的。多晶硅层14和金属硅化物层18在第二次的离子注入是做遮蔽之用，至于源极/漏极的氧化步骤，可以在更进一步的驱使，或扩散掺质进入衬底。
根据图4，间隙壁28沿着栅极22的侧壁形成，这是利用在晶圆衬底10表面上沉积一层氧化物(图上并未画出)，再以干蚀刻或者是热氧化的方式形成。氧化层可由二氧化硅组成，然而在蚀刻的过程中，栅氧化层12可能会有所损伤，尤其是靠近栅极22的转角处，而再氧化步骤可用来修复栅氧化层12，并可以增强栅氧化层12的完整性。
本发明许多其他的修改及润饰可由本领域技术人员实现，而上述的说明和举例只是用于示范性的，其真正的范围和精神将由所附权利要求所述。

Claims (8)

1、一种半导体元件制造方法，其包含：
在晶圆衬底上提供第一层；
在该第一层上提供多晶硅层；
在该多晶硅层上注入氮离子；
移除在该多晶硅层上形成的原生氧化层；
在该多晶硅层上形成金属多晶硅化物层，其中形成该金属多晶硅化物层的步骤包含在该多晶硅层上沉积金属层，并使该多晶硅层退火；
对该金属多晶硅化物层与多晶硅层进行蚀刻以形成栅极；
以及形成源极和漏极区。
2、如权利要求1所述的方法，其中该第一层包含二氧化硅层。
3、如权利要求1所述的方法，其中移除该原生氧化层的步骤包含以稀释的氢氟酸溶液清除。
4、一种半导体元件工艺的方法，包含：
定义晶圆衬底；
在该晶圆衬底上提供第一层；
在该第一层上形成第二层；
在该第二层内注入氮离子；
在该第二层上形成金属硅化物层；
在该金属硅化物层上提供光刻胶层；
定义该光刻胶层图形；
蚀刻该金属硅化物层以及该第二层以至少形成一个栅极，而该栅极至少含有一个侧壁；
移除该光刻胶层；
在所述晶圆衬底中注入杂质以定义源极和漏极；
沿着该栅极的该侧壁形成至少一个间隙壁；以及
形成该至少一个间隙壁后再氧化。
5、如权利要求4所述的方法，还包含清除步骤，以移除该第二层上形成的原生氧化层。
6、如权利要求4所述的方法，其中该第二层包含多晶硅组成。
7、如权利要求4所述的方法，还包含源极/漏极氧化步骤，使该杂质更深入该晶圆衬底。
8、如权利要求4所述的方法，形成该金属硅化物层的步骤包含在该第二层上沉积金属层和该第二层的退火。
CNB2005101296723A 2005-01-28 2005-12-16 减少在氮离子注入时产生多晶硅化金属空洞的方法 Expired - Fee Related CN100555586C (zh)

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CN105047552A (zh) * 2015-08-26 2015-11-11 上海华力微电子有限公司 一种制备金属栅极的方法

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JP3830541B2 (ja) * 1993-09-02 2006-10-04 株式会社ルネサステクノロジ 半導体装置及びその製造方法
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US7009264B1 (en) * 1997-07-30 2006-03-07 Micron Technology, Inc. Selective spacer to prevent metal oxide formation during polycide reoxidation
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