CN100541773C - 电子装置及其制造方法 - Google Patents
电子装置及其制造方法 Download PDFInfo
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- CN100541773C CN100541773C CNB2007101411082A CN200710141108A CN100541773C CN 100541773 C CN100541773 C CN 100541773C CN B2007101411082 A CNB2007101411082 A CN B2007101411082A CN 200710141108 A CN200710141108 A CN 200710141108A CN 100541773 C CN100541773 C CN 100541773C
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- bump electrode
- electronic installation
- electrode
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- 238000009434 installation Methods 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000011241 protective layer Substances 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000000463 material Substances 0.000 claims abstract description 27
- 230000015556 catabolic process Effects 0.000 claims abstract description 20
- 238000006731 degradation reaction Methods 0.000 claims abstract description 20
- 238000002844 melting Methods 0.000 claims abstract description 17
- 150000002739 metals Chemical class 0.000 claims abstract description 10
- 230000008595 infiltration Effects 0.000 claims abstract description 7
- 238000001764 infiltration Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 66
- 239000004065 semiconductor Substances 0.000 claims description 52
- 239000011247 coating layer Substances 0.000 claims description 40
- 239000000945 filler Substances 0.000 claims description 24
- 229910052738 indium Inorganic materials 0.000 claims description 9
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 9
- 238000007772 electroless plating Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 239000003870 refractory metal Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 21
- 239000010931 gold Substances 0.000 description 17
- 230000004888 barrier function Effects 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 238000007747 plating Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 230000007850 degeneration Effects 0.000 description 5
- 230000008018 melting Effects 0.000 description 5
- 230000035882 stress Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- 230000006835 compression Effects 0.000 description 4
- 238000007906 compression Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052763 palladium Inorganic materials 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 208000034189 Sclerosis Diseases 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 239000003960 organic solvent Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 238000006722 reduction reaction Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 208000037656 Respiratory Sounds Diseases 0.000 description 1
- 229910020836 Sn-Ag Inorganic materials 0.000 description 1
- 229910020988 Sn—Ag Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000002180 anti-stress Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000005494 tarnishing Methods 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
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Abstract
本发明公开了一种电子装置及其制造方法。该电子装置包括凸点电极和保护层,该凸点电极由低熔点的单质金属形成,并且电连接第一元件和第二元件,而该保护层至少形成在凸点电极的侧面上,并且阻止使凸点电极特性退化的物质的渗入。
Description
技术领域
本发明涉及一种其具有由凸点电极(bump electrode)形成的接合部的电子装置,更特别地,涉及一种可以防止凸点电极退化并且改善电子装置的可靠性的电子装置及其制造方法。
背景技术
在以如移动电话的移动产品为代表的电子设备中,强烈地需要增加集成度、减小尺寸以及改善性能。为了满足这些需要,广泛采用了通过凸点电极将半导体芯片连接到安装基板或者另一个半导体芯片上的倒装芯片连接。有必要降低布线延迟(RC delay)以实现速度增加。当低电阻的铜布线和低介电常数(k)的低介电膜(low-k)用作层间绝缘膜时,作为低损耗封装技术,采用了通过使用低熔点焊接凸点电极来进行的熔接结合(fusion bonding)。为了保证通过倒装芯片连接所制造的结合产品中电连接对各种应力的可靠性,通常将底填料(under-fill material)填充在结合表面之间的间隙中。
在半导体装置中,采用了具有低热阻且由于受热而倾向于引起特性退化的基板材料,为了防止在其制造工艺中引起的特性的退化,尽可能采用低温工艺。例如,对于基板的电连接,有这样一种技术,采用铟(In)作为无铅凸点电极材料在半导体芯片上形成In凸点电极,并且通过In凸点电极倒装芯片连接半导体芯片。因为In凸点电极由低熔点金属制造,所以具有能够低温连接的优点。在过去用In凸点电极封装半导体芯片时,焊盘电极形成在上、下半导体芯片中,Ni层形成在焊盘电极上,In凸点电极形成在Ni层上,而上、下半导体芯片倒装芯片连接以将其结合。
图4A和4B是说明现有技术中通过In凸点电极结合基板的剖面图。
如图4A所示,上基板10具有由绝缘层25彼此电隔离的形成在焊盘电极15上的In凸点电极30,并且通过In凸点电极30由倒装芯片连接电连接到下基板20。
随后,如图4B所示,为了保护通过In凸点电极30的上基板10和下基板20之间的电连接并且确保结合产品的可靠性,底填料35作为密封材料填充在上基板10和下基板20之间的间隙中并且被硬化。
下面报告稍后将描述的混合成像装置和混合红外线传感器等,作为采用In凸点电极的半导体装置。介绍作为制造In凸点电极的方法的几种方法。
在标题为“Semiconductor Device and Method of Manufacturing theSemiconductor Device”的JP-A-9-82757(参见0003至0005段和图2)和标题为“Flexible Substrate and Semiconductor Device”的JP-A-2004-200196(参见0008和0009段、0013和0014段以及图1)中,有下面的描述。
图5A和5B是说明凸点电极连接的示意图。图5A对应于JP-A-9-82757中的图2,并且是说明混合型成像元件的主件结构的示意图,而图5B对应于JP-A-2004-200196中的图1,并且是示出COF(Chip On Flexible Substrate-柔性基板上芯片)结构的示意性结构的剖面图。
如图5A所示,在JP-A-9-82757所揭示的成像装置111中,在其上形成有大量光电转换元件的检测元件113安装在其上形成有信号处理电路的电路元件112上。大量光电转换元件的电极形成在检测元件113的下表面上,并且大量电极形成在电路元件112的上表面上,它们通过含有铟作为主成分的凸点电极连接。通常,焊盘114通过剥离(lift-off)法形成在电路元件112或检测元件113的预定部分中。电路元件112和检测元件113随同夹置于这些元件之间的凸点电极114被施压并被加热到凸点电极114到熔化温度以被连接。
JP-A-2004-200196中所揭示的半导体装置包括包含凸点电极和柔性基板的IC芯片,该凸点电极上形成有Cu、Ni、Al、Ti、Au或Pd的表面膜,在柔性基板上提供了经电镀Au、Cu、Ni或Pd的引线端子或者仅由引线材料形成的引线端子,并且凸点电极压接到引线端子上。因此,采用除Au以外的金属作为凸点电极的表面材料可以将凸点电极压接到引线端子上。因此,能够实现降低COF结构的成本。
在图5B中,引线端子102提供在柔性基板101上。引线端子102包括涂有Au镀覆层102b的Cu基板层102a。另一方面,凸点电极104提供在IC芯片103上。在凸点电极104中,除Au以外的金属镀覆层104b涂敷在除Au以外金属的金属核104a之上。这里,作为金属核104a的材料,可以使用例如Cu、Ni或Pd。作为金属镀覆或者膜层104b,可以使用例如Cu、Ni、Al或Pd。
可以通过将凸点电极104压接在引线端子102上来将IC芯片103装配到柔性基板101上。因此,当凸点电极104压接到引线端子102时,可以使用除Au以外的金属作为凸点电极104的材料。因此,可以实现降低COF结构的成本。
在Nishino等人的FUJITSU,56,p.352-357(2005)标题为“Quantum WellInfrared Photodetecto”(“Summary”,“QWIP-FPA and Optical CouplingStructure”,and Fig.3)中,有下面的描述。
采用III-V族半导体开发了量子阱红外线光电探测器(QWIP),其吸收通过不同能带隙的半导体的层叠结构所形成的量子阱中量子化能级之间的红外线。实现了通过混合QWIP和带有铟凸点电极的Si信号读出电路而获得的大尺寸二维阵列(QWIP-焦平面阵列(QWIP-FPT))。在实际的红外线照相机中所采用的QWIP红外线光电探测器包括QWIP二维阵列和Si信号读出电路,在该QWIP二维阵列中QWIP元件以二维阵列形状排列,而Si信号读出电路以时间序列读出各个像素的信号。QWIP红外线光电探测器采用了一种混合结构,其中各QWIP元件逐一地由铟(In)的凸点电极(连接像素的柱形电极)结合到Si信号读出电路。
发明内容
在室温下是稳定的固体金属中,铟(In)是最软的。In通过压缩基本上是无限地变形,熔点低至156.4℃,并且没有相变。因此,在需要以低温工艺制造的半导体装置中,或者倾向于由于热循环引起应力并且有必要释放该应力的半导体装置中,当半导体芯片基板结合到安装基板或者另一个半导体芯片基板上时,In用作例如凸点电极(突出电极)的材料,形成在半导体芯片的焊盘电极上。
因为In凸点电极具有低熔点,所以当结合基板时,可以减少对基板材料和形成半导体装置的元件的热影响。此外,能够缓和作用在接合部上的应力。然而,当出现湿气时,In倾向于锈蚀。考虑到接合部的可靠性,有必要考虑针对湿气的出现的抗湿气性。在过去,抗湿气性没有得到充分的考虑。
如图4B所示,在通过In凸点电极倒装芯片连接后,通常将称为底填料的环氧树脂等被注入上下基板之间的间隙中并且硬化,以保证连接产品的可靠性。与焊接金属如Sn相比,当In与湿气(H2O)进行接触时In容易腐蚀。如图4B所示,因为底填料35和In凸点电极30彼此直接接触,所以由于从外面透入底填料35中的湿气的影响,In凸点电极30出现腐蚀。因此,在高温高湿度试验(85℃/85%RH)等的可靠性评估中,In凸点电极与其他焊接金属制造的凸点电极相比就抗湿性方面而言可靠性低。
在其上形成有In凸点电极的半导体芯片中,例如,事先通过形成金镀覆层和用金镀覆层涂敷In凸点电极能够保护In凸点电极。然而,当上下半导体芯片结合时,必须设定结合温度,以等于或者高于金的熔点1063℃,并且使金镀覆层变为熔化状态。这不符合于使用In凸点电极以实现低温工艺的目的。此外,可能的是In凸点电极暴露在高温下,并且使In凸点电极的氧化更糟。
作为实例上面说明了采用In凸点电极的半导体装置。然而,不仅在在第一和第二元件通过凸点电极结合的半导体装置中而且在电子装置中,凸点电极的特性退化,例如,电特性(导电率、电阻等)、机械特性(抗拉强度、抗压强度等),引起采用凸点电极的电子装置的可靠性退化。这导致电子装置的经久性寿命缩短。因此,存在阻止凸点电极特性退化的强烈需求。
因此,希望提供一种电子装置及其制造方法,其可以防止具有通过凸点电极形成的接合部的电子装置的凸点电极的退化,并且可以改善电子装置的可靠性。
根据本发明的实施例,提供有一种电子装置包括凸点电极和保护层,该凸点电极由具有低熔点的单质金属形成,并且电连接第一元件和第二元件,而该保护层至少形成在该凸点电极的侧面上,并且阻止使该凸点电极特性退化的物质渗入。
根据本发明的另一个实施例,提供一种制造电子装置的方法包括第一步骤和第二步骤,第一步骤使用具有低熔点的单质金属形成的凸点电极电连接第一元件和第二元件,而第二步骤至少在该凸点电极的侧面形成保护层,其阻止使该凸点电极特性退化的物质的渗入。
在根据本发明实施例的电子装置中,阻止使凸点电极特性退化的物质渗入的保护层至少形成在凸点电极的侧面上。因此,可以阻止使特性(电特性,如导电率和电阻,以及机械特性,如抗拉强度和抗压强度等)退化的物质的渗入,这发生在电子装置所处的环境下。因此,可以阻止凸点电极的特性的退化,改善电子装置的可靠性,并且实现电子装置的经久性寿命的延长。
在根据本发明实施例的电子装置的制造方法中,阻止使凸点电极特性退化的物质渗入的保护层至少形成在凸点电极的侧面上。因此,保护层防止了发生在电子装置所处环境下的使特性退化的物质的渗入。防止了凸点电极的特性退化。因此,可以制造可靠性改善的电子装置。
在根据本发明实施例的电子装置中,优选分别形成在第一元件和第二元件上的焊盘电极由凸点电极电连接,并且保护层形成来防止凸点电极暴露到外面。保护层形成来防止凸点电极的表面暴露到外面,该凸点电极分别电连接形成在第一和第二元件上的焊盘电极。凸点电极的侧面涂敷有保护层。因此,在电子装置所处的各种环境下,例如在高湿度的环境和倾向于产生腐蚀气体的环境下,该保护层用作湿气渗入防止层(使得水蒸气和水不容易通过的层)和防腐防止层(抗腐蚀层)。因此,形成凸点电极的单质金属可以保持单质金属的固有特性。因此,可以改善电子装置的可靠性。
优选保护层形成在凸点电极的侧面上。凸点电极所有暴露到外面的侧面都涂敷有保护层。保护凸点电极不接触使凸点电极特性退化的物质(下文中简称特性退化物质)。
优选一部分焊盘涂敷有保护层。因为凸点电极和焊盘电极的接合部也涂敷有保护层,所以也防止接合部受到特性退化物质的影响。
优选凸点电极由单质铟金属形成。利用单质铟金属中的固有特性可以获得这样的电子产品,其具有低熔点接合部,可以进行低温工艺,并且在弹性和耐应力方面优秀。
优选保护层由具有高熔点的金属形成。甚至当电子装置所处的环境温度升高到接近形成凸点电极的单质金属的熔点时,因为保护层没有达到熔化状态,所以保护层保护了凸点电极。
优选在第一元件和第二元件之间的间隙填充焊底填充材料。因为凸点电极涂敷有保护层,所以填充在间隙中的底填料保护凸点电极不受外部环境的影响而不与凸点电极直接接触。换言之,凸点电极受到保护层和底填料双重保护。即使存在特性退化物质(例如,环境中的湿气)从外部进入焊底填充材料并且接近凸点电极,特性退化物质被保护层阻断,并且凸点电极得到针对特性退化物质的保护。因此,可以防止由于特性退化物质而退化,并且可以改善电子装置的可靠性。
优选第一元件为第一半导体芯片,而第二元件为第二半导体芯片或安装基板。优选安装基板是间插基板(interposer substrate)或母板基板(motherboard substrate)。这可以改善其中半导体芯片和间插基板或母板基板结合使用的电子装置的可靠性。
优选电子装置构成半导体装置。可以改善半导体芯片通过凸点电极结合并且用作元件的半导体装置的可靠性。
在根据本发明实施例的电子装置的制造方法中,优选该方法包括在第一元件和第二元件之间的间隙中填充底填料的第三步骤。通过在间隙中填充底填料可以制造具有由保护层和底填料双重保护的凸点电极的电子装置。
优选在第二步骤中,具有高熔点的金属镀覆层形成为保护层。优选镀覆层由无电镀形成。可以根据镀覆层的形成时间适当调整镀覆层的厚度。由凸点电极电连接的焊盘电极的暴露部分与凸点电极的侧面一起涂敷有镀覆层。凸点电极和焊盘电极的接合部也涂敷有镀覆层。因此,该接合部也对特性退化物质得到了保护。
在本发明的实施例中,“低熔点”意味着熔点等于或者低于200℃,而“高熔点”意味着温度超过形成凸点电极的单质金属的熔点,即熔点超过200℃。高熔点设置成保持保护层的性能,这是因为,如果具有高熔点的金属在结合时的温度达到熔化状态并且保护层破裂,则损坏了保护层的性能。优选保护层由起到具有抗锈蚀性的抗锈蚀层和具有抗湿气渗透性的湿气渗透防止层作用的金属形成。“凸点电极的特性”指凸点电极的如导电率和电阻的电特性和如抗拉强度和抗压强度等的机械特性。
附图说明
图1A至1C是说明根据本发明实施例通过In凸点电极连接基板所形成的半导体装置的剖面图;
图2是说明根据本发明实施例通过In凸点电极连接基板的程序的流程图;
图3是说明通过In凸点电极连接基板所形成的半导体装置的接合部的尺寸的剖面图。
图4A和4B是说明通过采用现有技术的In凸点电极进行基板连接的剖面图;和
图5A和5B是说明现有技术中由In凸点电极的连接的示意图。
具体实施方式
在下文,将参照附图详细说明本发明的实施例。在下面的说明中,作为电子装置的实例将说明一种半导体装置,在该半导体装置中半导体芯片通过凸点电极结合为元件。
在根据该实施例的半导体装置中,倒装芯片连接其上形成有In凸点电极的半导体芯片基板。随后,在半导体芯片基板之间的间隙中填充底填料之前,In凸点电极和其上形成有In凸点电极的焊盘电极(由Cu或者Ni层形成)覆盖有除In以外的金属的金属镀覆层,例如通过无电Au镀覆得到的Au金镀覆层。然后底填料填充在间隙中并硬化。因此,可以防止In凸点电极与湿气的直接接触,并且显著改善由可靠性试验评估的耐用寿命,该试验例如是高温高湿度试验。因此,可以改善由具有In凸点电极的倒装芯片结构形成的半导体装置的可靠性。
在该实施例中,可以实现通过采用In凸点电极所完成的倒装芯片安装,该In凸点电极可以利用In凸点电极柔软且具有低熔点的特性,并且可以改善防潮性能从而与其他种类的无铅焊料的防潮性能一样高,而在过去,In凸点电极的防潮性能很低。
因为In凸点电极柔软,所以不容易由于外力而形成裂纹。In凸点电极具有抗裂性,并且在抗应力方面是优秀的。因为In凸点电极具有低熔点,所以在低温下的倒装芯片连接是可能的,而不容易产生热应力,并且半导体芯片基板或者安装基板作为要结合的元件不被热损坏。因此,可以按照低温工艺制造半导体装置。
图1A至1C是说明根据该实施例通过In凸点电极30结合基板10和20所形成的半导体装置50的剖面图。图1A是示出基板的倒装芯片连接的示意图,图1B是示出In凸点电极30和焊盘电极15的镀金表面的示意图,而图1C是示出底填料35填充的示意图。
图2是说明在半导体装置50中通过In凸点电极30结合基板10和20的过程的流程图。
In凸点电极30形成在上基板10或下基板20的焊盘电极15上。上基板10和下基板20倒装芯片连接。在该实施例中,假设In凸点电极30形成在上基板10的焊盘电极15上。
在该倒装芯片连接之前,如图2的步骤S1所示,在金镀覆层40的形成中形成掩模层(在图1A至1C和图3中未示出)。该掩模层以厚度约为1μm的抗蚀剂层在除了形成在上基板10的In凸点电极30和焊盘电极15之外的表面上形成。该掩模层以厚度约为1μm的抗蚀剂层在除了形成在下基板20上的焊盘电极15之外的表面上形成。该抗蚀剂层采用易于由有机溶剂去除的材料形成。在上基板10和下基板20倒装芯片连接后,该抗蚀剂层用有机溶剂去除。
如图2中的步骤S2所示,上基板10通过In凸点电极30的倒装芯片连接电连接到下基板20,如图1A所示。
在图1A至1C所示的实例中,上基板10是半导体芯片基板,具有形成在其焊盘电极15上的In凸点电极30。下基板20是半导体芯片基板,具有形成在其上的焊盘电极15。形成在上基板10和下基板20上的焊盘电极15通过倒装芯片连接而电连接。也可以提供安装基板以代替下基板20的半导体芯片基板。
在上基板10的焊盘电极15上所形成的In凸点电极30的外形可以是任意形状,例如圆冠型或者柱形。In凸点电极30可以通过凸点电极底金属层连接到形成在上基板10上的焊盘电极15。
进行这样的设置,In凸点电极30形成在焊盘电极15上,用绝缘层25使它们彼此电隔离,且形成在上基板10上,并且焊盘电极15形成在下基板20上。对上基板10和下基板20进行热控制和负荷控制。因此,连接上基板10和下基板20,且在上基板10和下基板20之间保持希望的间隙(例如,20μm至50μm)。
如上所述,在上基板10和下基板20倒装芯片连接后,用有机溶剂去除抗蚀剂层。
必要时,执行稍后描述的步骤S4,以清洗上基板10和下基板20之间的间隙的内部。
在上基板10和下基板20之间的间隙中填充底填料35之前,如图2中的步骤S3所示,对In凸点电极30和焊盘电极15的表面进行金镀覆。换言之,金镀覆层40形成在In凸点电极30的暴露表面(没有与焊盘电极1 5结合的表面)和焊盘电极15的暴露表面(没有与In凸点电极30结合的表面)上(见图1B)。
采用金属之间的化学置换反应通过在表面上形成金膜的置换镀覆,或者采用金属之间的化学还原反应通过在表面上沉积金以形成膜的还原镀覆,来形成金镀覆层40。
通过将倒装芯片连接的上基板10和下基板20沉浸在例如置换镀覆液中来进行无电镀。形成在In凸点电极30侧面(外表面)上的金镀覆层40的厚度为0.01μm至1μm,例如0.05μm。当金镀覆层40太薄时,作为形成金镀覆层40目的的保护In凸点电极30的性能不足。另一方面,当金镀覆层40太厚时,形成镀覆层所需时间和成本增加。
如图1B所示,金镀覆层40通过镀覆形成在金属部分的表面上,即In凸点电极30和焊盘电极15的表面。In凸点电极30和焊盘电极15的表面涂敷有金镀覆层40,并且In凸点电极30与湿气隔离且提供抗湿气的保护。
除了Au镀覆层,还可以形成熔点高于铟的金属镀覆层。例如,在抗湿气性方面比In更优秀的金属层例如Sn或Ni层可以由无电镀形成,以覆盖In凸点电极30和焊盘电极15。
上基板10和下基板20之间的间隙通过清洗(使用纯水)和干燥来清洗,如图1C和图2中的步骤S4所示。通过给间隙提供加压水流并清洗间隙的喷水法或者给间隙提供带有低频振荡的加压水流以清洗间隙的超振荡法来清洗上基板10和下基板20之间的间隙。
当省略上述步骤S1时,在In凸点电极30上形成金镀覆层40中,金镀覆层40可以粘附到绝缘层25的表面。因为金镀覆层40粘附到绝缘层25的强度不大,所以在清洗中粘附到绝缘层25的金镀覆层40被剥离和冲走,并且清洗了绝缘层25。
如图1C和图2中的步骤S5所示,为了保护在结合产品中通过In凸点电极30的上基板10和下基板20的接合部并且保证结合产品的可靠性,底填料35作为密封材料填充在上基板10和下基板20之间的间隙中并硬化。
在具有In凸点电极30和焊盘电极15涂敷有金镀覆层40的连接结构的所连接的元件中,可以实现一种结构,其中通过在上基板10和下基板20之间的间隙中注入底填料35,In凸点电极30和底填料35彼此不直接接触,如图1C所示。
结果,底填料35覆盖了涂敷In凸点电极30和焊盘电极15表面的金镀覆层40。因此,In凸点电极30和焊盘电极15的表面不直接接触底填料35,并且不暴露于湿气,且可以控制In凸点电极30上的湿气影响。因此,因为In凸点电极30不被锈蚀,所以可以改善通过In凸点电极30的基板的结合产品的可靠性,并且改善采用该连接产品的半导体装置的可靠性。
根据该实施例,可以实现采用In凸点电极所实现的倒装芯片安装,其可以改善抗湿气性从而具有与无铅焊料如Sn-Ag焊料和Sn焊料一样高的抗湿气性。
如上所述,可以省略步骤S1。不必说,金镀覆层40可以由电解镀形成。
当半导体装置设置在密闭的空间中时,其中填充有干燥状态的如大气的中性物,也可以省略在间隙中填充底填料而不执行步骤S5。
图3是包括接合部放大图的剖面图,用于说明通过In凸点电极30结合基板10和20所形成的半导体装置的接合部尺寸的实例。
图3示出了接合部的剖面图和放大剖面图,其状态为其中执行了上基板10和下基板20通过In凸点电极30的电连接,在焊盘电极15和In凸点电极30的暴露表面上形成金镀覆层40,并且在上基板10和下基板20之间的间隙中填充底填料35。
在图3中,“g”表示在上基板10和下基板20之间结合的间隙,而“t”表示金镀覆层40的厚度。在上基板10和下基板20通过焊盘电极15电连接后,且在底填料35填充在间隙中之前,金镀覆层40形成在焊盘电极15和In凸点电极30暴露在间隙“g”中的侧面(外周表面)上。
在图3所示的实例中,示出了通过倒装芯片连接结合上基板10和下基板20的状态。在上基板10上,In凸点电极形成在半径为15μm的圆形焊盘电极15上,该In凸点电极具有球冠作为其外部形状,其底半径为15μm,高为23μm。在下基板20上,形成有半径为15μm的圆形焊盘电极15。这里,g=13μm,而t=0.05μm。
在上面的说明中,说明了在In凸点电极的侧面上形成Au镀覆层的实例。然而,凸点电极由低熔点的单质金属形成且保护层由高熔点的金属形成,这就足够了。例如,为了形成防锈层,镀覆层可以由除Au以外的稀有金属形成以代替Au镀覆层。
在上面的说明中,In凸点电极30形成在上基板10的焊盘电极15上。然而,也可以省略步骤S3,这通过在形成圆冠形状的In凸点电极30的外形之后,在焊盘电极15和In凸点电极30所暴露的外表面上形成金镀覆层40,靠近In凸点电极30的圆冠形状的顶点处选择性地蚀刻金镀覆层40,以从上基板10的绝缘层25的表面在与图3所示的间隙“g”相同高度处留下的部分金镀覆层40,并且暴露靠近In凸点电极30顶点的部分,从而可以结合上基板10和下基板20。
已经说明了本发明的实施例。然而,本发明不限于该实施例,基于本发明技术概念的各种修改是可能的。
如上所说明,本发明适合于需要低温工艺制造的电子装置,并且能够提供了防止凸点电极特性的退化来改善可靠性的半导体装置。
本领域的技术人员应该理解的是,在权利要求的范围或其等同特征的范围内,根据设计要求和其他因素可以进行各种修改、结合、部分结合和改造。
Claims (12)
1、一种电子装置,包括:
凸点电极,由具有低熔点的单质金属形成,并且电连接第一元件和第二元件;和
保护层,至少形成在该凸点电极的侧面上,并且阻止使该凸点电极特性退化的物质的渗入,其中该保护层由具有高熔点的金属形成。
2、根据权利要求1所述的电子装置,其中分别形成在该第一元件和第二元件上的焊盘电极通过该凸点电极电连接,并且该保护层形成来防止该凸点电极被暴露在外面。
3、根据权利要求2所述的电子装置,其中该保护层形成在该凸点电极的侧面上。
4、根据权利要求2所述的电子装置,其中该焊盘电极的一部分涂敷有该保护层。
5、根据权利要求1所述的电子装置,其中该凸点电极由单质铟金属形成。
6、根据权利要求1所述的电子装置,其中底填料填充在该第一元件和该第二元件之间的间隙中。
7、根据权利要求1所述的电子装置,其中该第一元件是第一半导体芯片,而该第二元件是第二半导体芯片或安装基板。
8、根据权利要求7所述的电子装置,其中该安装基板是间插基板或母板基板。
9、根据权利要求1所述的电子装置,其中该电子装置组成半导体装置。
10、一种制造电子装置的方法,包括如下步骤:
采用由低熔点的单质金属形成的凸点电极电连接第一元件和第二元件;并且
至少在该凸点电极的侧面上形成阻止使该凸点电极的特性退化的物质渗入的保护层;
其中在形成保护层的步骤中,形成高熔点金属的镀覆层作为该保护层。
11、根据权利要求10所述的制造电子装置的方法,还包括在该第一元件和该第二元件之间的间隙中填充底填料的步骤。
12、根据权利要求10所述的制造电子装置的方法,其中该镀覆层由无电镀形成。
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US5523628A (en) * | 1994-08-05 | 1996-06-04 | Hughes Aircraft Company | Apparatus and method for protecting metal bumped integrated circuit chips during processing and for providing mechanical support to interconnected chips |
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