CN100539035C - The new caustic solution of semiconductor integrated circuit silicon single crystal flake substrate back silicon nitride layer - Google Patents
The new caustic solution of semiconductor integrated circuit silicon single crystal flake substrate back silicon nitride layer Download PDFInfo
- Publication number
- CN100539035C CN100539035C CN 200410066298 CN200410066298A CN100539035C CN 100539035 C CN100539035 C CN 100539035C CN 200410066298 CN200410066298 CN 200410066298 CN 200410066298 A CN200410066298 A CN 200410066298A CN 100539035 C CN100539035 C CN 100539035C
- Authority
- CN
- China
- Prior art keywords
- single crystal
- layer
- crystal flake
- silicon single
- sin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Weting (AREA)
- Semiconductor Memories (AREA)
Abstract
The caustic solution of semiconductor integrated circuit silicon single crystal flake substrate back silicon nitride layer, may further comprise the steps: (1) is provided with the silicon single crystal flake substrate; (2) deposited oxide grid material on the silicon single crystal flake substrate; (3) deposit polysilicon layer; (4) form silicon nitride (SiN) protective layer on the silicon single crystal flake top surface He on the back side; (5) form silicon dioxide (SiO on silicon nitride (SiN) layer that forms on the silicon single crystal flake top surface
2) layer; (6) with phosphoric acid (H
3PO
4) wet corrosion removes silicon nitride (SiN) layer on the silicon single crystal flake substrate back; (7) remove silicon dioxide (SiO on silicon nitride (SiN) layer of silicon single crystal flake top surface with hydrofluoric acid (HF) corrosion
2) layer, silicon nitride (SiN) layer of reservation top surface.
Description
Technical field
The present invention relates to the manufacture method of semiconductor integrated circuit, be specifically related to the new caustic solution of semiconductor integrated circuit silicon single crystal flake substrate back silicon nitride layer.
Background technology
Existing, for example, the manufacture method of the semiconductor integrated circuit of semiconductor memory may further comprise the steps:
(1) the silicon single crystal flake substrate is set; (2) deposit gate oxide on the silicon single crystal flake substrate; (3) deposit polysilicon layer (polysilicon) layer on gate oxide; (4) the silicon single crystal flake substrate that is deposited with polysilicon layer forms silicon nitride (SiN) protective layer in low pressure chemical vapor deposition (LPCVD) stove; (5) remove silicon nitride (SiN) protective layer of silicon single crystal flake substrate back; Carry out photoetching composition then, form processing steps subsequently such as gate figure.
The purpose that forms silicon nitride (SiN) protective layer is, prevents that grid material is corroded in the lithography corrosion process step of carrying out subsequently, and the silicon nitride on the silicon single crystal flake top surface (SiN) protective layer is a needed etch stop layer in the technology of carrying out subsequently.But; must remove silicon nitride (SiN) protective layer of silicon single crystal flake substrate back; its reason is; the silicon nitride of silicon single crystal flake substrate back (SiN) protective layer can cause very big stress; big stress can make silicon single crystal flake substrate warpage (wrap), causes that the optics critical size of semiconductor integrated circuit changes, thereby causes waste product; reduce product percent of pass, caused total manufacturing cost height of semiconductor integrated circuit.
In the manufacture method of conventional semiconductor memory, need with special silicon single crystal flake substrate back silicon nitride (SiN) layer etching apparatus, remove silicon nitride (SiN) layer of silicon single crystal flake substrate back, single-chip back side silicon nitride (SiN) the layer etching apparatus of this special use costs an arm and a leg, thereby, cause total manufacturing cost height of semiconductor memory.
Summary of the invention
In order to overcome the shortcoming that exists in the above-mentioned prior art the present invention is proposed.The objective of the invention is, propose the new caustic solution of a kind of semiconductor integrated circuit silicon single crystal flake substrate back silicon nitride (SiN) layer.
According to a technical scheme of the present invention, the back side silicon nitride (SiN) of semiconductor integrated circuit wafer substrates layer corrosion new method may further comprise the steps:
(1) the silicon single crystal flake substrate is set; (2) deposit gate oxide on the silicon single crystal flake substrate; (3) deposit polysilicon layer (polysilicon) on the oxide gate material; (4) on the silicon single crystal flake substrate behind the deposit polysilicon layer, in low pressure chemical vapor deposition (LPCVD) stove, on polysilicon layer, form silicon nitride (SiN) protective layer; (5) form silica (SiO with chemical vapor deposition (CVD) on silicon nitride (SiN) protective layer that forms on the silicon single crystal flake top surface
2) protective layer; (6) then singualtion chemical vapor deposition (CVD) on the silicon nitride on the silicon single crystal flake top surface (SiN) protective layer is formed with silicon dioxide layer (SiO
2) protective layer, and silicon nitride (SiN) layer that has only the silicon single crystal flake substrate back to form is exposed in the environment, will have this structure is that the silicon single crystal flake lining immerses phosphoric acid (H
3PO
4) in the etching tank, with phosphoric acid (H
3PO
4) silicon nitride (SiN) layer on the wet corrosion silicon single crystal flake substrate back; remove silicon nitride (SiN) layer of silicon single crystal flake substrate back, can not be owing to be deposited with on silicon nitride (SiN) protective layer on the silicon single crystal flake top surface by the silicon dioxide layer (SiO of phosphoric acid corrosion
2), so at silicon dioxide layer (SiO
2) protection under, kept silicon nitride (SiN) protective layer on the silicon single crystal flake top surface; Carry out the subsequent technique of semiconductor integrated circuit manufacture method then.Etch stop layer in silicon nitride on the silicon single crystal flake top surface (SiN) the layer conduct technology of carrying out subsequently, the silicon dioxide layer (SiO that forms on the silicon nitride on the silicon single crystal flake top surface (SiN) layer
2) can in hydrofluoric acid (HF) etching process subsequently, be removed.
New caustic solution according to silicon single crystal flake substrate back silicon nitride of the present invention (SiN) layer, do not need special-purpose etching apparatus to corrode silicon single crystal flake substrate back silicon nitride (SiN) layer, only need on silicon nitride (SiN) layer of silicon single crystal flake top surface, form silicon dioxide layer (SiO by singualtion chemical vapor deposition (CVD)
2), make on silicon nitride (SiN) layer that forms on the silicon single crystal flake top surface to be formed with silicon dioxide (SiO
2) the protection cover layer, and silicon single crystal flake substrate back silicon nitride (SiN) layer is exposed in the environment, the single-chip substrate member immersion temperature range that will have this structure is 150 ℃ to 165 ℃ phosphoric acid (H
3PO
4) carry out wet corrosion in the etching tank, because phosphoric acid (H
3PO
4) corroding silicon nitride (SiN) layer and do not corrode silicon dioxide layer (SiO
2), so, can use phosphoric acid (H commonly used in the semiconductor integrated circuit manufacturing process
3PO
4) wet corrosion technology simply and is easily removed silicon single crystal flake substrate back silicon nitride (SiN) layer, and the silicon nitride of silicon single crystal flake top surface (SiN) layer is at silicon dioxide layer (SiO
2) protection under be retained, the silicon nitride of silicon single crystal flake top surface (SiN) layer is at silicon dioxide layer (SiO
2) silicon dioxide layer (SiO in hydrofluoric acid (HF) etching process subsequently on silicon nitride (SiN) layer of silicon single crystal flake top surface
2) be corroded, because therefore hydrofluoric acid (HF) corroding silicon nitride (SiN) layer has not kept silicon nitride (SiN) layer as the silicon single crystal flake top surface of the etch stop layer in technology subsequently.
Do not need expensive special-purpose etching apparatus to remove silicon nitride (SiN) layer on the silicon single crystal flake substrate back by method of the present invention, and, phosphoric acid (H
3PO
4) wet corrosion and hydrofluoric acid (HF) etching process all be the general technology of semiconductor integrated circuit, not needing increases processing step in addition, thereby has simplified technology, has reduced total manufacturing cost of semiconductor integrated circuit.
Description of drawings
Accompanying drawing is included in the specification, book component part as an illustration, demonstrate the preferred embodiments of the present invention in the accompanying drawing, the word segment one of accompanying drawing and specification is used from explanation principle of the present invention and feature, and all identical part is indicated with identical numeral in the accompanying drawing.Wherein:
Fig. 1 is the processing step schematic diagram of existing silicon single crystal flake substrate back silicon nitride (SiN) layer caustic solution: and
Fig. 2 is the processing step schematic diagram according to the new caustic solution of silicon single crystal flake substrate back silicon nitride of the present invention (SiN) layer.
The description of contents that designation number in the accompanying drawing is indicated:
Accompanying drawing 1:
1) the single-chip nitride of LPCVD (low pressure chemical vapor deposition) method deposit;
2) the operation back layer is removed instrument and is removed back side nitride;
The 1-silicon wafer; The 2-grid material; The 3-nitride layer.
Accompanying drawing 2:
1) nitride of LPCVD (low pressure chemical vapor deposition) method deposit;
2) the single-chip top surface forms oxide skin(coating) with the CVD method;
3) with phosphoric acid (H
3PO
4) soak, remove the nitride layer at the single-chip back side, the nitride layer on the single-chip top surface is subjected to the protection of oxide skin(coating);
4) hydrofluoric acid dips is removed the oxide skin(coating) that the CVD method on the single-chip top surface forms;
The 1-silicon wafer; The 2-grid material; The 3-nitride layer; The 4-oxide skin(coating).
Embodiment
Fig. 1 is the processing step schematic diagram of existing silicon single crystal flake substrate back silicon nitride (SiN) layer caustic solution.
Referring to Fig. 1, existing silicon single crystal flake substrate back silicon nitride (SiN) layer caustic solution may further comprise the steps: deposit grid material on the silicon single crystal flake substrate; The silicon single crystal flake substrate that is deposited with grid material on it is placed in low pressure chemical vapor deposition (LPCVD) stove, all form silicon nitride (SiN) protective layer on the top surface of silicon single crystal flake substrate and the back side, the silicon nitride on the top surface (SiN) protective layer is as the etch stop layer in the technology of carrying out subsequently; Because, the silicon nitride that forms on the back side of silicon single crystal flake substrate (SiN) layer can cause big stress, this big stress causes the silicon single crystal flake substrate warpage, the optics critical size of semiconductor integrated circuit is changed, cause semiconductor integrated circuit waste product to occur, so, must remove silicon nitride (SiN) layer that forms on the silicon single crystal flake substrate back, the method of removing of back side silicon nitride (SiN) layer of now general silicon single crystal flake substrate is, with special silicon single crystal flake substrate back silicon nitride (SiN) layer etching apparatus wet etching, only remove silicon nitride (SiN) layer that forms on the back side of silicon single crystal flake substrate.Remove special-purpose silicon single crystal flake substrate back silicon nitride (SiN) the layer etching apparatus of silicon nitride (SiN) layer that forms on the back side of silicon single crystal flake substrate and cost an arm and a leg, cause total manufacturing cost height of semiconductor integrated circuit.
Fig. 2 is the processing step schematic diagram according to the new caustic solution of silicon single crystal flake substrate back silicon nitride of the present invention (SiN) layer.
Referring to Fig. 2,, comprise according to silicon single crystal flake substrate back silicon nitride of the present invention (SiN) layer caustic solution; (1) the silicon single crystal flake substrate is set; (2) deposit gate oxide on the silicon single crystal flake substrate; (3) deposit polysilicon layer (polysilicon) on the oxide gate material; (4) the silicon single crystal flake substrate that is deposited with grid material on it is placed in low pressure chemical vapor deposition (LPCVD) stove, all forms silicon nitride (SiN) protective layer on the top surface of silicon single crystal flake substrate and the back side; (5) all form the silicon single crystal flake substrate of silicon nitride (SiN) protective layer on its top surface and the back side, with chemical vapor deposition (CVD) method, on the silicon nitride that forms on the silicon single crystal flake top surface (SiN) layer, form silicon dioxide (SiO2) protection cover layer, and silicon single crystal flake substrate back silicon nitride (SiN) layer is exposed in the environment; (6) to immerse temperature range be 150 ℃ to 165 ℃ phosphoric acid (H to the single-chip substrate member that will have a structure that above-mentioned processing step forms
3PO
4) carry out wet corrosion in the etching tank, because phosphoric acid (H
3PO
4) corroding silicon nitride (SiN) layer and do not corrode silicon dioxide layer (SiO
2), so, can use phosphoric acid (H commonly used in the semiconductor integrated circuit manufacturing process
3PO
4) wet corrosion technology simply and is easily removed silicon single crystal flake substrate back silicon nitride (SiN) layer, and the silicon nitride of silicon single crystal flake top surface (SiN) layer is at silicon dioxide layer (SiO
2) protection under be retained, (7) carry out hydrofluoric acid (HF) corrosion subsequently, remove the silicon dioxide layer (SiO on silicon nitride (SiN) layer of silicon single crystal flake top surface
2), because hydrofluoric acid (HF) corroding silicon nitride (SiN) layer not, so kept silicon nitride (SiN) layer as the silicon single crystal flake top surface of the etch stop layer in technology subsequently.
Grid material can form with different materials, for example, with gate oxide/polysilicon/tungsten silicide (oxide/polysilicon/WSix), oxide/polysilicon (gate oxide/polysilicon), and oxide/polysilicon/tungsten/tungsten nitride formations such as (gate oxide/polysilicon/W/WN).
Silicon dioxide layer (the SiO that forms on silicon nitride on the silicon single crystal flake top surface (SiN) layer
2) in hydrofluoric acid (HF) etching process subsequently, be removed.Because hydrofluoric acid (HF) corrode silicon dioxide layer (SiO
2), and corroding silicon nitride (SiN) layer not, so kept silicon nitride (SiN) layer of silicon single crystal flake top surface.
With temperature 150 ℃ to 165 ℃ phosphoric acid (H
3PO
4) technology of wet corrosion silicon nitride (SiN) layer is technology general in the semiconductor integrated circuit manufacture method.With hydrofluoric acid (HF) corrode silicon dioxide layer (SiO
2) also be technology general in the semiconductor integrated circuit manufacture method.
Because phosphoric acid (H
3PO
4) wet corrosion and hydrofluoric acid (HF) etching process all be the general technology of semiconductor integrated circuit, so, do not need special-purpose silicon single crystal flake substrate back silicon nitride (SiN) layer etching apparatus with the inventive method, do not need to increase in addition processing step, thereby simplified technology, reduced total manufacturing cost of semiconductor integrated circuit.
More than show and described basic principle of the present invention and principal character and advantage of the present invention.The technical staff of the industry should understand; the present invention is not subjected to the restriction of above-mentioned execution mode; that describes in the foregoing description and the specification just illustrates basic principle of the present invention; the present invention also has various changes and modifications without departing from the spirit and scope of the present invention, and these changes and improvements all fall in the claimed scope of the present invention.The scope of protection of present invention is defined by appending claims and equivalent thereof.
Claims (5)
1. the caustic solution of semiconductor integrated circuit silicon single crystal flake substrate back silicon nitride layer may further comprise the steps:
(1) the silicon single crystal flake substrate is set;
(2) deposited oxide grid material on the silicon single crystal flake substrate;
(3) deposit polysilicon layer (polysilicon) on the oxide gate material;
(4) on the silicon single crystal flake substrate behind the deposit polysilicon layer, forming silicon nitride (SiN) protective layer on the polysilicon layer on the silicon single crystal flake top surface and on the back side of silicon single crystal flake substrate;
(5) form silicon dioxide (SiO on silicon nitride (SiN) layer that forms on the silicon single crystal flake top surface
2) protective layer;
(6) the silicon single crystal flake substrate that will have a structure that forms in the above processing step immerses phosphoric acid (H
3PO
4) in the etching tank, with phosphoric acid (H
3PO
4) silicon nitride (SiN) layer on the wet corrosion silicon single crystal flake substrate back, remove silicon nitride (SiN) layer of silicon single crystal flake substrate back;
(7) carry out hydrofluoric acid (HF) corrosion, remove the silicon dioxide (SiO on silicon nitride (SiN) layer of silicon single crystal flake top surface
2) protective layer, keep silicon nitride (SiN) protective layer on the silicon single crystal flake top surface.
2. according to the method for claim 1, it is characterized in that the item surface of silicon single crystal flake substrate and silicon nitride (SiN) layer on the back side form in low pressure chemical vapor deposition (LPCVD) stove.
3. according to the method for claim 1, it is characterized in that the silicon dioxide (SiO on the silicon nitride of silicon single crystal flake top surface (SiN) layer
2) protective layer forms with chemical vapor deposition (CVD) method.
4. according to the method for claim 1, it is characterized in that phosphoric acid (H
3PO
4) the phosphoric acid (H of silicon nitride (SiN) layer usefulness on the wet corrosion silicon single crystal flake substrate back
3PO
4) temperature range of corrosive agent is 150 ℃ to 165 ℃.
5. according to the method for claim 4, it is characterized in that described grid material is gate oxide/polysilicon/tungsten silicide, oxide/polysilicon or oxide/polysilicon/tungsten/tungsten nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410066298 CN100539035C (en) | 2004-09-10 | 2004-09-10 | The new caustic solution of semiconductor integrated circuit silicon single crystal flake substrate back silicon nitride layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410066298 CN100539035C (en) | 2004-09-10 | 2004-09-10 | The new caustic solution of semiconductor integrated circuit silicon single crystal flake substrate back silicon nitride layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1747136A CN1747136A (en) | 2006-03-15 |
| CN100539035C true CN100539035C (en) | 2009-09-09 |
Family
ID=36166577
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200410066298 Active CN100539035C (en) | 2004-09-10 | 2004-09-10 | The new caustic solution of semiconductor integrated circuit silicon single crystal flake substrate back silicon nitride layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100539035C (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100501936C (en) * | 2007-03-23 | 2009-06-17 | 厦门大学 | Electrochemical processing method for micro-structure of P type silicon surface |
| CN102079503B (en) * | 2009-11-26 | 2012-08-29 | 中芯国际集成电路制造(上海)有限公司 | Etching method of silicon substrate forming MEMS (Micro Electro Mechanical System) device |
| CN102110654B (en) * | 2009-12-23 | 2013-07-24 | 中芯国际集成电路制造(上海)有限公司 | Method for forming film structure on back of wafer |
| CN102290349A (en) * | 2010-06-21 | 2011-12-21 | 无锡华润上华半导体有限公司 | Semiconductor structure and forming method thereof |
| CN102420131B (en) * | 2011-07-01 | 2015-06-17 | 上海华力微电子有限公司 | Silicon wafer back silicon nitride growth method integrated in FEOL (front end of line) |
| CN103972074A (en) * | 2013-01-30 | 2014-08-06 | 无锡华润上华科技有限公司 | Method of removing mask layer from back of wafer |
| CN106298483B (en) * | 2015-05-31 | 2019-08-27 | 中芯国际集成电路制造(上海)有限公司 | The production method of the production method and embedded flash memory of polysilicon gate |
| CN107731662A (en) * | 2017-11-22 | 2018-02-23 | 上海华力微电子有限公司 | A kind of method for improving device uniformity |
| CN110246761A (en) * | 2019-06-19 | 2019-09-17 | 上海华力集成电路制造有限公司 | A method of removal backside of wafer silicon nitride film |
| CN111354636B (en) * | 2020-03-10 | 2022-09-02 | 上海华力微电子有限公司 | Memory forming method |
| CN111681949B (en) * | 2020-06-22 | 2021-05-18 | 长江存储科技有限责任公司 | Method for processing back of wafer |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3479237A (en) * | 1966-04-08 | 1969-11-18 | Bell Telephone Labor Inc | Etch masks on semiconductor surfaces |
| CN1181617A (en) * | 1996-10-24 | 1998-05-13 | 佳能株式会社 | Production of electronic device |
| CN1303127A (en) * | 2000-01-05 | 2001-07-11 | 三菱电机株式会社 | Non volatile semi-conductor memory and its manufacturing method |
| US6274421B1 (en) * | 1998-01-09 | 2001-08-14 | Sharp Laboratories Of America, Inc. | Method of making metal gate sub-micron MOS transistor |
-
2004
- 2004-09-10 CN CN 200410066298 patent/CN100539035C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3479237A (en) * | 1966-04-08 | 1969-11-18 | Bell Telephone Labor Inc | Etch masks on semiconductor surfaces |
| CN1181617A (en) * | 1996-10-24 | 1998-05-13 | 佳能株式会社 | Production of electronic device |
| US6274421B1 (en) * | 1998-01-09 | 2001-08-14 | Sharp Laboratories Of America, Inc. | Method of making metal gate sub-micron MOS transistor |
| CN1303127A (en) * | 2000-01-05 | 2001-07-11 | 三菱电机株式会社 | Non volatile semi-conductor memory and its manufacturing method |
Non-Patent Citations (2)
| Title |
|---|
| 氮化硅刻蚀工艺的研究. 赵水林.电子工业专用设备，第113期. 2004 * |
| 硅化钨/多晶硅复合栅的反应离子刻蚀工艺研究. 李祥，华亚平.微电子学，第21卷第5期. 1991 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1747136A (en) | 2006-03-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100539035C (en) | The new caustic solution of semiconductor integrated circuit silicon single crystal flake substrate back silicon nitride layer | |
| US9385031B2 (en) | Method for providing a self-aligned pad protection in a semiconductor device | |
| CN101459108B (en) | Method for forming shallow groove isolation structure and etching method for forming shallow groove | |
| JPH09298199A (en) | Semiconductor device and its manufacture | |
| TW392213B (en) | Surface cleaning method with plasma sputter used in the post-wolfram etching process | |
| CN103972082B (en) | Method for preventing pattern loss and wafer manufacturing method capable of preventing pattern loss | |
| US6635565B2 (en) | Method of cleaning a dual damascene structure | |
| CN112908839B (en) | Method for reducing silicon carbide wafer bow | |
| US9704719B2 (en) | Systems and methods to mitigate nitride precipitates | |
| CN100576453C (en) | The manufacture method of grid and nmos pass transistor | |
| CN100576497C (en) | Form the method for integrated circuit (IC)-components self-aligned contacts | |
| CN105513954A (en) | Forming method of semiconductor device | |
| US6291329B1 (en) | Protective oxide buffer layer for ARC removal | |
| CN103426745B (en) | The formation method of semiconductor structure | |
| US8398779B2 (en) | Non destructive selective deposition removal of non-metallic deposits from aluminum containing substrates | |
| TW460965B (en) | Cleaning method and device for silicon substrate | |
| JP2003133412A (en) | Method of improving adhesion of dielectric layer to copper | |
| JP4337446B2 (en) | Etching agent and etching method | |
| CN113675083B (en) | Method for exposing active region of silicon-on-insulator device, application and failure analysis method | |
| CN110797298A (en) | Electronic device and preparation method thereof | |
| CN111825055B (en) | Gold etching method | |
| TW471098B (en) | Method in making a storage node of stack capacitor upon silicon substrate | |
| CN105448645A (en) | Bonding pad processing method | |
| JP2007080966A (en) | Etching compound for hafnium oxide | |
| CN102751197B (en) | Method for manufacturing NMOS (N-channel metal oxide semiconductor) device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20111123 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20111123 Address after: 201203 Shanghai Zhangjiang Road, Zhangjiang High Tech Park of Pudong New Area No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai Zhangjiang Road, Zhangjiang High Tech Park of Pudong New Area No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |