CN102751197B - Method for manufacturing NMOS (N-channel metal oxide semiconductor) device - Google Patents
Method for manufacturing NMOS (N-channel metal oxide semiconductor) device Download PDFInfo
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- CN102751197B CN102751197B CN201210209048.4A CN201210209048A CN102751197B CN 102751197 B CN102751197 B CN 102751197B CN 201210209048 A CN201210209048 A CN 201210209048A CN 102751197 B CN102751197 B CN 102751197B
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Abstract
The invention relates to a method for manufacturing an NMOS (N-channel metal oxide semiconductor) device, which comprises the following steps of: providing an NMOS-containing substrate; allowing a silicon nitride layer with high tensile stress to be deposited on the substrate; classifying NMOSs non-covered with silicon nitride layers before deposition in accordance with the lengths of NMOS channels, retaining the silicon nitride layer corresponding to the NMOS with a maximum channel length, removing the silicon nitride layers corresponding to the rest NMOSs by remote plasma etching, and re-depositing the silicon nitride layers; and repeatedly performing the step until the NMOSs non-covered with silicon nitride layers before deposition can not be classified in accordance with the lengths of NMOS channels, continuing to perform the follow-up universal semiconductor process flow so as to form an NMOS transistor. According to the method for manufacturing the NMOS device, in accordance with the length of the channel of the NMOS device, by a depositing-remote plasma etching-re-deposition method, the thickness of the silicon nitride layer is proportional to the channel length, and the consistency of performance adjustment of the NMOS device is realized.
Description
Technical field
The present invention relates to semiconductor fabrication process, and in particular to nmos device manufacture method.
Background technology
Along with the development of semiconductor fabrication process technology, the characteristic line breadth of integrated circuit (IC) chip is more and more less, and in order to improve the performance of semiconductor device, stress engineering technology is widely used in semiconductor technology, in order to improve the electromobility of charge carrier.Wherein, more common, in the manufacturing process of nmos device, such as adopt via etch stop-layer (Contact Etch Stop Layer, CESL) stress engineering technology.
Via etch stop-layer stress engineering is in via etch stop-layer film deposition process, by adjustment sedimentary condition, produces heavily stressed, this stress is transmitted in device channel, thus has an impact to the mobility of charge carrier in film inside.Such as, for nmos device, by via etch stop-layer stress engineering, form via etch stop-layer film, produce compression in film inside, and this stress is conducted in the raceway groove of NMOS, tensile stress is formed to raceway groove.Tensile stress due to channel direction contributes to the electron mobility improving nmos device, thus can contribute to the performance improving nmos device.In practice, had experiment to prove, by deposition high tensile stress silicon nitride film, the performance that can improve NMOS reaches more than 10%.
But inventor is by finding in practice, and adopt the method for conventional through holes etching stop layer stress engineering to promote the performance of NMOS, for the NMOS of different channel lengths, it promotes effect is inconsistent.With reference to figure 1, along with the increase of channel length, the effect of improving performance diminishes.
At present, in production reality, in order to address this problem, usually the impact of channel length is just considered when layout design, thus adopt the transistor design of special construction, and designed domain is constantly tested and correction, this method considerably increases development & production cycle and the cost of product undoubtedly.
Summary of the invention
The invention provides a kind of nmos device manufacture method, according to the length of channel length successively to the silicon nitride layer corresponding to the NMOS with different channel lengths deposit-remote plasma etching remove-deposits again, silicon nitride layer thickness is directly proportional to channel length, thus realizes the consistency to nmos device adjusting performance.
In order to realize above-mentioned technical purpose, the present invention proposes a kind of nmos device manufacture method, comprising: provide the substrate containing NMOS; Deposition has the silicon nitride layer of high tensile stress on the substrate; The described NMOS covered without silicon nitride layer before deposition is classified according to the length order of NMOS channel length, retain the silicon nitride layer corresponding to NMOS in above-mentioned NMOS with the longest channel length, remote plasma etches to remove the silicon nitride layer in above-mentioned NMOS corresponding to all the other, deposited silicon nitride layer again; Repeat above-mentioned steps, until the described NMOS covered without silicon nitride layer before deposition cannot classify according to the length order of NMOS channel length, continue follow-up general semiconductor process flow, to form nmos pass transistor.
Optionally, described by deposition before without silicon nitride layer covering NMOS classify according to the length order of NMOS channel length, retain the silicon nitride layer corresponding to NMOS in above-mentioned NMOS with the longest channel length, remote plasma etching is to remove the silicon nitride layer in above-mentioned NMOS corresponding to all the other, deposited silicon nitride layer comprises again: be divided three classes according to the length order of NMOS channel length by described NMOS, the shortest and the secondary short NMOS for channel length, remote plasma etching removes the silicon nitride layer of its correspondence; Deposit the second silicon nitride layer; Remote plasma etching removes the second silicon nitride layer corresponding to the NMOS the shortest with channel length; Deposit the 3rd silicon nitride layer.
Optionally, using plasma strengthens silicon nitride layer described in chemical vapor deposition.
Optionally, the thickness of each deposited described silicon nitride layer is 100 dust to 300 dusts.
Optionally, described silicon nitride layer has high tensile stress, and described high tensile stress is the lucky handkerchief of 0.7 lucky handkerchief to 2.0.
It is optionally, described that to carry out to silicon nitride layer the etching gas that remote plasma etching adopts be remote plasma containing hydrogen and/or gas of nitrogen trifluoride.
Optionally, the follow-up general semiconductor process flow of described continuation comprises dielectric substance layer before plated metal.
Compared to prior art, nmos device manufacture method of the present invention has taken into full account the Different Effects of high tensile stress to channel carrier of the silicon nitride layer of different-thickness, according to the length of nmos device channel length, the method remove-again deposited is etched by deposition-remote plasma, the thickness of described silicon nitride layer is directly proportional to channel length, thus the consistency to nmos device adjusting performance can be realized.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the channel length performance corresponding to it of nmos device;
Fig. 2 is the schematic flow sheet of a kind of execution mode of nmos device manufacture method of the present invention;
Fig. 3 is generalized section when having different length NMOS raceway groove in the substrate of nmos device manufacture method of the present invention;
Fig. 4 is the schematic flow sheet of an embodiment of nmos device manufacture method of the present invention;
The generalized section of nmos device of Fig. 5-Fig. 9 for being formed according to a kind of embodiment of nmos device manufacture method of the present invention.
Embodiment
Nmos device manufacture method provided by the present invention is by after common high tensile stress silicon nitride layer has deposited, length according to nmos device channel length takes deposition-remote plasma to etch the process remove-again deposited to described silicon nitride layer, make the raceway groove of nmos device longer, the described silicon nitride layer of its correspondence is thicker, thus can realize the consistency to nmos device adjusting performance.
Below in conjunction with specific embodiments and the drawings, nmos pass transistor manufacture method of the present invention is described in detail.
With reference to figure 2, nmos device manufacture method of the present invention comprises:
Step S100, provides the substrate containing NMOS;
Step S200, deposition has the silicon nitride layer of high tensile stress on the substrate;
Step S300, the described NMOS covered without silicon nitride layer before deposition is classified according to the length order of NMOS channel length, retain the silicon nitride layer corresponding to NMOS in above-mentioned NMOS with the longest channel length, remote plasma etches to remove the silicon nitride layer in above-mentioned NMOS corresponding to all the other, deposited silicon nitride layer again;
Repeated execution of steps S300, until the described NMOS covered without silicon nitride layer before deposition cannot classify according to the length order of NMOS channel length, performs step S400, continues follow-up general semiconductor process flow, to form nmos pass transistor.
With reference to figure 3, in one embodiment, the NMOS in substrate 100 has the different raceway groove of three kinds of length respectively, is wherein followed successively by NMOS101, NMOS102 and NMOS103 according to the order that channel length increases progressively.Accordingly, with reference to figure 4, nmos device manufacture method of the present invention comprises:
Step S1, provides the substrate containing NMOS;
Step S2, deposits the first silicon nitride layer on the substrate;
Step S3, the shortest and secondary short NMOS for channel length, remote plasma etching removes the first silicon nitride layer of its correspondence;
Step S4, deposits the second silicon nitride layer;
Step S5, remote plasma etching removes the second silicon nitride layer corresponding to the NMOS the shortest with channel length;
Step S6, deposition the 3rd silicon nitride layer;
Step S7, continues follow-up general semiconductor process flow, to form nmos pass transistor.
Specifically, with reference to figure 5, the substrate 100 with NMOS deposits the first silicon nitride layer 110.
With reference to figure 6, first the first silicon nitride layer 110 that time short NMOS102 of the shortest NMOS101 of channel length and channel length deposits is exposed and remote plasma etching, remove the first corresponding silicon nitride layer 110.Then, with reference to figure 7, again deposit, form the second silicon nitride layer 120.
Then, with reference to figure 8, then the second silicon nitride layer 120 that the shortest NMOS101 of channel length deposits is exposed and remote plasma etching, remove the second corresponding silicon nitride layer 120.Then, with reference to figure 9, again deposit, form the 3rd silicon nitride layer 130.
In above-mentioned first silicon nitride layer 110, second silicon nitride layer 120 and the 3rd silicon nitride layer 130, the thickness of any one can be 100 dust to 300 dusts, and can strengthen chemical vapour deposition technique and deposit by using plasma.Described first silicon nitride layer 110, second silicon nitride layer 120 and the 3rd silicon nitride layer 130 all have high tensile stress, and the range of stress is that 0.7 lucky handkerchief (GPa) is to 2.0 lucky handkerchiefs.
Be not difficult to find, after formation the 3rd silicon nitride layer 130, the NMOS103 that channel length is the longest deposited the first silicon nitride layer 110, second silicon nitride layer 120 and the 3rd silicon nitride layer 130, the NMOS102 of channel length vice-minister deposited the second silicon nitride layer 120 and the 3rd silicon nitride layer 130, and the shortest NMOS101 of channel length deposited the 3rd silicon nitride layer 130.That is, the mode remove-again deposited is etched by above-mentioned deposition-remote plasma, the thickness of the silicon nitride layer that NMOS deposits is directly proportional to the length of its channel length, channel length is long, then deposited silicon nitride layer thickness is thick, otherwise channel length is short, then deposited silicon nitride layer thickness is thin.
Because deposited silicon nitride layer has high tensile stress, and this stress can conduct in raceway groove, to improve the migration rate of charge carrier, and silicon nitride layer is thicker, the charge carrier quantity that its stress can affect is more, thus can adjust the performance of the NMOS with longer raceway groove.Therefore, the silicon nitride layer be directly proportional to channel length can realize the consistency to nmos device adjusting performance.
Wherein, the etching gas adopted during above-mentioned remote plasma etching is the remote plasma containing the gas such as hydrogen (H2), Nitrogen trifluoride (NF3), can adopt the SiCoNi processing procedure of such as company of Applied Materials.
In a kind of embodiment, step S7 also can comprise dielectric substance layer before plated metal.
In other execution mode of nmos device manufacture method of the present invention, the NMOS in substrate also can have the raceway groove more than three kinds of different lengths respectively, and the kind of its channel length does not cause restriction to the invention thinking of nmos device manufacture method of the present invention.
Compared to prior art, nmos device manufacture method of the present invention has taken into full account the Different Effects that the high tensile stress that the thickness of silicon nitride layer makes it have causes channel carrier, according to the length of nmos device channel length, NMOS is classified, and gradation is carried out the removal of remote plasma etching and is again deposited, the thickness of described silicon nitride layer is directly proportional to channel length, thus the consistency to nmos device adjusting performance can be realized.Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (6)
1. a nmos device manufacture method, is characterized in that, comprising:
Step one: the substrate containing NMOS is provided;
Step 2: deposition has the silicon nitride layer of high tensile stress on the substrate;
Step 3: the described NMOS covered without silicon nitride layer before deposition is classified according to the length order of NMOS channel length, retain the silicon nitride layer corresponding to NMOS in above-mentioned NMOS with the longest channel length, remote plasma etches to remove the silicon nitride layer in above-mentioned NMOS corresponding to all the other, deposited silicon nitride layer again;
Repeat above-mentioned steps three, until the described NMOS covered without silicon nitride layer before deposition cannot classify according to the length order of NMOS channel length, perform step 4: continue follow-up general semiconductor process flow, to form nmos pass transistor.
2. nmos device manufacture method as claimed in claim 1, it is characterized in that, the NMOS in described substrate has the different raceway groove of three kinds of length respectively, then above-mentioned steps three comprises:
Described NMOS is divided three classes according to the length order of NMOS channel length, the shortest and secondary short NMOS for channel length, remote plasma etching removes the silicon nitride layer of its correspondence;
Deposit the second silicon nitride layer;
Remote plasma etching removes the second silicon nitride layer corresponding to the NMOS the shortest with channel length;
Deposit the 3rd silicon nitride layer.
3. nmos device manufacture method as claimed in claim 1, is characterized in that, using plasma strengthens silicon nitride layer described in chemical vapor deposition.
4. nmos device manufacture method as claimed in claim 1, it is characterized in that, described silicon nitride layer has high tensile stress, and described high tensile stress is the lucky handkerchief of 0.7 lucky handkerchief to 2.0.
5. nmos device manufacture method as claimed in claim 1, is characterized in that, described to carry out to silicon nitride layer etching gas that remote plasma etching adopts be remote plasma containing hydrogen and/or gas of nitrogen trifluoride.
6. nmos device manufacture method as claimed in claim 1, is characterized in that, the follow-up general semiconductor process flow of described continuation comprises dielectric substance layer before plated metal.
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| CN102376645A (en) * | 2010-08-19 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Forming method of CMOS (Complementary Metal-Oxide-Semiconductor Transistor) device stress film |
| CN102412125A (en) * | 2011-04-29 | 2012-04-11 | 上海华力微电子有限公司 | Method for manufacturing silicon nitride film with high tensile stress |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102376645A (en) * | 2010-08-19 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Forming method of CMOS (Complementary Metal-Oxide-Semiconductor Transistor) device stress film |
| CN102412125A (en) * | 2011-04-29 | 2012-04-11 | 上海华力微电子有限公司 | Method for manufacturing silicon nitride film with high tensile stress |
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