CN111354636B - Memory forming method - Google Patents

Memory forming method Download PDF

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CN111354636B
CN111354636B CN202010159638.5A CN202010159638A CN111354636B CN 111354636 B CN111354636 B CN 111354636B CN 202010159638 A CN202010159638 A CN 202010159638A CN 111354636 B CN111354636 B CN 111354636B
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oxide layer
silicon oxide
layer
silicon nitride
top silicon
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CN111354636A (en
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陆霄宇
齐瑞生
陈昊瑜
邵华
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

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  • Chemical & Material Sciences (AREA)
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  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention provides a method for forming a memory, which comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate, a tunneling oxide layer, a first silicon nitride layer and a first top silicon oxide layer which are positioned on the front surface of the substrate, and a bottom silicon oxide layer, a second silicon nitride layer and a second top silicon oxide layer which are positioned on the back surface of the substrate; removing the first top silicon oxide layer and the second top silicon oxide layer; forming a third top silicon oxide layer on the first silicon nitride layer, and simultaneously forming an uneven fourth top silicon oxide layer below the second silicon nitride layer; forming a protective layer on the third top silicon oxide layer of the SONOS region; etching the fourth top silicon oxide layer; removing the third top silicon oxide layer of the non-SONOS region; and removing the protective layer, and removing the first silicon nitride layer and the second silicon nitride layer in the non-SONOS region. Finally, the problem that uneven ONO is generated on the back surface of the substrate in the etching process is solved, and the problems of wafer warping and the like caused by uneven quality are avoided.

Description

Memory forming method
Technical Field
The invention relates to the technical field of semiconductors, in particular to a forming method of a memory.
Background
With the continuous improvement of the integration level requirement of the market on the FLASH memory device, the contradiction between the reliability of data storage of the traditional FLASH device and the aspects of the working speed, the power consumption, the size and the like of the device is increasingly highlighted. The SONOS memory has the characteristics of small cell size, low operating voltage, compatibility with CMOS processes, and the like, and the continuous improvement of the SONOS technology will push the development of semiconductor memories toward miniaturization, high performance, large capacity, low cost, and the like.
The SONOS memory uses a Silicon substrate-tunneling Oxide layer-Silicon Nitride-blocking Oxide layer-polysilicon (Silicon-Oxide-Nitride-Oxide-Silicon) gate stack structure, and is a charge trap type memory. The prior art forms a tunnel oxide-silicon nitride-barrier oxide (ONO) structure by In-situ and secondary growth methods. After the ONO is formed, the non-SONOS storage region needs to be removed by adopting the processes of photoetching, dry etching/wet etching and the like, and the specific process flow is as follows:
as shown in fig. 1, a semiconductor base is first provided, the semiconductor comprising a substrate 110 (which may be a wafer), and an ONO stack on the front and back sides of the substrate 110. The front side ONO stack includes: a tunnel oxide layer 121, a first silicon nitride layer 122, and a first top silicon oxide layer 123; the backside ONO stack includes: a bottom silicon oxide layer 131, a second silicon nitride layer 132, and a second top silicon oxide layer 133.
As shown in fig. 2, the wet etching removes the first top silicon oxide layer 123 to expose the surface of the first silicon nitride layer 122 and the wet etching removes the second top silicon oxide layer 133 to expose the surface of the second silicon nitride layer 132.
As shown in fig. 3, a third top silicon oxide layer 124 is formed on the surface of the first silicon nitride layer 122, and a fourth top silicon oxide layer 134 is formed in a portion of the region under the second silicon nitride layer 132, and the thickness of the fourth top silicon oxide layer 134 is not uniform.
As shown in fig. 4, a photoresist 142 and a bottom anti-reflective coating 141 are coated on the third top silicon oxide layer 124 and developed to expose the non-SONOS memory region. The third top silicon oxide layer 124 of the developed region is removed by dry etching.
As shown in fig. 5, the photoresist 142 and the bottom anti-reflective coating 141 are removed, and the SONOS region ON the front surface of the substrate 110 is an ONO stack from bottom to top, and the non-SONOS region is an ON stack. The substrate 110 has a complete ON stack and an incomplete, non-uniform silicon oxide layer ON the back side, i.e. an ONO stack is present in a partial region ON the back side of the substrate 110.
As shown in fig. 6, the first silicon nitride layer 122 in the non-SONOS region on the front surface of the substrate 110 is removed by wet etching, and at this time, the SONOS region on the front surface of the substrate 110 is an ONO stack from bottom to top, and only the bottom tunneling oxide layer 121 remains in the non-SONOS region.
In the prior art, an uneven ONO lamination layer is formed on the back surface of a substrate 110 in the ONO etching process, so that the following problems are caused:
1. the second silicon nitride layer 132 and the fourth top silicon oxide layer 134 have a certain color difference, and the back of the wafer (substrate) has an uneven color difference phenomenon, which affects the wafer shipment quality;
2. the ONO lamination with uneven wafer back is an uncontrollable category in the prior art, which can cause uneven quality in the wafer surface and easily generate problems of warping, bending and the like, thereby causing inaccurate photoetching focusing and influencing subsequent process steps;
3. the back surface of the wafer is covered with a poly, silicon nitride and other laminated layers subsequently, if a back-end wafer back cleaning method is adopted to solve the problem of chromatic aberration, a plurality of process steps are required to be added, the cost is increased, and side effects are possibly brought.
Disclosure of Invention
The invention aims to provide a forming method of a memory, which can effectively solve the problem that a wafer back generates uneven ONO laminate in the etching process of the ONO laminate in a non-SONOS region, avoid the step of cleaning the wafer back at the later stage, avoid the problem of wafer warping caused by uneven quality, and improve the stability and the reliability of the subsequent process.
In order to achieve the above object, the present invention provides a method of forming a memory, the memory including: SONOS regions and non-SONOS regions, including:
providing a semiconductor substrate, the semiconductor substrate comprising: the silicon nitride wafer comprises a substrate, a tunneling oxide layer, a first silicon nitride layer, a first top silicon oxide layer, a bottom silicon oxide layer, a second silicon nitride layer and a second top silicon oxide layer, wherein the tunneling oxide layer is positioned on the front surface of the substrate;
removing the first top silicon oxide layer to expose the first silicon nitride layer, and removing the second top silicon oxide layer to expose the second silicon nitride layer;
forming a third top silicon oxide layer on the first silicon nitride layer, and simultaneously forming an uneven fourth top silicon oxide layer below the second silicon nitride layer;
forming a protective layer on the third top silicon oxide layer of the SONOS region;
etching the fourth top silicon oxide layer;
removing the third top silicon oxide layer of the non-SONOS region;
and removing the protective layer, and removing the first silicon nitride layer and the second silicon nitride layer in the non-SONOS region.
Optionally, in the method for forming a memory, the protective layer includes an anti-reflective coating on the third top silicon oxide layer and a photoresist on the anti-reflective coating.
Optionally, in the method for forming the memory, the tunneling oxide layer, the bottom silicon oxide layer, the first top silicon oxide layer, the second top silicon oxide layer, the first silicon nitride layer, and the second silicon nitride layer are formed by an ONO furnace tube.
Optionally, in the method for forming a memory, the third top silicon oxide layer and the fourth top silicon oxide layer are both formed by a CVD process.
Optionally, in the method for forming the memory, the fourth top silicon oxide layer is etched by using a silicon oxide etching solution.
Optionally, in the method for forming the memory, the etching amount of the fourth top silicon oxide layer is 5 to 50 angstroms.
Optionally, in the method for forming the memory, a dry etching process is used to remove the third top silicon oxide layer in the non-SONOS region.
Optionally, in the method for forming the memory, the etching amount of the third top silicon oxide layer is 5 to 80 angstroms.
Optionally, in the method for forming a memory, the method for removing the protection layer includes: the photoresist and the anti-reflective coating are sequentially removed.
Optionally, in the method for forming the memory, a wet etching process is used to remove the first silicon nitride layer and the second silicon nitride layer in the non-SONOS region.
According to the forming method of the memory, the problem that uneven ONO lamination is generated on the back surface of the substrate in the etching process of the ONO lamination in the non-SONOS region is solved, the step of cleaning the back section is omitted, the cost is saved, the problems of wafer warping and the like caused by uneven quality are avoided, and the stability and the reliability of the subsequent process are improved. In addition, the method can also be well applied to the existing process flow, and has strong compatibility; the influence on the prior process flow and the device structure is small.
Drawings
FIGS. 1-6 are cross-sectional views of a prior art method of forming a memory device with the ONO stack removed;
FIG. 7 is a flow chart illustrating the removal of the ONO stack in a method for forming a memory according to an embodiment of the present invention;
FIGS. 8-15 are cross-sectional views of an ONO stack removal in a method of forming a memory device according to an embodiment of the invention;
in the figure: 110-substrate, 121-tunnel oxide layer, 122-first silicon nitride layer, 123-first top silicon oxide layer, 131-bottom silicon oxide layer, 132-second silicon nitride layer, 133-second top silicon oxide layer, 124-third top silicon oxide layer, 134-fourth top silicon oxide layer, 141-bottom anti-reflection coating, 142-photoresist, 210-substrate, 221-tunnel oxide layer, 222-first silicon nitride layer, 223-first top silicon oxide layer, 224-third top silicon oxide layer, 231-bottom silicon oxide layer, 232-second silicon nitride layer, 233-second top silicon oxide layer, 234-fourth top silicon oxide layer, 241-bottom anti-reflection coating, 242-photoresist.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Referring to fig. 7, the present invention provides a method for forming a memory, including: SONOS regions and non-SONOS regions, including:
s11: providing a semiconductor substrate, the semiconductor substrate comprising: the silicon nitride wafer comprises a substrate, a tunneling oxide layer, a first silicon nitride layer, a first top silicon oxide layer, a bottom silicon oxide layer, a second silicon nitride layer and a second top silicon oxide layer, wherein the tunneling oxide layer is positioned on the front surface of the substrate;
s12: removing the first top silicon oxide layer to expose the first silicon nitride layer, and removing the second top silicon oxide layer to expose the second silicon nitride layer;
s13: forming a third top silicon oxide layer on the first silicon nitride layer, and simultaneously forming an uneven fourth top silicon oxide layer below the second silicon nitride layer;
s14: forming a protective layer on the third top silicon oxide layer of the SONOS region;
s15: etching the fourth top silicon oxide layer;
s16: removing the third top silicon oxide layer of the non-SONOS region;
s17: and removing the protective layer, and removing the first silicon nitride layer and the second silicon nitride layer of the non-SONOS region.
Referring to fig. 8, a semiconductor substrate is provided, where the semiconductor substrate includes a substrate 210, which may be a wafer, a first ONO stack on a front surface of the substrate 210, the first ONO stack including a tunnel oxide layer 221 on the front surface of the substrate 210, a first silicon nitride layer 222 covering the tunnel oxide layer 221, and a first top silicon oxide layer 223 covering the first silicon nitride layer 222, and the second ONO stack including a bottom silicon oxide layer 231 on a back surface of the substrate 210, a second silicon nitride layer 232 covering the bottom silicon oxide layer 231, and a second top silicon oxide layer 233 covering the second silicon nitride layer 232. The tunnel oxide layer 221, the bottom silicon oxide layer 231, the first top silicon oxide layer 223, the second top silicon oxide layer 233, the first silicon nitride layer 222, and the second silicon nitride layer 232 are formed by an ONO furnace tube and other prior art techniques known to those skilled in the art.
Referring to fig. 9, the first top silicon oxide layer 223 is removed to expose the first silicon nitride layer 222, the second top silicon oxide layer 233 is removed to expose the second silicon nitride layer 232, and the etching method may be wet etching.
Referring to fig. 10, a third top silicon Oxide layer 224 is formed on the first silicon Nitride layer 222, because an ONO process is performed, the ONO furnace is integrated, Oxide-Nitride-Oxide is formed simultaneously, but the top silicon Oxide layer of the conventional furnace has poor performance and cannot meet the requirement, in the embodiment of the present invention, a wet method is used to remove the first silicon Nitride layer 222 and grow the third top silicon Oxide layer 224, i.e., the second silicon Oxide layer is grown to form the ONO layer, however, due to the defects of the process, an uneven fourth top silicon Oxide layer 234 is also formed below the second silicon Nitride layer 232, and the fourth top silicon Oxide layer 234 is accidentally generated by the process, which is not only not required, but also affects the subsequent processes, may cause uneven color difference phenomenon on the back of the wafer (substrate), affects the product quality of the wafer, and may cause uneven quality in the wafer plane, the problems of warping, bending and the like are easy to occur, so that the photoetching focusing is inaccurate, and the subsequent process steps are influenced. The third top silicon oxide layer and the fourth top silicon oxide layer are both formed using a CVD process and other prior art techniques known to those skilled in the art.
Referring to fig. 11, a protection layer is formed on the third top silicon oxide layer 224 in the SONOS region, and the protection layer includes an anti-reflective coating 241 on the third top silicon oxide layer 224 and a photoresist 242 on the anti-reflective coating 241.
Referring to fig. 12, the fourth top silicon oxide layer 234 is etched by a silicon oxide etching solution, the silicon oxide etching solution is an HF mixed solution and has a high etching selectivity to silicon nitride, the preferred etching solution in this embodiment is an etching reagent with HF as a main component, and the etching amount of the fourth top silicon oxide layer 234 is 5 angstroms to 50 angstroms, and in this embodiment, is preferably 20 angstroms. In this step, the fourth top silicon oxide layer 234 on the back surface of the semiconductor substrate is completely removed, the third top silicon oxide layer 224 in the undeveloped region on the front surface is protected by the protective layer and is not etched, and the third top silicon oxide layer 224 in the developed region has a small loss and is not completely etched.
Referring to fig. 13, the third top silicon oxide layer 224 of the non-SONOS region is removed; and removing the third top silicon oxide layer 224 in the non-SONOS region by using a dry etching method, wherein the etching amount is 5-80 angstroms. At this time, the front side SONOS memory region of the substrate 210 is an ONO stack from bottom to top, the non-SONOS memory region is an ON stack, and the back side of the substrate 210 is an ON stack from top to bottom.
Referring to fig. 14, the protective layer is removed, and the method for removing the protective layer includes: the photoresist 242 and the anti-reflection coating 241 are sequentially removed, and the removing method may be implemented by using the prior art, which is not described herein.
Referring to fig. 14 and 15, the first silicon nitride layer 222 and the second silicon nitride layer 232 in the non-SONOS region are removed, and the first silicon nitride layer 222 and the second silicon nitride layer 232 in the non-SONOS region are removed by a wet etching process, where the etching solution is a composite etching solution mainly containing phosphoric acid or other existing etching solutions that etch silicon nitride materials and have a high selectivity (slow etching) for etching silicon oxide. And removing the first silicon nitride layer 222 on the front surface and the second silicon nitride layer 232 on the back surface of the substrate 210 by wet etching, wherein the ONO lamination is formed in the front SONOS region from bottom to top, the tunneling oxide layer 221 is only reserved in the non-SONOS region, and the etching of the ONO lamination is finished. The substrate 210 is backed by a bottom silicon oxide layer 231 and the ONO stack is removed.
In the forming process of the memory provided by the embodiment of the invention, the ONO lamination layer in the non-SONOS region can be etched, and the uneven ONO lamination layer can be formed on the back surface of the substrate in the conventional ONO etching process, so that the wafer quality and the subsequent process steps are influenced. The method solves the problem of uneven ONO lamination on the back surface of the substrate in the ONO etching process, omits the step of cleaning the back section, saves the cost, simultaneously avoids the problems of wafer warping and the like caused by uneven quality, and improves the stability and the reliability of the subsequent process. In addition, the method can be well applied to the existing process flow, and has strong compatibility; has little influence on the prior process flow, conditions and device structure.
In conclusion, in the forming method of the memory provided by the embodiment of the invention, the problem that the back surface of the substrate generates the uneven ONO laminate in the etching process of the ONO laminate of the non-SONOS region is solved, the step of cleaning the back section is omitted, the cost is saved, meanwhile, the problems of wafer warping and the like caused by uneven quality are avoided, and the stability and the reliability of the subsequent process are improved. In addition, the method can also be well applied to the existing process flow, and has strong compatibility; the method has little influence on the prior process flow and the device structure.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A method of forming a memory, the memory comprising: SONOS region and non-SONOS region, characterized by, include:
providing a semiconductor substrate, the semiconductor substrate comprising: the silicon nitride wafer comprises a substrate, a tunneling oxide layer, a first silicon nitride layer, a first top silicon oxide layer, a bottom silicon oxide layer, a second silicon nitride layer and a second top silicon oxide layer, wherein the tunneling oxide layer is positioned on the front surface of the substrate;
removing the first top silicon oxide layer to expose the first silicon nitride layer, and removing the second top silicon oxide layer to expose the second silicon nitride layer;
forming a third top silicon oxide layer on the first silicon nitride layer, and simultaneously forming an uneven fourth top silicon oxide layer below the second silicon nitride layer;
forming a protective layer on the third top silicon oxide layer of the SONOS region;
etching the fourth top silicon oxide layer;
removing the third top silicon oxide layer of the non-SONOS region;
and removing the protective layer, and removing the first silicon nitride layer and the whole second silicon nitride layer in the non-SONOS region.
2. The method of claim 1, wherein the protective layer comprises an anti-reflective coating on the third top silicon oxide layer and a photoresist on the anti-reflective coating.
3. The method of claim 1, wherein the tunneling oxide layer, the bottom silicon oxide layer, the first top silicon oxide layer, the second top silicon oxide layer, the first silicon nitride layer, and the second silicon nitride layer are formed by an ONO furnace tube.
4. The method of claim 1, wherein the third top silicon oxide layer and the fourth top silicon oxide layer are formed using a CVD process.
5. The method of claim 1, wherein etching the fourth top silicon oxide layer is performed with a silicon oxide etching solution.
6. The method of claim 5, wherein the fourth top silicon oxide layer is etched by an amount of 5 to 50 angstroms.
7. The method of claim 1, wherein removing the third top silicon oxide layer in the non-SONOS region is performed using a dry etching process.
8. The method of claim 7, wherein the third top silicon oxide layer is etched in an amount of 5 to 80 angstroms.
9. The method of claim 2, wherein the removing the protective layer comprises: the photoresist and the anti-reflective coating are sequentially removed.
10. The method of claim 1, wherein removing the first silicon nitride layer and the entire second silicon nitride layer in the non-SONOS region is performed using a wet etch process.
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Citations (3)

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Publication number Priority date Publication date Assignee Title
JP2005260032A (en) * 2004-03-12 2005-09-22 Matsushita Electric Ind Co Ltd Semiconductor device manufacturing method
CN1747136A (en) * 2004-09-10 2006-03-15 中芯国际集成电路制造(上海)有限公司 Corrosion of silicon nitride layer with single-chip substrate as back for IC integrated circuit
CN105826181A (en) * 2015-01-07 2016-08-03 中芯国际集成电路制造(上海)有限公司 Method for preventing peeling defect of ONO structure

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7572735B2 (en) * 2006-09-27 2009-08-11 Texas Instruments Incorporated Blanket resist to protect active side of semiconductor
JP2008300643A (en) * 2007-05-31 2008-12-11 Fujitsu Microelectronics Ltd Manufacturing method of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005260032A (en) * 2004-03-12 2005-09-22 Matsushita Electric Ind Co Ltd Semiconductor device manufacturing method
CN1747136A (en) * 2004-09-10 2006-03-15 中芯国际集成电路制造(上海)有限公司 Corrosion of silicon nitride layer with single-chip substrate as back for IC integrated circuit
CN105826181A (en) * 2015-01-07 2016-08-03 中芯国际集成电路制造(上海)有限公司 Method for preventing peeling defect of ONO structure

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