CN100536303C - Voltage boost circuit and voltage level shifter - Google Patents
Voltage boost circuit and voltage level shifter Download PDFInfo
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- CN100536303C CN100536303C CNB2006101617907A CN200610161790A CN100536303C CN 100536303 C CN100536303 C CN 100536303C CN B2006101617907 A CNB2006101617907 A CN B2006101617907A CN 200610161790 A CN200610161790 A CN 200610161790A CN 100536303 C CN100536303 C CN 100536303C
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- booster circuit
- drain electrode
- grid
- input signal
- voltage level
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Abstract
The invention relates to booster circuits and a voltage level shifter, in particular to the voltage level shifter which comprises a first booster circuit, an inverter, a second booster circuit and a voltage level shift circuit. The first booster circuit receives an input signal and determines a voltage amplification rate of the input signal according to a control signal. The inverter receives the input signal and generates an inverse input signal. The second booster circuit is coupled with an output end of the inverter for receiving the inverse input signal and determining the voltage amplification rate of the inverse input signal. The voltage level shift circuit comprises a first input end and a second input end which are respectively coupled with output ends of the first booster circuit and the second booster circuit, thereby shifting the voltage level of the input signal to a first voltage level. In the booster circuits and the voltage level shifter provided by the invention, the booster circuits occupy a small area of circuit placement, so the generation of DC can be avoided, and the problem of breakdown voltage is averted.
Description
Technical field
The present invention is a kind of voltage level shifter, particularly a kind of voltage level shifter that utilizes booster circuit to carry out the two-part booster tension.
Background technology
Known circuit in order to booster tension utilizes voltage level shifter to finish more.Voltage level shifter has two inputs, receives the inversion signal of an input signal and this input signal respectively, and in general circuit, input is generally transistorized grid.And if when generally wanting to increase the output current of voltage level shifter, essentially increase transistorized W/L ratio, yet such design but can increase the layout area of circuit.With nmos pass transistor, if nmos pass transistor is wanted complete conducting, then the voltage of input signal must surpass a predetermined value, if the voltage of input is big inadequately, then the conducting degree of nmos pass transistor is not enough, and nmos pass transistor only can be exported output current in a small amount in such cases.Relative when input voltage big inadequately, can the drive voltage level shift unit, also just can't reach the function of booster tension.
Summary of the invention
Purpose of the present invention is for providing a kind of voltage level shifter that utilizes booster circuit to carry out the two-part booster tension.
The invention provides a kind of booster circuit, comprise a first transistor, a transistor seconds, one the 3rd transistor, one the 4th transistor, one the 5th transistor and a capacitance group.This first transistor has one first source electrode, a first grid and one first drain electrode, and wherein this first source electrode couples a voltage source.This transistor seconds has one second source electrode, a second grid and one second drain electrode, and wherein this second drain electrode couples this first drain electrode, this second source ground, and this second grid and this first grid receive an input signal.This capacitance group has one first end and one second end, is controlled by a control signal changing its capacitance, and in order to change capacitance group discharge time, wherein first end couples this second drain electrode and this first drain electrode.The 3rd transistor has one the 3rd source electrode, one the 3rd grid and one the 3rd drain electrode, and wherein the 3rd source electrode couples this voltage source, and the 3rd grid couples an output signal end.One the 4th transistor has one the 4th source electrode, one the 4th grid and one the 4th drain electrode, and wherein the 4th grid receives this input signal, and the 4th source electrode and the 3rd drain electrode couple this second end of this capacitance group, and the 4th drain electrode couples this output signal end.The 5th transistor has one the 5th source electrode, one the 5th grid and one the 5th drain electrode, and wherein the 5th grid receives this input signal, and the 5th drain electrode couples this output signal end, the 5th source ground.
Booster circuit of the present invention, wherein this capacitance group comprises that one first electric capacity and one second electric capacity are connected in parallel, wherein this first electric capacity is coupled to a switching device, and determines according to this control signal whether this first electric capacity is in parallel with this second electric capacity.
Booster circuit of the present invention, wherein this first electric capacity and this second electric capacity all are made up of transistor.
Booster circuit of the present invention, wherein this switching device is a cmos transmission gate.
The invention provides a kind of voltage level shifter, comprise first booster circuit identical, an inverter, second booster circuit and a voltage level shifter identical with above-mentioned booster circuit with above-mentioned booster circuit.This first booster circuit receives an input signal, and determines the voltage amplification multiplying power of this input signal according to a control signal.This inverter receives this input signal, produces a rp input signal.This second booster circuit couples the output of this inverter, receives a rp input signal, and determines the voltage amplification multiplying power of this rp input signal according to this control signal.This voltage level shift circuit has a first input end and one second input, couples the output of this first booster circuit and this second booster circuit respectively, in order to voltage level shifting to one first voltage level with this input signal.
Voltage level shifter of the present invention, wherein this capacitance group comprises that one first electric capacity and one second electric capacity are connected in parallel, wherein this first electric capacity is coupled to a switching device, and determines according to this control signal whether this first electric capacity is in parallel with this second electric capacity.
Voltage level shifter of the present invention, wherein this first electric capacity and this second electric capacity all are made up of transistor.
Voltage level shifter of the present invention, wherein this switching device is a cmos transmission gate.
Booster circuit provided by the present invention and voltage level shifter, the shared circuit layout area of booster circuit is little, can avoid direct current to produce, and does not have break-down voltage problem.
Description of drawings
Fig. 1 is the circuit diagram according to an embodiment of booster circuit of the present invention.
Fig. 2 is the circuit diagram of an embodiment of the capacitance group among Fig. 1.
Fig. 3 is the circuit diagram according to an embodiment of voltage level shifter of the present invention.
Embodiment
Fig. 1 is the circuit diagram according to an embodiment of booster circuit of the present invention.Transistor T 1 has one first source electrode, a first grid and one first drain electrode, and wherein this first source electrode couples a voltage source V DD.Transistor T 2 has one second source electrode, a second grid and one second drain electrode, and wherein this second drain electrode couples this first drain electrode, this second source ground, and this second grid and this first grid receive an input signal Vin.Capacitance group 11 has one first end and one second end, is controlled by a control signal Cs to change its capacitance, and in order to change the capacitance discharges time, wherein first end couples this second drain electrode and first drain electrode.Transistor T 3 has one the 3rd source electrode, one the 3rd grid and one the 3rd drain electrode, and wherein the 3rd source electrode couples this voltage source V DD, and the 3rd grid is in order to export an output signal Vout.Transistor T 4, have one the 4th source electrode, one the 4th grid and one the 4th drain electrode, wherein the 4th grid receives this input signal Vin, and the 4th source electrode and the 3rd drain electrode couple the other end (second end) of this capacitance group 11, and the 4th drain electrode is in order to export an output signal Vout.Transistor T 5 has one the 5th source electrode, one the 5th grid and one the 5th drain electrode, and wherein the 5th grid receives this input signal Vin, and the 5th drain electrode is in order to export an output signal Vout, the 5th source ground.
When input signal Vin was high-voltage level, this moment, the voltage of output signal Vout was 0.But store the voltage of VDD in the drain electrode of transistor T 3 at this moment because of the relation of capacitance group 11.When input signal Vin was low voltage level, the voltage in the drain electrode of transistor T 3 be promoted to the voltage of 2VDD, so output voltage V out was 2VDD because of the reason of capacitance group 11 chargings at this moment.In the present invention, the capacitance of capacitance group 11 can change because of control signal Cs, in order to adjust the discharge time of capacitance group 11.
For more clearly demonstrating, please refer to Fig. 2.Fig. 2 is the circuit diagram of an embodiment of the capacitance group among Fig. 1.The source electrode of transistor T 6 and drain electrode, the source electrode of transistor T 7 is coupled in drain electrode with the source electrode of drain electrode and transistor T 8.The grid of transistor T 7 couples the grid of transistor T 8.The grid of transistor T 6 is coupled to a transmission gate 22.One termination of transmission gate 22 is received control signal Cs, and the other end couples inverter 21, in order to receive anti-phase control signal Cs.When transmission gate 22 not conductings, this moment, the capacitance of capacitance group 11 was determined by the electric capacity that transistor T 7 and transistor T 8 form.When transmission gate 22 conductings, this moment, the capacitance of capacitance group 11 was determined with the electric capacity that transistor T 8 forms by transistor T 6, transistor T 7.The sharp capacitance that just can change capacitance group 11 in such a way through control signal Cs is in order to adjust the discharge time of capacitance group 11.
Fig. 3 is the circuit diagram according to an embodiment of voltage level shifter of the present invention.First booster circuit 31 couples voltage source V DD1, receiving inputted signal Vin, and determine the voltage amplification multiplying power of this input signal Vin according to a control signal Sel.Second booster circuit 32 couples an inverter 33 and voltage source V DD1, receives the rp input signal that inverter 33 is produced according to input signal Vin, and determines the voltage amplification multiplying power of this rp input signal according to control signal Sel.Transistor T 11 has one first source electrode, one first drain electrode and a first grid, and wherein first source electrode couples voltage source V DD2, and first drain electrode couples an end of resistance R 1.Transistor T 12 has one second source electrode, one second drain electrode and a second grid, and wherein second source electrode couples voltage source V DD2, and second drain electrode couples an end of resistance R 2, and second grid couples the other end of resistance R 1.Transistor T 13 has one the 3rd source electrode, one the 3rd drain electrode and one the 3rd grid, and wherein the 3rd drain electrode couples second grid, and the 3rd grid receives the output signal of first booster circuit 31, the 3rd source ground.Transistor T 14 has one the 4th source electrode, one the 4th drain electrode and one the 4th grid, and wherein the 4th drain electrode couples first grid, and the 4th grid receives the output signal of second booster circuit 32, the 4th source ground.Transistor T 15 has one the 5th source electrode, one the 5th drain electrode and one the 5th grid, and wherein the 5th source electrode couples voltage source V DD2, and the 5th grid couples first grid.Transistor T 16 has one the 6th source electrode, one the 6th drain electrode and one the 6th grid, and wherein the 6th drain electrode couples the 5th drain electrode, and the 6th grid couples first grid, the 6th source ground.Transistor T 17 has one the 7th source electrode, one the 7th drain electrode and one the 7th grid, and wherein the 7th source electrode couples voltage source V DD2, and the 7th grid couples the 5th drain electrode and the 6th drain electrode, and the 7th drain electrode is then in order to output signal output Vout1 and couple an end of resistance R 3.Transistor T 18 has one the 8th source electrode, one the 8th drain electrode and one the 8th grid, and wherein the 8th source electrode couples voltage source V DD2, and the 8th grid couples first grid.Transistor T 19 has one the 9th source electrode, one the 9th drain electrode and one the 9th grid, and wherein the 9th drain electrode couples the 8th drain electrode, and the 9th grid couples first grid, the 9th source ground.Transistor T 20 has 1 the tenth source electrode, 1 the tenth drain electrode and 1 the tenth grid, and wherein the tenth grid couples the 8th drain electrode and the 9th drain electrode, and the tenth drain electrode couples the other end of resistance R 3, the tenth source ground.The negative electrode of diode 34 couples between the tenth drain electrode and the resistance R 3, the plus earth of diode 34.
When the output signal of second booster circuit 32 is low voltage level and transistor T 12 and T13 conducting, this moment transistor T 16 and T17 conducting, so the voltage level of output signal Vout1 is VDD2.Utilize such circuit, just can be earlier input signal Vin be seen through first booster circuit 31 or second booster circuit 32 earlier the voltage level of input signal Vin is risen to 2VDD1, utilize voltage level shift circuit (in Fig. 3 by transistor T 11～T20 and diode 34 composition) that the voltage level of input signal is risen to VDD2 once more again.Utilize circuit as shown in Figure 3, though integrated circuit has increased by first booster circuit 31 and second booster circuit 32, but its shared circuit layout area is little, and first booster circuit 31 and second booster circuit 32 all belong to the element of low-work voltage, therefore can not consume too many power.Utilize the voltage level shifter of Fig. 3 in addition, can avoid the generation of direct current, more do not have the problem of puncture voltage.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
11: capacitance group
T1, T2, T3, T4, T5, T6, T7, T8, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20: transistor
21,33: phase inverter
22: transmission gate
31: the first booster circuits
32: the second booster circuits
34: diode
Claims (8)
1. a booster circuit is characterized in that, this booster circuit comprises:
One the first transistor has one first source electrode, a first grid and one first drain electrode, and wherein this first source electrode couples a voltage source;
One transistor seconds has one second source electrode, a second grid and one second drain electrode, and wherein this second drain electrode couples this first drain electrode, this second source ground, and this second grid and this first grid receive an input signal;
One capacitance group has one first end and one second end, is controlled by a control signal to change its capacitance, and in order to change the discharge time of this capacitance group, wherein this first end couples this second drain electrode and this first drain electrode;
One the 3rd transistor has one the 3rd source electrode, one the 3rd grid and one the 3rd drain electrode, and wherein the 3rd source electrode couples this voltage source, and the 3rd grid couples an output signal end;
One the 4th transistor has one the 4th source electrode, one the 4th grid and one the 4th drain electrode, and wherein the 4th grid receives this input signal, and the 4th source electrode and the 3rd drain electrode couple this second end of this capacitance group, and the 4th drain electrode couples this output signal end; And
One the 5th transistor has one the 5th source electrode, one the 5th grid and one the 5th drain electrode, and wherein the 5th grid receives this input signal, and the 5th drain electrode couples this output signal end, the 5th source ground.
2. booster circuit according to claim 1, it is characterized in that, this capacitance group comprises that one first electric capacity and one second electric capacity are connected in parallel, and wherein this first electric capacity is coupled to a switching device, and determines according to this control signal whether this first electric capacity is in parallel with this second electric capacity.
3. booster circuit according to claim 2 is characterized in that, this first electric capacity and this second electric capacity all are made up of transistor.
4. booster circuit according to claim 2 is characterized in that, this switching device is a cmos transmission gate.
5. a voltage level shifter that uses booster circuit described in the claim 1 is characterized in that, this voltage level shifter comprises:
One first booster circuit receives an input signal, and determines the voltage amplification multiplying power of this input signal according to a control signal, and this first booster circuit is identical with the booster circuit described in the claim 1;
One inverter receives this input signal, produces a rp input signal;
One second booster circuit couples the output of this inverter, receives this rp input signal, and determines the voltage amplification multiplying power of this rp input signal according to this control signal, and this second booster circuit is identical with the booster circuit described in the claim 1; And
One voltage level shift circuit has a first input end and one second input, couples the output of this first booster circuit and this second booster circuit respectively, in order to voltage level shifting to one first voltage level with this input signal.
6. voltage level shifter according to claim 5, it is characterized in that, this capacitance group comprises that one first electric capacity and one second electric capacity are connected in parallel, and wherein this first electric capacity is coupled to a switching device, and determines according to this control signal whether this first electric capacity is in parallel with this second electric capacity.
7. voltage level shifter according to claim 6 is characterized in that, this first electric capacity and this second electric capacity all are made up of transistor.
8. voltage level shifter according to claim 6 is characterized in that, this switching device is a cmos transmission gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101617907A CN100536303C (en) | 2006-12-25 | 2006-12-25 | Voltage boost circuit and voltage level shifter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101617907A CN100536303C (en) | 2006-12-25 | 2006-12-25 | Voltage boost circuit and voltage level shifter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101212179A CN101212179A (en) | 2008-07-02 |
| CN100536303C true CN100536303C (en) | 2009-09-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101617907A Expired - Fee Related CN100536303C (en) | 2006-12-25 | 2006-12-25 | Voltage boost circuit and voltage level shifter |
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| CN (1) | CN100536303C (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9584011B1 (en) * | 2016-01-06 | 2017-02-28 | Semiconductor Components Industries, Llc | Capacitive coupled input transfer gates |
| CN108932006B (en) * | 2017-05-26 | 2020-04-10 | 新唐科技股份有限公司 | Level conversion circuit |
| US10498315B2 (en) * | 2018-03-05 | 2019-12-03 | Texas Instruments Incorporated | Level shifter circuit |
| TWI675273B (en) * | 2019-03-28 | 2019-10-21 | 友達光電股份有限公司 | Voltage boosting circuit, output buffer circuit and display panel |
| CN111010164B (en) * | 2019-12-24 | 2023-08-25 | 中电国基南方集团有限公司 | Output buffer circuit based on GaAs technology |
| CN112769319B (en) * | 2021-04-06 | 2021-06-25 | 深圳市拓尔微电子有限责任公司 | Level conversion module, drive circuit and control chip |
| CN115833576B (en) * | 2022-12-19 | 2024-08-30 | 珠海极海半导体有限公司 | Low-power consumption control circuit and micro-processing chip |
Citations (5)
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|---|---|---|---|---|
| JP2001025237A (en) * | 1999-07-08 | 2001-01-26 | Nec Ic Microcomput Syst Ltd | Voltage raise circuit |
| EP1247327A2 (en) * | 2000-01-14 | 2002-10-09 | Infineon Technologies AG | Circuit arrangement for applying a supply voltage to a load |
| JP2002315311A (en) * | 2001-04-18 | 2002-10-25 | Rohm Co Ltd | Switching regulator |
| CN1619932A (en) * | 2003-11-14 | 2005-05-25 | 松下电器产业株式会社 | DC-DC converter |
| WO2005074110A1 (en) * | 2004-01-28 | 2005-08-11 | Renesas Technology Corp. | Switching power supply and semiconductor integrated circuit |
-
2006
- 2006-12-25 CN CNB2006101617907A patent/CN100536303C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001025237A (en) * | 1999-07-08 | 2001-01-26 | Nec Ic Microcomput Syst Ltd | Voltage raise circuit |
| EP1247327A2 (en) * | 2000-01-14 | 2002-10-09 | Infineon Technologies AG | Circuit arrangement for applying a supply voltage to a load |
| JP2002315311A (en) * | 2001-04-18 | 2002-10-25 | Rohm Co Ltd | Switching regulator |
| CN1619932A (en) * | 2003-11-14 | 2005-05-25 | 松下电器产业株式会社 | DC-DC converter |
| WO2005074110A1 (en) * | 2004-01-28 | 2005-08-11 | Renesas Technology Corp. | Switching power supply and semiconductor integrated circuit |
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| Publication number | Publication date |
|---|---|
| CN101212179A (en) | 2008-07-02 |
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Assignee: Pucheng Science and Technology Co., Ltd. Assignor: Universal technology (Shenzhen) Co., Ltd. Contract record no.: 2010990000884 Denomination of invention: Voltage boost circuit and voltage level shifter Granted publication date: 20090902 License type: Exclusive License Open date: 20080702 Record date: 20101108 |
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| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Universal technology (Shenzhen) Co., Ltd. Assignor: Pucheng Science and Technology Co., Ltd. Contract record no.: 2010990000884 Denomination of invention: Voltage boost circuit and voltage level shifter Granted publication date: 20090902 License type: Exclusive License Open date: 20080702 Record date: 20101108 |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090902 Termination date: 20171225 |
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| CF01 | Termination of patent right due to non-payment of annual fee |