CN115065248B

CN115065248B - Boost converter circuit and boost converter

Info

Publication number: CN115065248B
Application number: CN202210993826.7A
Authority: CN
Inventors: 李海波; 丛锋; 戴兴科
Original assignee: Shenzhen Weiyuan Semiconductor Co ltd
Current assignee: Shenzhen Weiyuan Semiconductor Co ltd
Priority date: 2022-08-18
Filing date: 2022-08-18
Publication date: 2022-11-15
Anticipated expiration: 2042-08-18
Also published as: CN115065248A

Abstract

The application is suitable for the technical field of power electronics, and provides a boost conversion circuit and a boost converter. The boost conversion circuit comprises a first driving module, a second driving module, a logic module and a boost conversion module. The switching tube in the boost conversion module is in a turn-off process and the first voltage signal is in a rising stage under the action of the second driving signal or the switching tube in the boost conversion module is in a conduction process and the first voltage signal is in a falling stage under the action of the second driving signal, and the follow current tube in the boost conversion module is in a weak conduction state under the action of the first driving signal. The boost converter circuit provided by the embodiment of the application solves the problems that the overshoot voltage of the switching node in the synchronous rectification boost converter is too large during the dead zone of switching, so that the device is in a breakdown risk, and the reliability of the system is reduced.

Description

Boost converter circuit and boost converter

Technical Field

The application belongs to the technical field of power electronics, and particularly relates to a boost conversion circuit and a boost converter.

Background

In the synchronous rectification boost converter, in order to avoid the chip damage caused by the current break-through of the switching tube and the follow current tube, a certain dead time is often set on the design of the driving circuit to ensure that before one tube is conducted, the other tube is in a closed state to avoid the simultaneous conduction of the switching tube and the follow current tube, but the overshoot voltage of the switching node in the synchronous rectification boost converter is overlarge, so that the device has the risk of breakdown, and the reliability of the system is reduced.

Disclosure of Invention

The embodiment of the application provides a boost converter circuit and a boost converter, and can solve the problems that overshoot voltage of a switching node in a synchronous rectification boost converter is too large during a dead zone period of switching, so that a device is in a breakdown risk, and the reliability of a system is reduced.

In a first aspect, an embodiment of the present application provides a boost conversion circuit, including a first driving module, a second driving module, a logic module, and a boost conversion module, where the first driving module is electrically connected to the logic module and the boost conversion module, the second driving module is electrically connected to the logic module and the boost conversion module, and the boost conversion module is electrically connected to the logic module;

the logic module is used for receiving a control signal and a first voltage signal, and outputting a first logic signal, a second logic signal, a third logic signal, a fourth logic signal, a fifth logic signal and a sixth logic signal according to the control signal and the first voltage signal, wherein the first voltage signal is a voltage signal at a switch node in the boost conversion module; the first driving module is used for outputting a first driving signal according to the first voltage signal, the first logic signal, the second logic signal and the third logic signal; the second driving module is configured to output a second driving signal according to the first voltage signal, the fourth logic signal, the fifth logic signal, and the sixth logic signal; the switching tube in the boost conversion module is in a turn-off process and the first voltage signal is in a rising stage under the action of the second driving signal or the switching tube in the boost conversion module is in a conduction process and the first voltage signal is in a falling stage under the action of the second driving signal, and the follow current tube in the boost conversion module is in a weak conduction state under the action of the first driving signal.

In a possible implementation manner of the first aspect, the first driving module includes a first switching tube, a second switching tube, a third switching tube, a fourth switching tube, a fifth switching tube, a sixth switching tube, a seventh switching tube, a first resistor, and a second resistor;

the source electrode of the first switch tube, the source electrode of the second switch tube and the source electrode of the fourth switch tube are all used for receiving a second voltage signal, the grid electrode of the first switch tube and the grid electrode of the second switch tube are all electrically connected with the logic module and are used for receiving the first logic signal, the drain electrode of the first switch tube is electrically connected with the first end of the first resistor, the second end of the first resistor is respectively electrically connected with the drain electrode of the seventh switch tube, the drain electrode of the third switch tube, the drain electrode of the fifth switch tube, the first end of the second resistor and the boost conversion module, the second end of the first resistor is used for outputting the first driving signal, the grid electrode of the seventh switch tube and the grid electrode of the fourth switch tube are electrically connected with the logic module and are used for receiving the second logic signal, the source electrode of the seventh switch tube is grounded, the drain electrode of the second switch tube is electrically connected with the source electrode of the third switch tube, the grid electrode of the third switch tube is electrically connected with the boost conversion module and is used for receiving the first voltage signal, the drain electrode of the sixth switch tube is electrically connected with the drain electrode of the sixth switch tube and the drain electrode of the sixth switch tube, and the drain electrode of the third switch tube is electrically connected with the drain electrode of the logic module and the drain electrode of the sixth switch tube.

In a possible implementation manner of the first aspect, the second driving module includes an eighth switching tube, a ninth switching tube, a tenth switching tube, an eleventh switching tube, a twelfth switching tube, a third resistor, and a fourth resistor;

the source electrode of the eighth switching tube and the source electrode of the ninth switching tube are both used for receiving a second voltage signal, the gate electrode of the eighth switching tube and the gate electrode of the ninth switching tube are both electrically connected with the logic module and are used for receiving the fourth logic signal, the drain electrode of the eighth switching tube is electrically connected with the first end of the third resistor, the second end of the third resistor is respectively electrically connected with the first end of the fourth resistor, the drain electrode of the tenth switching tube, the drain electrode of the twelfth switching tube and the boost conversion module, the second end of the third resistor is used for outputting the second driving signal, the second end of the fourth resistor is electrically connected with the drain electrode of the eleventh switching tube, the gate electrode of the eleventh switching tube is electrically connected with the logic module and is used for receiving the fifth logic signal, the gate electrode of the twelfth switching tube is electrically connected with the logic module and is used for receiving the sixth logic signal, the source electrode of the eleventh switching tube and the source electrode of the twelfth switching tube are both grounded, the drain electrode of the ninth switching tube is electrically connected with the source electrode of the tenth switching tube and is used for receiving the tenth voltage signal, and the first switching module is electrically connected with the boost conversion module.

In a possible implementation manner of the first aspect, the logic module includes a first logic unit, a second logic unit, a third logic unit, a fourth logic unit, a fifth logic unit, and a delay unit; the first logic unit is electrically connected with the second logic unit, the fourth logic unit and the first driving module respectively, the second logic unit is electrically connected with the first driving module and the delay unit respectively, the third logic unit is electrically connected with the first driving module and the boost conversion module respectively, the fourth logic unit is electrically connected with the second driving module and the fifth logic unit respectively, the fifth logic unit is electrically connected with the second driving module and the delay unit respectively, and the delay unit is electrically connected with the second driving module;

the first logic unit is used for receiving the control signal and the second logic signal and outputting the first logic signal according to the control signal and the second logic signal; the second logic unit is configured to receive the control signal, the first logic signal, and the sixth logic signal, and output the second logic signal according to the control signal, the first logic signal, and the sixth logic signal; the third logic unit is used for receiving the control signal and the first voltage signal and outputting the third logic signal according to the control signal and the first voltage signal; the fourth logic unit is configured to receive the control signal, the first logic signal, and the fifth logic signal, and output the fourth logic signal according to the control signal, the first logic signal, and the fifth logic signal; the fifth logic unit is configured to receive the fourth logic signal and output the fifth logic signal according to the fourth logic signal; the delay unit is configured to delay the fifth logic signal and output the sixth logic signal.

In one possible implementation manner of the first aspect, the first logic unit includes a first inverter, a first nor gate, and a second inverter;

the input end of the first phase inverter is used for receiving the control signal, the output end of the first phase inverter is electrically connected with the first input end of the first NOR gate, the second input end of the first NOR gate is electrically connected with the second logic unit and used for receiving the second logic signal, the output end of the first NOR gate is electrically connected with the input end of the second phase inverter, the output end of the second phase inverter is electrically connected with the first driving module, the second logic unit and the fourth logic unit respectively, and the output end of the second phase inverter is used for outputting the first logic signal.

In one possible implementation manner of the first aspect, the second logic unit includes a third inverter, a second nor gate, a first nand gate, and a fourth inverter;

the input end of the third inverter is electrically connected to the delay unit and configured to receive the sixth logic signal, the output end of the third inverter is electrically connected to the first input end of the second nor gate, the second input end of the second nor gate is configured to receive the control signal, the output end of the second nor gate is electrically connected to the first input end of the first nand gate, the second input end of the first nand gate is electrically connected to the first logic unit and configured to receive the first logic signal, the output end of the first nand gate is electrically connected to the input end of the fourth inverter, the output ends of the fourth inverter are electrically connected to the first logic unit and the first driving module, respectively, and the output end of the fourth inverter is configured to output the second logic signal.

In one possible implementation manner of the first aspect, the third logic unit includes a fifth inverter and a third nor gate;

the input end of the fifth inverter is electrically connected with the boost conversion module and is used for receiving the first voltage signal, the output end of the fifth inverter is electrically connected with the first input end of the third nor gate, the second input end of the third nor gate is used for receiving the control signal, and the output end of the third nor gate is electrically connected with the first driving module and is used for outputting the third logic signal.

In one possible implementation manner of the first aspect, the fourth logic unit includes a sixth inverter, a second nand gate, a fourth nor gate, and a seventh inverter;

an input end of the sixth inverter is electrically connected to the first logic unit and configured to receive the first logic signal, an output end of the sixth inverter is electrically connected to a first input end of the second nand gate, a second input end of the second nand gate is configured to receive the control signal, output ends of the second nand gate are electrically connected to the first input end of the fourth nor gate and the fifth logic unit, respectively, a second input end of the fourth nor gate is electrically connected to the fifth logic unit and configured to receive the fifth logic signal, an output end of the fourth nor gate is electrically connected to an input end of the seventh inverter, an output end of the seventh inverter is electrically connected to the second driving module and the fifth logic unit, respectively, and an output end of the seventh inverter is configured to output the fourth logic signal.

In one possible implementation manner of the first aspect, the fifth logic unit includes a third nand gate and an eighth inverter;

a first input end of the third nand gate is electrically connected to the fourth logic unit and configured to receive the fourth logic signal, a second input end of the third nand gate is electrically connected to the fourth logic unit, an output end of the third nand gate is electrically connected to an input end of the eighth inverter, an output end of the eighth inverter is electrically connected to the fourth logic unit, the second driving module, and the delay unit, respectively, and an output end of the eighth inverter is configured to output the fifth logic signal.

In a second aspect, an embodiment of the present application provides a boost converter, including the boost converter circuit described in any one of the first aspects.

Compared with the prior art, the embodiment of the application has the advantages that:

the embodiment of the application provides a boost conversion circuit, wherein a logic module is used for receiving a control signal and a first voltage signal, and outputting a first logic signal, a second logic signal, a third logic signal, a fourth logic signal, a fifth logic signal and a sixth logic signal according to the control signal and the first voltage signal, wherein the first voltage signal is a voltage signal at a switch node in the boost conversion module. The first driving module is used for outputting a first driving signal according to the first voltage signal, the first logic signal, the second logic signal and the third logic signal. The second driving module is used for outputting a second driving signal according to the first voltage signal, the fourth logic signal, the fifth logic signal and the sixth logic signal. The switching tube in the boost conversion module is in a turn-off process and the first voltage signal is in a rising stage under the action of the second driving signal or the switching tube in the boost conversion module is in a conducting process and the first voltage signal is in a falling stage under the action of the second driving signal, and the follow current tube in the boost conversion module is in a weak conducting state under the action of the first driving signal. It can be seen from the above that, in the on-process or off-process of the switching tube in the boost conversion module, the freewheeling tube in the boost conversion module is in the weak on-state, so that the first voltage signal is not too high, even if the voltage signal at the switching node in the boost conversion module is not too high, the purpose of reducing the overshoot voltage at the switching node in the boost conversion module is achieved, and the reliability of the system is improved.

It is understood that the beneficial effects of the second aspect can be referred to the related description of the first aspect, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the embodiments or the prior art description will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings may be obtained according to these drawings without inventive labor.

Fig. 1 is a schematic block diagram of a boost converter circuit according to an embodiment of the present application;

fig. 2 is a schematic block diagram of a boost converter circuit according to another embodiment of the present application;

fig. 3 is a circuit connection diagram of a boost converter circuit according to another embodiment of the present application;

fig. 4 is a timing diagram illustrating an operation of the boost converter circuit according to an embodiment of the present disclosure.

In the figure: 10. a first driving module; 20. a second driving module; 30. a logic module; 31. a first logic unit; 32. a second logic unit; 33. a third logic unit; 34. a fourth logic unit; 35. a fifth logic unit; 36. a delay unit; 40. and a boost conversion module.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

As used in the specification of this application and the appended claims, the term "if" may be interpreted contextually as "when …" or "once" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.

As shown in fig. 1, an embodiment of the present application provides a boost converter circuit, which includes a first driver module 10, a second driver module 20, a logic module 30, and a boost converter module 40. The first driving module 10 is electrically connected to the logic module 30 and the boost conversion module 40, the second driving module 20 is electrically connected to the logic module 30 and the boost conversion module 40, and the boost conversion module 40 is electrically connected to the logic module 30.

Specifically, the logic module 30 is configured to receive the control signal PWM and the first voltage signal VX, and output a first logic signal L1, a second logic signal L2, a third logic signal L3, a fourth logic signal L4, a fifth logic signal L5, and a sixth logic signal L6 according to the control signal PWM and the first voltage signal VX, where the first voltage signal VX is a voltage signal at a switch node in the boost converter module 40. The first driving module 10 is configured to output a first driving signal PGATE according to the first voltage signal VX, the first logic signal L1, the second logic signal L2, and the third logic signal L3. The second driving module 20 is configured to output a second driving signal NGATE according to the first voltage signal VX, the fourth logic signal L4, the fifth logic signal L5, and the sixth logic signal L6. The switching tube in the boost conversion module 40 is in the turn-off process and the first voltage signal VX is in the rising stage under the action of the second driving signal NGATE, or the switching tube in the boost conversion module 40 is in the turn-on process and the first voltage signal VX is in the falling stage under the action of the second driving signal NGATE, and the freewheeling tube in the boost conversion module 40 is in the weak turn-on state under the action of the first driving signal PGATE. As can be seen from the above, in the on-process or the off-process of the switching tube in the boost conversion module 40, the freewheeling tube in the boost conversion module 40 is in the weak on-state, so that the first voltage signal VX is not too high, even if the voltage signal at the switching node in the boost conversion module 40 is not too high, the purpose of reducing the overshoot voltage at the switching node in the boost conversion module 40 is achieved, and the reliability of the system is improved.

It should be noted that the weak conduction state means that the current tube has a certain conduction capability, but it is not completely conducted.

As shown in fig. 3, the boost converter module 40 includes an inductor L, an output capacitor Cout, a freewheeling tube P0, and a switching tube N0. The first end of the inductor L is used for receiving a power supply voltage VIN, the second end of the inductor L is electrically connected with the drain of the follow current tube P0 and the drain of the switching tube NO, respectively, a common end of the inductor L, the follow current tube P0 and the switching tube NO is a switching node of the boost conversion module 40, and a voltage signal at the switching node of the boost conversion module 40 is a first voltage signal VX. The gate of the freewheeling tube P0 is electrically connected to the first driving module 10 and is configured to receive the first driving signal PGATE. The source of the freewheeling tube P0 is electrically connected to the first end of the output capacitor Cout, the common end of the freewheeling tube P0 and the output capacitor Cout is the output end of the boost conversion module 40, and the voltage at the output end of the boost conversion module 40 is the output voltage Vout. The gate of the switching tube N0 is electrically connected to the second driving module 20, and is configured to receive the second driving signal NGATE. The source of the switch tube N0 is grounded, and the second end of the output capacitor Cout is grounded.

Specifically, when the freewheeling tube P0 is in an off state under the action of the first driving signal PGATE and the switching tube N0 is in an on state under the action of the second driving signal NGATE, the inductor L stores energy, and the first voltage signal VX is a low potential.

When the freewheeling tube P0 is in a conducting state under the action of the first driving signal PGATE and the switching tube N0 is in an off state under the action of the second driving signal NGATE, the inductor L discharges, and the first voltage signal VX changes from a low potential to a high potential.

During the dead zone of the switching, if the freewheeling tube P0 and the switching tube N0 are both in the off state, the first voltage signal VX at the switching node is too high, so that the risk of breaking down the device connected to the switching node exists, and the reliability of the system is reduced, so when the switching tube N0 is in the off process under the action of the second driving signal NGATE and the first voltage signal VX is in the rising stage or the switching tube N0 is in the on process under the action of the second driving signal NGATE and the first voltage signal VX is in the falling stage, the freewheeling tube P0 is in the weak on state under the action of the first driving signal PGATE, so that the first voltage signal VX is not too high, even if the voltage signal at the switching node in the boost conversion module 40 is not too high, the purpose of reducing the voltage at the switching node in the boost conversion module 40 is achieved, and the reliability of the system is improved.

Furthermore, the follow current tube P0 is a PMOS tube, and the switch tube N0 is an NMOS tube.

As shown in fig. 3, the first driving module 10 includes a first switching tube M1, a second switching tube M2, a third switching tube M3, a fourth switching tube M4, a fifth switching tube M5, a sixth switching tube M6, a seventh switching tube M7, a first resistor R1, and a second resistor R2. The source of the first switching tube M1, the source of the second switching tube M2, and the source of the fourth switching tube M4 are all configured to receive the second voltage signal VMAX, the gate of the first switching tube M1 and the gate of the second switching tube M2 are all electrically connected to the logic module 30, and are configured to receive the first logic signal L1, the drain of the first switching tube M1 is electrically connected to the first end of the first resistor R1, the second end of the first resistor R1 is respectively electrically connected to the drain of the seventh switching tube M7, the drain of the third switching tube M3, the drain of the fifth switching tube M5, the first end of the second resistor R2, and the boost conversion module 40, the second end of the first resistor R1 is configured to output the first driving signal PGATE, the gate of the seventh switching tube M7 and the gate of the fourth switching tube M4 are both electrically connected to the logic module 30, and are configured to receive the second logic signal L2, the source of the seventh switching tube M7 is grounded, the drain of the second switching tube M2 is electrically connected to the source of the third switching tube M3, the drain of the fourth switching tube M6 is electrically connected to the sixth switching tube M6, and the drain of the sixth switching tube M6 are electrically connected to receive the gate of the third switching tube M6, and the drain of the sixth switching tube M6, and the gate of the sixth switching tube M6 are electrically connected to receive the gate of the third switching tube.

As can be seen from fig. 3, the second end of the first resistor R1 is electrically connected to the drain of the seventh switching tube M7, the drain of the third switching tube M3, the drain of the fifth switching tube M5, the first end of the second resistor R2, and the gate of the freewheeling tube P0 in the boost conversion module 40, respectively. The gate of the third switching tube M3 is electrically connected to the switching node of the boost conversion module 40.

Specifically, as shown in fig. 4, when the control signal PWM changes from high level to low level, the first logic signal L1 changes from low level to high level, and the fourth logic signal L4 and the fifth logic signal L5 change from low level to high level. At this time, the switch tube N0 is in the turn-off process under the action of the second drive signal NGATE, so that the first voltage signal VX starts to increase, after the third logic signal L3 changes from the low level to the high level after rising to a certain value, at this time, the second logic signal L2 still maintains the low level, the path where the fourth switch tube M4, the fifth switch tube M5, the second resistor R2 and the sixth switch tube M6 are located is turned on, the fourth switch tube M4 is completely turned on, which is equivalent to a conducting wire, the connection mode of the fifth switch tube M5 is equivalent to the connection mode of a diode, therefore, when the path where the fourth switch tube M4, the fifth switch tube M5, the second resistor R2 and the sixth switch tube M6 are located is turned on, the first drive signal pgp 0 is pulled down to the VMAX-VGS voltage, the pgp 0 is in the weak on state under the action of the first drive signal, at this time, a part of the current on the inductor L flows to the switch tube N0, a part of the ate flows to the second switch tube P0 through the switch tube P0, and the voltage of the boost switch tube P0 is gradually changed, so that the boost tube P0 flows to the output end of the boost switch tube P0, the boost switch module, and the boost switch tube P0 is not to cause the problem that the boost switch tube P0 to overshoot. In addition, the problem that the efficiency is reduced and even the device is damaged because the charge of the output capacitor Cout flows back to the switching node and the ground due to the fact that the follow current tube P0 is completely conducted in the turn-off process of the switching tube N0 can be avoided.

When the first voltage signal VX becomes the normal value, the sixth logic signal L6 changes from the low level to the high level, at this time the second drive signal NGATE quickly changes to the low level, the switching tube N0 is completely turned off, and then the second logic signal L2 changes from the low level to the high level, so that the fourth switching tube M4 and the fifth switching tube M5 are turned off, the seventh switching tube M7 is turned on, so that the first drive signal PGATE quickly changes to the low level, and the freewheeling tube P0 is completely turned on.

When the control signal PWM changes from low level to high level, the first logic signal L1, the second logic signal L2, and the third logic signal L3 all change from high level to low level, the seventh switching tube M7 is turned off, the eighth switching tube M8 is turned off, the first switching tube M1 is turned on, the second switching tube M2 is turned on, the fourth switching tube M4 is turned on, the fifth switching tube M5 is turned on, because the first voltage signal VX is high potential, the third switching tube M3 is still in an off state, because the fourth switching tube M4 and the fifth switching tube M5 are turned on, the first driving signal PGATE rapidly rises to VMAX-VGS voltage, the freewheeling tube P0 is in a weak on state under the action of the first driving signal PGATE, and thereafter, under the action of the first switching tube M1 and the first resistor R1, the first driving signal PGATE continues to slowly rise. Meanwhile, the fourth logic signal L4, the fifth logic signal L5, and the sixth logic signal L6 change from high level to low level, the second driving signal NGATE rises slowly, when the second driving signal NGATE rises to a voltage greater than the turn-on threshold voltage of the switching tube N0, the switching tube N0 is turned on, a part of the upper current of the inductor L flows to the switching tube N0, a part of the upper current flows to the output end of the boost converter module 40 through the follow current tube P0, and the current flowing to the switching tube N0 is larger and smaller, so that the first voltage signal VX is not too high. Before the switching tube N0 is not fully turned on, the freewheeling tube P0 is always in a weak on state, so that the problem of excessive overshoot voltage at the switching node in the boost conversion module 40 caused by complete turn-off of the freewheeling tube P0 is avoided. In addition, the problem that the efficiency is reduced and even the device is damaged because the charge of the output capacitor Cout flows back to the switching node and the ground because the follow current tube P0 is completely conducted in the conducting process of the switching tube N0 can be avoided. When the current corresponding to the switch tube N0 is greater than the current on the inductor L, the first voltage signal VX starts to fall, and when the current falls to a certain value, the third switch tube M3 is turned on, so that the first driving signal PGATE rapidly rises to the second voltage signal VMAX, the follow current tube P0 is completely turned off, the occurrence of reverse current is further prevented, and meanwhile, the second driving signal NGATE rapidly rises, and the switch tube N0 is completely turned on.

Further, the first switching tube M1, the second switching tube M2, the third switching tube M3, the fourth switching tube M4 and the fifth switching tube M5 are PMOS tubes. The sixth switching tube M6 and the seventh switching tube M7 are both NMOS tubes.

As shown in fig. 3, the second driving module 20 includes an eighth switching tube M8, a ninth switching tube M9, a tenth switching tube M10, an eleventh switching tube M11, a twelfth switching tube M12, a third resistor R3, and a fourth resistor R4. The source of the eighth switching tube M8 and the source of the ninth switching tube M9 are both configured to receive the second voltage signal VMAX, the gate of the eighth switching tube M8 and the gate of the ninth switching tube M9 are both electrically connected to the logic module 30 and configured to receive the fourth logic signal L4, the drain of the eighth switching tube M8 is electrically connected to the first end of the third resistor R3, the second end of the third resistor R3 is respectively electrically connected to the first end of the fourth resistor R4, the drain of the tenth switching tube M10, the drain of the twelfth switching tube M12 and the boost conversion module 40, the second end of the third resistor R3 is configured to output the second driving signal NGATE, the second end of the fourth resistor R4 is electrically connected to the drain of the eleventh switching tube M11, the gate of the eleventh switching tube M11 is electrically connected to the logic module 30 and configured to receive the fifth logic signal L5, the gate of the twelfth switching tube M12 is electrically connected to the logic module 30 and configured to receive the sixth logic signal L6, the source of the eleventh switching tube M11 and the source of the twelfth switching tube M12, the source of the ninth switching tube M9 is electrically connected to the drain of the tenth switching tube VX, and the tenth switching tube M10 is electrically connected to receive the voltage signal VX 10.

As can be seen from fig. 3, the second end of the third resistor R3 is electrically connected to the first end of the fourth resistor R4, the drain of the tenth switching tube M10, the drain of the twelfth switching tube M12, and the gate of the switching tube N0 in the boost converter module 40, respectively. The gate of the tenth switching tube M10 is electrically connected to the switching node of the boost converter module 40.

Specifically, when the control signal PWM changes from high level to low level, the first logic signal L1 changes from low level to high level, and the fourth logic signal L4 and the fifth logic signal L5 change from low level to high level. The eleventh switch tube M11 is turned on, the second driving signal NGATE discharges through the fourth resistor R4 and the eleventh switch tube M11 and starts to fall, when the second driving signal NGATE falls to a state where the current corresponding to the switch tube N0 is smaller than the current on the inductor L, the first voltage signal VX starts to increase, due to the limitation of the fourth resistor R4, the discharge current of the second driving signal NGATE is relatively small, the turn-off process of the switch tube NO is relatively slow, the rising slope of the first voltage signal VX is controlled to be relatively small, and the first voltage signal VX is prevented from being rapidly charged. When the first voltage signal VX rises to a certain value, the third logic signal L3 changes from low level to high level, and at this time, the second logic signal L2 still maintains low level, then the path where the fourth switching tube M4, the fifth switching tube M5, the second resistor R2, and the sixth switching tube M6 are located is turned on, the fourth switching tube M4 is completely turned on, which is equivalent to a wire, and the connection mode of the fifth switching tube M5 is equivalent to the connection mode of a diode, so when the path where the fourth switching tube M4, the fifth switching tube M5, the second resistor R2, and the sixth switching tube M6 are located is turned on, the first driving signal PGATE is pulled down to the VMAX-VGS voltage, the freewheeling tube P0 is in a weak conduction state under the action of the first driving signal pg0, at this time, a part of the current on the inductor L flows to the switching tube N0, and a part of the current flows to the output end of the boost conversion module 40 through the freewheeling tube P0, and since the switching tube N0 is in an off process, the current of the ate flows to the switching tube N0, and the voltage of the boost conversion module 40 can not overshoot, and the voltage of the first switching tube P0 can overshoot. In addition, the problem that the efficiency is reduced and even the device is damaged because the charge of the output capacitor Cout flows back to the switching node and the ground due to the fact that the follow current tube P0 is completely conducted in the turn-off process of the switching tube N0 can be avoided.

When the first voltage signal VX becomes the normal value, the sixth logic signal L6 becomes the high level from the low level, the twelfth switching tube M12 is turned on, so that the second drive signal NGATE quickly becomes the low level, the switching tube N0 is completely turned off, and subsequently the second logic signal L2 becomes the high level from the low level, so that the fourth switching tube M4 and the fifth switching tube M5 are turned off, the seventh switching tube M7 is turned on, so that the first drive signal PGATE quickly becomes the low level, and the freewheeling tube P0 is completely turned on.

When the control signal PWM changes from low level to high level, the first logic signal L1, the second logic signal L2, and the third logic signal L3 all change from high level to low level, the seventh switching tube M7 is turned off, the eighth switching tube M8 is turned off, the first switching tube M1 is turned on, the second switching tube M2 is turned on, the fourth switching tube M4 is turned on, the fifth switching tube M5 is turned on, because the first voltage signal VX is high potential, the third switching tube M3 is still in an off state, because the fourth switching tube M4 and the fifth switching tube M5 are turned on, the first driving signal PGATE rapidly rises to VMAX-VGS voltage, the freewheeling tube P0 is in a weak on state under the action of the first driving signal PGATE, and thereafter, under the action of the first switching tube M1 and the first resistor R1, the first driving signal PGATE continues to slowly rise. Meanwhile, the fourth logic signal L4, the fifth logic signal L5 and the sixth logic signal L6 are changed from high level to low level, the eleventh switch M11 is turned off, the twelfth switch M12 is turned off, the eighth switch M8 is turned on, the ninth switch M9 is turned on, since the first voltage signal VX is high level, the tenth switch M10 is turned off, the second driving signal NGATE is charged through the eighth switch M8 and the third resistor R3 and rises slowly, when the second driving signal NGATE rises to a voltage higher than the turn-on threshold voltage of the switch N0, the switch N0 is turned on, a part of the upper current of the inductor L flows to the switch N0, a part of the upper current flows to the output end of the boost conversion module 40 through the freewheeling tube P0, and the current flowing to the switch N0 is larger and larger, and the current flowing to the freewheeling tube P0 is smaller and smaller, so that the first voltage signal VX is not too high. Before the switching tube N0 is not fully turned on, the freewheeling tube P0 is always in a weak on state, so that the problem of excessive overshoot voltage at the switching node in the boost conversion module 40 caused by complete turn-off of the freewheeling tube P0 is avoided. In addition, the problem that the efficiency is reduced and even the device is damaged because the charge of the output capacitor Cout flows back to the switching node and the ground due to the fact that the follow current tube P0 is completely conducted in the conducting process of the switching tube N0 can be avoided.

When the corresponding current of the switch tube N0 is greater than the current on the inductor L, the first voltage signal VX starts to drop, and when the current drops to a certain value, the third switch tube M3 is turned on, so that the first driving signal PGATE rapidly rises to the second voltage signal VMAX, the follow current tube P0 is completely turned off, further preventing the occurrence of the backward flow current, and at the same time, the tenth switch tube M10 is turned on, so that the second driving signal NGATE rapidly rises to the second voltage signal VMAX, and the switch tube N0 is completely turned on.

Furthermore, the eighth switch tube M8, the ninth switch tube M9 and the tenth switch tube M10 are PMOS tubes, and the eleventh switch tube M11 and the twelfth switch tube M12 are NMOS tubes.

Note that the second voltage signal VMAX is the maximum value of the power supply voltage VIN and the output voltage Vout. When the supply voltage VIN is greater than the output voltage Vout, the second voltage signal VMAX is the supply voltage VIN, and when the supply voltage VIN is less than the output voltage Vout, the second voltage signal VMAX is the output voltage Vout.

As shown in fig. 2, the logic module 30 includes a first logic unit 31, a second logic unit 32, a third logic unit 33, a fourth logic unit 34, a fifth logic unit 35, and a delay unit 36. The first logic unit 31 is electrically connected with the second logic unit 32, the fourth logic unit 34 and the first driving module 10, the second logic unit 32 is electrically connected with the first driving module 10 and the delay unit 36, the third logic unit 33 is electrically connected with the first driving module 10 and the boost conversion module 40, the fourth logic unit 34 is electrically connected with the second driving module 20 and the fifth logic unit 35, the fifth logic unit 35 is electrically connected with the second driving module 20 and the delay unit 36, and the delay unit 36 is electrically connected with the second driving module 20.

Specifically, the first logic unit 31 is configured to receive the control signal PWM and the second logic signal L2, and output the first logic signal L1 according to the control signal PWM and the second logic signal L2. The second logic unit 32 is configured to receive the control signal PWM, the first logic signal L1, and the sixth logic signal L6, and output a second logic signal L2 according to the control signal PWM, the first logic signal L1, and the sixth logic signal L6. The third logic unit 33 is configured to receive the control signal PWM and the first voltage signal VX, and output a third logic signal L3 according to the control signal PWM and the first voltage signal VX. The fourth logic unit 34 is configured to receive the control signal PWM, the first logic signal L1, and the fifth logic signal L5, and output a fourth logic signal L4 according to the control signal PWM, the first logic signal L1, and the fifth logic signal L5. The fifth logic unit 35 is configured to receive the fourth logic signal L4 and output a fifth logic signal L5 according to the fourth logic signal L4. The delay unit 36 is configured to delay the fifth logic signal L5 and output a sixth logic signal L6.

As shown in fig. 3, the first logic unit 31 includes a first inverter F1, a first nor gate H1, and a second inverter F2. The input end of the first inverter F1 is configured to receive the control signal PWM, the output end of the first inverter F1 is electrically connected to the first input end of the first nor gate H1, the second input end of the first nor gate H1 is electrically connected to the second logic unit 32 and configured to receive the second logic signal L2, the output end of the first nor gate H1 is electrically connected to the input end of the second inverter F2, the output end of the second inverter F2 is electrically connected to the first driving module 10, the second logic unit 32 and the fourth logic unit 34, respectively, and the output end of the second inverter F2 is configured to output the first logic signal L1.

As can be seen from fig. 3, the output end of the second inverter F2 is electrically connected to the gate of the first switching tube M1, the gate of the second switching tube M2, the second logic unit 32 and the fourth logic unit 34 in the first driving module 10, respectively.

Specifically, when the control signal PWM changes from high level to low level, the control signal PWM changes the first logic signal L1 from low level to high level immediately after passing through the first inverter F1, the first nor gate H1, and the second inverter F2.

When the control signal PWM changes from low level to high level, the second logic signal L2 changes to low level, the control signal PWM changes to low level after passing through the first inverter F1, at this time, both input ends of the first nor gate H1 are at low level, the output of the first nor gate H1 is at high level, and the first logic signal L1 changes to low level after being inverted by the first inverter F1.

As shown in fig. 3, the second logic unit 32 includes a third inverter F3, a second nor gate H2, a first nand gate Y1, and a fourth inverter F4. The input end of the third inverter F3 is electrically connected to the delay unit 36 and configured to receive the sixth logic signal L6, the output end of the third inverter F3 is electrically connected to the first input end of the second nor gate H2, the second input end of the second nor gate H2 is configured to receive the control signal PWM, the output end of the second nor gate H2 is electrically connected to the first input end of the first nand gate Y1, the second input end of the first nand gate Y1 is electrically connected to the first logic unit 31 and configured to receive the first logic signal L1, the output end of the first nand gate Y1 is electrically connected to the input end of the fourth inverter F4, the output end of the fourth inverter F4 is electrically connected to the first logic unit 31 and the first driving module 10, and the output end of the fourth inverter F4 is configured to output the second logic signal L2.

As can be seen from fig. 3, the second input terminal of the first nand gate Y1 is electrically connected to the output terminal of the second inverter F2 in the first logic unit 31. An output end of the fourth inverter F4 is electrically connected to a second input end of the first nor gate H1 in the first logic unit 31, a gate electrode of the seventh switch tube M7 in the first driving module 10, and a gate electrode of the fourth switch tube M4, respectively.

Specifically, when the control signal PWM changes from high level to low level, the sixth logic signal L6 is at low level and changes to high level after being inverted by the third inverter F3, one input of the second nor gate H2 is at high level, the second nor gate H2 outputs low level, one input of the first nand gate Y1 is at low level, the first nand gate Y1 outputs high level, and the fourth inverter F4 inverts to make the second logic signal L2 at low level.

When the first voltage signal VX becomes a normal value, the sixth logic signal L6 becomes a high level, becomes a low level after inversion by the third inverter F3, one input of the second nor gate H2 is a low level, the second nor gate H2 outputs a high level, one input of the first nand gate Y1 is a high level, the first nand gate Y1 outputs a low level, and the second logic signal L2 becomes a high level after inversion by the fourth inverter F4.

When the control signal PWM changes from low level to high level, one input of the second nor gate H2 is high level, the output of the second nor gate H2 is low level, one input of the first nand gate Y1 is low level, the output of the first nand gate Y1 is high level, and the second logic signal L2 changes to low level after being inverted by the fourth inverter F4.

As shown in fig. 3, the third logic unit 33 includes a fifth inverter F5 and a third nor gate H3. An input end of the fifth inverter F5 is electrically connected to the boost converting module 40 and configured to receive the first voltage signal VX, an output end of the fifth inverter F5 is electrically connected to a first input end of the third nor gate H3, a second input end of the third nor gate H3 is configured to receive the control signal PWM, and an output end of the third nor gate H3 is electrically connected to the first driving module 10 and configured to output the third logic signal L3.

As can be seen from fig. 3, the input terminal of the fifth inverter F5 is electrically connected to the switching node of the boost conversion module 40. The output end of the third nor gate H3 is electrically connected to the gate of the sixth switching tube M6 in the first driving module 10.

Specifically, when the control signal PWM changes from high level to low level, after the first voltage signal VX rises to the inversion threshold of the fifth inverter F5, both inputs of the third nor gate H3 are at low level, so that the third logic signal L3 output by the third nor gate H3 changes to high level.

When the control signal PWM changes from low level to high level, one input of the third nor gate H3 is high level, so that the third logic signal L3 output by the third nor gate H3 changes to low level.

As shown in fig. 3, the fourth logic unit 34 includes a sixth inverter F6, a second nand gate Y2, a fourth nor gate H4, and a seventh inverter F7. An input end of the sixth inverter F6 is electrically connected to the first logic unit 31 and configured to receive the first logic signal L1, an output end of the sixth inverter F6 is electrically connected to a first input end of the second nand gate Y2, a second input end of the second nand gate Y2 is configured to receive the control signal PWM, an output end of the second nand gate Y2 is electrically connected to the first input end of the fourth nor gate H4 and the fifth logic unit 35, respectively, a second input end of the fourth nor gate H4 is electrically connected to the fifth logic unit 35 and configured to receive the fifth logic signal L5, an output end of the fourth nor gate H4 is electrically connected to an input end of the seventh inverter F7, an output end of the seventh inverter F7 is electrically connected to the second driving module 20 and the fifth logic unit 35, respectively, and an output end of the seventh inverter F7 is configured to output the fourth logic signal L4.

As can be seen from fig. 3, the input terminal of the sixth inverter F6 is electrically connected to the output terminal of the second inverter F2 in the first logic unit 31. The output end of the seventh inverter F7 is electrically connected to the gate of the eighth switching tube M8, the gate of the ninth switching tube M9 and the fifth logic unit 35 in the second driving module 20, respectively.

Specifically, when the control signal PWM changes from high level to low level, one input of the second nand gate Y2 is low level, the second nand gate Y2 outputs high level, at this time, the fifth logic signal L5 changes to high level, both inputs of the fourth nor gate H4 are high level, the fourth nor gate H4 outputs low level, and after being inverted by the seventh inverter F7, the fourth logic signal L4 changes to high level.

When the control signal PWM changes from low level to high level, the first logic signal L1 changes to low level, and changes to high level after inversion by the sixth inverter F6, both the two inputs of the second nand gate Y2 are high level, the output of the second nand gate Y2 is low level, one input of the fourth nor gate H4 is low level, the output of the fourth nor gate H4 is high level, and changes to low level after inversion by the seventh inverter F7, so that the fourth logic signal L4 changes to low level.

As shown in fig. 3, the fifth logic unit 35 includes a third nand gate Y3 and an eighth inverter F8. A first input end of the third nand gate Y3 is electrically connected to the fourth logic unit 34 and is configured to receive the fourth logic signal L4, a second input end of the third nand gate Y3 is electrically connected to the fourth logic unit 34, an output end of the third nand gate Y3 is electrically connected to an input end of an eighth inverter F8, an output end of the eighth inverter F8 is electrically connected to the fourth logic unit 34, the second driving module 20, and the delay unit 36, respectively, and an output end of the eighth inverter F8 is configured to output the fifth logic signal L6.

As can be seen from fig. 3, a first input terminal of the third nand gate Y3 is electrically connected to an output terminal of the seventh inverter F7 in the fourth logic unit 34. A second input terminal of the third nand gate Y3 is electrically connected to an output terminal of the second nand gate Y2 in the fourth logic unit 34. An output end of the eighth inverter F8 is electrically connected to a second input end of the fourth nor gate H4 in the fourth logic unit 34, a gate of the eleventh switch M11 in the second driving module 20, and the delay unit 36, respectively. The delay unit 36 is electrically connected to the gate of the twelfth switching tube M12 in the second driving module 20, and the delay unit 36 is configured to delay the fifth logic signal L5 and output the sixth logic signal L6.

Specifically, when the control signal PWM changes from high level to low level, the output of the second nand gate Y2 is high level, and one input of the third nand gate Y3 is high level, the output of the third nand gate Y3 is low level, and after being inverted by the eighth inverter F8, the fifth logic signal L5 changes to high level. The fifth logic signal L5 is delayed by the delay unit 36 to change the sixth logic signal L6 to a high level.

When the control signal PWM changes from low level to high level, the first logic signal L1 changes to low level, the second nand gate Y2 outputs low level, one input of the third nand gate Y3 is low level, the output of the third nand gate Y3 is high level, and after being inverted by the eighth inverter F8, the fifth logic signal L5 changes to low level. The fifth logic signal L5 is delayed by the delay unit 36 to change the sixth logic signal L6 to a low level.

For clarity of the description of the present application, the operation principle of the boost converter circuit is described in detail below with reference to fig. 3 and 4:

when the control signal PWM changes from high level to low level, the control signal PWM makes the first logic signal L1 change from low level to high level immediately after passing through the first inverter F1, the first nor gate H1, and the second inverter F2. When the control signal PWM is at a low level, the output of the second nand gate Y2 is at a high level, so that the fourth logic signal L4 and the fifth logic signal L5 become at a high level, the second driving signal NGATE discharges through the fourth resistor R4 and the eleventh switch tube M11 and starts to fall, when the second driving signal NGATE falls to a point where the current corresponding to the switch tube N0 is smaller than the current on the inductor L, the first voltage signal VX starts to increase upward, and due to the limitation of the fourth resistor R4, the discharge current of the second driving signal NGATE is relatively small, so that the turn-off process of the switch tube N0 is relatively slow, the rising slope of the first voltage signal VX can be controlled relatively small, and the first voltage signal VX is prevented from being rapidly charged high.

When the first voltage signal VX rises to the inversion threshold of the fifth inverter F5, both inputs of the third nor gate H3 are at a low level, the third logic signal L3 output by the third nor gate H3 changes from a low level to a high level, because the sixth logic signal L6 remains at a low level at this time, the output of the third inverter F3 is at a high level, one input of the second nor gate H2 is at a high level, the output of the second nor gate H2 is at a low level, after passing through the first nand gate Y1 and the fourth inverter F4, the second logic signal L2 output by the fourth inverter F4 is at a low level, the path where the fourth switching tube M4, the fifth switching tube M5, the second resistor R2, and the sixth switching tube M6 are located is turned on, the first driving signal PGATE is pulled down to the VMAX-VGS voltage, and the freewheeling tube P0 is in a weak on state under the action of the first driving signal PGATE. At this time, a part of the current on the inductor L flows to the switching tube N0, and a part of the current flows to the output end of the boost conversion module 40 through the freewheeling tube P0, and since the switching tube N0 is in the turn-off process, the current flowing to the switching tube N0 is smaller and smaller, and the current flowing to the freewheeling tube P0 is larger and larger, so that the first voltage signal VX is not too high, and the problem of too high overshoot voltage at the switching node in the boost conversion module 40 caused by the complete turn-off of the freewheeling tube P0 is avoided. In addition, the problem that the efficiency is reduced and even the device is damaged because the charge of the output capacitor Cout flows back to the switching node and the ground due to the fact that the follow current tube P0 is completely conducted in the turn-off process of the switching tube N0 can be avoided.

When the first voltage signal VX becomes a normal value, the fifth logic signal L5 is delayed by the delay unit 36, so that the sixth logic signal L6 becomes a high level, the twelfth switching tube M12 is turned on, so that the second driving signal NGATE quickly becomes a low level, and the switching tube N0 is completely turned off. The input end of the third inverter F3 is configured to receive the sixth logic signal L6, and is turned to a low level after being inverted by the third inverter F3, at this time, both inputs of the second nor gate H2 are low levels, the output of the second nor gate H2 is high levels, both inputs of the first nand gate Y1 are high levels, the output of the first nand gate Y1 is low levels, and after being inverted by the fourth inverter F4, the second logic signal L2 is turned from a low level to a high level, the fourth switching tube M4 and the fifth switching tube M5 are turned off, the seventh switching tube M7 is turned on, the first driving signal pgis turned to a low level quickly, and the ate P0 is turned on completely.

When the control signal PWM changes from low level to high level, one input of the second nor gate H2 is high level, the second nor gate H2 is low level, and after passing through the first nand gate Y1 and the fourth inverter F4, the second logic signal L2 output by the fourth inverter F4 changes to low level, the seventh switch tube M7 is turned off, and the fourth switch tube M4 and the fifth switch tube M5 are turned on. One input end of the third nor gate H3 receives the control signal PWM, and the third logic signal L3 output by the third nor gate H3 becomes a low level, and the sixth switching tube M6 is turned off. When the second logic signal L2 changes to a low level, both the two inputs of the first nor gate H1 are at a low level, the first nor gate H1 outputs a high level, after the phase of the second inverter F2 is reversed, the first logic signal L1 output by the second inverter F2 changes to a low level, the first switching tube M1 is turned on, the second switching tube M2 is turned on, because the first voltage signal VX is at a high potential, the third switching tube M3 is still in an off state, because the fourth switching tube M4 and the fifth switching tube M5 are turned on, the first driving signal PGATE rapidly rises to the VMAX-VGS voltage, the freewheeling tube P0 is in a weak on state under the action of the first driving signal PGATE, and thereafter, under the action of the first switching tube M1 and the first resistor R1, the first driving signal PGATE continues to slowly rise.

When the first logic signal L1 changes to a low level, the output of the sixth inverter F6 changes to a high level, both inputs of the second nand gate Y2 are at a high level, the output of the second nand gate Y2 changes to a low level, one input of the third nand gate Y3 changes to a low level, the output of the third nand gate Y3 changes to a high level, after inversion by the eighth inverter F8, the fifth logic signal L5 changes to a low level, the sixth logic signal L6 changes to a low level after the fifth logic signal L5 is delayed by the delay unit 36, the eleventh switch M11 is turned off, the twelfth switch M12 is turned off, at this time, one input of the fourth nor gate H4 is at a low level, the output of the fourth nor gate H4 is at a high level, after inversion by the seventh inverter F7, the fourth logic signal L4 changes to a low level, the eighth switch M8 is turned on, the ninth switch M9 is turned on, because the first voltage VX is at a high level, the tenth switch M10, the second switch L4 changes to a low level through the second switch 3, the second switch R3, the eighth switch M8 is turned on, and the second switch R0 is turned on, the second switch R0, and the second switch R3 is turned on, the second switch R8 is turned on, and the first switch R0, the second switch R0 is turned on. Before the switching tube N0 is not fully turned on, the freewheeling tube P0 is always in a weak on state, so that the problem of excessive overshoot voltage at the switching node in the boost conversion module 40 caused by complete turn-off of the freewheeling tube P0 is avoided. In addition, the problem that the efficiency is reduced and even the device is damaged because the charge of the output capacitor Cout flows back to the switching node and the ground due to the fact that the follow current tube P0 is completely conducted in the conducting process of the switching tube N0 can be avoided.

The embodiment of the application also provides a boost converter which comprises the boost conversion circuit.

The boost converter provided by the embodiment of the application can solve the problems that the overshoot voltage of the switching node in the synchronous rectification boost converter is too large during the dead zone of switching, so that the device is in a breakdown risk, and the system reliability is reduced. For a specific working principle, reference is made to the description of the working principle of the boost converter circuit, and details are not repeated here.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.

The above-mentioned embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A boost conversion circuit is characterized by comprising a first driving module, a second driving module, a logic module and a boost conversion module, wherein the first driving module is electrically connected with the logic module and the boost conversion module respectively;

the logic module is used for receiving a control signal and a first voltage signal, and outputting a first logic signal, a second logic signal, a third logic signal, a fourth logic signal, a fifth logic signal and a sixth logic signal according to the control signal and the first voltage signal, wherein the first voltage signal is a voltage signal at a switch node in the boost conversion module; the first driving module is used for outputting a first driving signal according to the first voltage signal, the first logic signal, the second logic signal and the third logic signal; the second driving module is configured to output a second driving signal according to the first voltage signal, the fourth logic signal, the fifth logic signal, and the sixth logic signal; the switching tube in the boost conversion module is in a turn-off process and the first voltage signal is in a rising stage under the action of the second driving signal or the switching tube in the boost conversion module is in a conducting process and the first voltage signal is in a falling stage under the action of the second driving signal, and the follow current tube in the boost conversion module is in a weak conducting state under the action of the first driving signal;

the logic module comprises a first logic unit, a second logic unit, a third logic unit, a fourth logic unit, a fifth logic unit and a delay unit; the first logic unit is electrically connected with the second logic unit, the fourth logic unit and the first driving module respectively, the second logic unit is electrically connected with the first driving module and the delay unit respectively, the third logic unit is electrically connected with the first driving module and the boost conversion module respectively, the fourth logic unit is electrically connected with the second driving module and the fifth logic unit respectively, the fifth logic unit is electrically connected with the second driving module and the delay unit respectively, and the delay unit is electrically connected with the second driving module; the first logic unit is used for receiving the control signal and the second logic signal and outputting the first logic signal according to the control signal and the second logic signal; the second logic unit is configured to receive the control signal, the first logic signal, and the sixth logic signal, and output the second logic signal according to the control signal, the first logic signal, and the sixth logic signal; the third logic unit is used for receiving the control signal and the first voltage signal and outputting the third logic signal according to the control signal and the first voltage signal; the fourth logic unit is configured to receive the control signal, the first logic signal, and the fifth logic signal, and output the fourth logic signal according to the control signal, the first logic signal, and the fifth logic signal; the fifth logic unit is configured to receive the fourth logic signal and output the fifth logic signal according to the fourth logic signal; the delay unit is configured to delay the fifth logic signal and output the sixth logic signal.

2. A boost converter circuit according to claim 1, wherein said first driving module comprises a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, a first resistor and a second resistor;

3. The boost converter circuit according to claim 1, wherein the second driving module comprises an eighth switching tube, a ninth switching tube, a tenth switching tube, an eleventh switching tube, a twelfth switching tube, a third resistor and a fourth resistor;

4. The boost converter circuit of claim 1, wherein the first logic cell comprises a first inverter, a first nor gate, and a second inverter;

the input end of the first phase inverter is used for receiving the control signal, the output end of the first phase inverter is electrically connected with the first input end of the first NOR gate, the second input end of the first NOR gate is electrically connected with the second logic unit and used for receiving the second logic signal, the output end of the first NOR gate is electrically connected with the input end of the second phase inverter, the output end of the second phase inverter is respectively electrically connected with the first driving module, the second logic unit and the fourth logic unit, and the output end of the second phase inverter is used for outputting the first logic signal.

5. A boost converter circuit according to claim 1, wherein said second logic cell comprises a third inverter, a second nor gate, a first nand gate and a fourth inverter;

the input end of the third inverter is electrically connected to the delay unit and configured to receive the sixth logic signal, the output end of the third inverter is electrically connected to the first input end of the second nor gate, the second input end of the second nor gate is configured to receive the control signal, the output end of the second nor gate is electrically connected to the first input end of the first nand gate, the second input end of the first nand gate is electrically connected to the first logic unit and configured to receive the first logic signal, the output end of the first nand gate is electrically connected to the input end of the fourth inverter, the output end of the fourth inverter is electrically connected to the first logic unit and the first driving module, and the output end of the fourth inverter is configured to output the second logic signal.

6. The boost converter circuit of claim 1, wherein the third logic unit comprises a fifth inverter and a third nor gate;

7. The boost converter circuit of claim 1, wherein the fourth logic cell comprises a sixth inverter, a second nand gate, a fourth nor gate, and a seventh inverter;

the input end of the sixth inverter is electrically connected to the first logic unit and configured to receive the first logic signal, the output end of the sixth inverter is electrically connected to the first input end of the second nand gate, the second input end of the second nand gate is configured to receive the control signal, the output ends of the second nand gate are electrically connected to the first input end of the fourth nor gate and the fifth logic unit, respectively, the second input end of the fourth nor gate is electrically connected to the fifth logic unit and configured to receive the fifth logic signal, the output end of the fourth nor gate is electrically connected to the input end of the seventh inverter, the output end of the seventh inverter is electrically connected to the second driving module and the fifth logic unit, respectively, and the output end of the seventh inverter is configured to output the fourth logic signal.

8. The boost converter circuit of claim 1, wherein said fifth logic cell comprises a third nand gate and an eighth inverter;

9. A boost converter comprising the boost converter circuit according to any one of claims 1 to 8.