CN100533742C - Non-volatile semiconductor memory device with alternative metal gate material - Google Patents

Non-volatile semiconductor memory device with alternative metal gate material Download PDF

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CN100533742C
CN100533742C CNB2005101199530A CN200510119953A CN100533742C CN 100533742 C CN100533742 C CN 100533742C CN B2005101199530 A CNB2005101199530 A CN B2005101199530A CN 200510119953 A CN200510119953 A CN 200510119953A CN 100533742 C CN100533742 C CN 100533742C
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dielectric
gate
work function
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CN1790718A (en
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田尚勋
韩桢希
金桢雨
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]

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Abstract

A non-volatile semiconductor memory device comprises a substrate including a source region, a drain region and a channel region provided between the source region and the drain region with a gate stack located above the channel region with a metal gate located above the gate stack. The metal gate is comprised of a metal having a specific metal work function relative to a composition of a layer of the gate stack that causes electrons to travel through the entire thickness of the blocking layer via direct tunneling. The gate stack preferably comprises a multiple layer stack selected from a group of multiple layer stacks consisting of: ONO, ONH, OHH, OHO, HHH, or HNH, where O is an oxide material, N is SiN, and H is a high kappa material.

Description

Non-volatile memory semiconductor device with alternative metal gate material
Invention field
The present invention relates to comprise the non-volatile memory semiconductor device of electric charge capture flash memory and floating boom flash memory, also relate to the method for making non-volatile memory semiconductor device.
Background technology
Nonvolatile semiconductor memory member is the memory electronic device that still can keep its content after external power source removes.Semiconductor nonvolatile memory device generally includes an electric charge capture layer that is used for trap-charge between transistorized grid and channel region.Captive electric charge produces threshold voltage difference in channel region.Threshold voltage V ThAccording to nonvolatile semiconductor memory member is to be in (program) state that writes that electric charge is injected into electric charge capture layer, still is in to make electronics leave the erase status of electric charge capture layer and change.This has changed grid voltage V again ThLevel so that electric current by the raceway groove conducting.Just as seen, the work of non-volatile memory semiconductor device is by capturing in the electric charge capture layer or charge stored makes threshold voltage V ThThe principle that changes realizes.
A kind of in the nonvolatile memory is flash memory.Flash memory further can be divided into floating gate type flash memory and charge trap-type flash memory.In floating boom (floating gate) memory, the floating boom that has used metal level or metalloid layer is as charge storage layer.In trapped-charge memory, for example in semiconductor-oxide-nitride thing-oxide-semiconductor (SONOS) memory, use the electric charge capture dielectric layer.
In essence, memory SONOS unit is traditional nmos pass transistor, but has gate dielectric thermal oxide layer, a silicon nitride layer and second oxide layer of a thickness between 5 to 10nm that about 5nm is thick that about 2nm is thick.Under the forward grid bias, electronics can arrive nitride layer (typical electric charge capture layer) by ultra-thin oxide layer (typical tunnel layer) tunnelling from substrate and also be captured subsequently.For example, silicon nitride has the build-in attribute of trapped electron.Because the negative electrical charge of capturing, transistorized threshold voltage can raise.Similarly, also can threshold voltage be reduced, thereby from nitration case, discharge electronics by on grid, applying negative voltage.So SONOS type memory cell is a kind of electric charge capture flash memory, wherein the data mode in the memory cell can by be stored in electric charge capture layer in the relevant operating characteristic of total amount of electric charge determine.
A shortcoming of the memory device of these types is to be produced by the characteristic of relatively poor relatively efficiency of erasing, and this makes them can not satisfy threshold voltage V approximately-3 volt Th(V) the following erasing time is 10 -3The requirement of the back compatible of second.Known electric charge capture flash memory is because the reverse tunnel of electronics by the barrier layer former thereby have this problem.In known SONOS device, the reverse tunnel effect of electronics causes erase threshold voltage V ThCan not fall after rise fully or fast enough.For example, the erase threshold voltage V in the known device ThState usually should be desired about 10 -3Drop to approximately-3 volts from about 1 volt in the erasing time of second.Erase threshold voltage V ThState may continue to descend or even can raise, particularly when grid bias is approximately-17 volts to-15 volts.Note, in our device, threshold voltage V ThEqual flat rubber belting (flat band) voltage V FBAdd 0.5 volt.
Along with reducing significantly of the design rule of nonvolatile semiconductor memory member, particularly for the unit of smaller szie, improve efficiency of erasing and become even more important.In order to improve efficiency of erasing, the inventor studies the improvement of the reverse tunnel characteristic of impelling the electronics that efficiency of erasing worsens.
In erase operation, owing to voltage is applied on the grid, so the electronics reverse tunnel between grid and electric charge capture layer is to move to electric charge capture layer from grid.This reverse tunnel means that electronics is provided to electric charge capture layer from the control grid, thus the decline that reduces or slowed down electron amount, and the result has prolonged erase operation and has also reduced efficiency of erasing on the other hand.
Fig. 1 has schematically provided a non-volatile ONO among the US609282 and has piled up flash memory.It comprises a silicon substrate 10 with source region 10a and drain region 10b and the channel region 10c between them.More than channel region 10c silicon dioxide SiO 2Dielectric layer 11 (" O "), electric charge capture layer 12 (" N ") and another SiO of silicon nitride SiN 2Dielectric layer (" O ") is for example as barrier layer 13.In this example, control grid 14 or work function are the N of 4.1eV +Polysilicon, or work function is the P of 5.1eV +Polysilicon.Using polysilicon rather than metal as the control grid, is because silicon dioxide has the tendency that forms silicide when being exposed to metal.That is to say that metal can cause instability with combining of silicon.
Fig. 2 has shown severally disclosedly can realize the irrelevant stacked structure of grid material that better writes with having relative thicker high k dielectric layer and it is said.
Fig. 3 has shown that the mixing of preceding two figure is polysilicon-HfO 2(high κ material) piles up.As people such as E.Cartier at " Systemic Study of pFET Vt with Hf-Based Gate Stacks with Poly-Si andFUSI Gates; " VLSI 2004-VLSI Technology/Circuits Symposium, IEEE, June, that is reported in 2004 is such, and the problem that this structure exists is at HfO 2The apparent effect of middle fermi level pinning.
As shown in Figure 4, the thick SiO of 4.5nm 2The position of Fermi level can change according to annealing temperature, but the HfO of 4nm 2The HfO of 4nm that perhaps has the SiON of 1nm 2High κ material then can be not like this.As 4nm thick-layer HfO 2Annealing temperature when about 600 degrees centigrade are elevated to about 1000 degrees centigrade, P +Originally the position of the Fermi level of polysilicon is elevated to and is approximately 0.4 or 0.5 from being approximately 0.3, rolls back then and is approximately 0.3.Under same annealing temperature, the thick SiO of 4.5nm 2The position of the Fermi level of layer drops to and is approximately-0.6 (P from being approximately 0 (intrinsic level) +The initial value of polysilicon gate).
Therefore, because the existence of reverse tunnel effect, no matter the annealing temperature that is used for material is how, high κ material and P +The grid that polysilicon constitutes is not compatible mutually.The reverse tunnel effect has caused relatively poor relatively efficiency of erasing.So the fermi level pinning this structure that made a difference has hindered its effectiveness in electric charge capture dielectric nonvolatile memory at least.So, still exist the necessity that reduces in floating gate type and the charge trap-type non-volatile memory by the reverse tunnel that stops dielectric layer.
Summary of the invention
The invention provides a kind of method of making nonvolatile semiconductor memory member, have and effectively to provide a big relatively barrier height to suppress electronics effectively by stopping the work function of dielectric layer generation reverse tunnel thereby wherein control metal gates.
Description of drawings
In conjunction with the accompanying drawings and by following description to one exemplary embodiment, above-mentioned and other characteristics of the present invention and advantage will become more obvious, and while the present invention is not limited to these embodiment.
Fig. 1 has shown the structure of a traditional nonvolatile memory.
Fig. 2 has shown the variation of the gate stack of non-volatile memory architecture shown in Figure 1.
Fig. 3 has shown polysilicon/HfO 2Stacked structure.
Fig. 4 has shown the problem that causes traditional structure shown in Figure 3 to be effective.
Fig. 5 has shown a typical floating boom stacked non-volatile memory spare.
Fig. 6 has shown a typical electric charge capture flash storage non-volatile memories part.
Fig. 7 a and 7b illustrate the influence of the present invention for barrier height.
Fig. 8 has shown the band gap of different oxides and the relation between the dielectric constant.
What Fig. 9 had shown different oxides can be with arrangement.
Figure 10 has shown the band gap of oxide and the relation between the dielectric constant.
Figure 11 has shown the relation between metallicl work function and the dielectric constant.
Figure 12 has shown write diagnostics.
Figure 13 a, 13b and 13c have shown the erasing characteristic under-10 volts of bias voltages ,-12 volts of bias voltages and-14 volts of bias voltages respectively.
Figure 14 has shown the voltage threshold of the O/SiN/H/M charge trapping non-volatile memories spare of an one exemplary embodiment and the relation between the erasing time according to the present invention.
Embodiment
Now will describe the present invention more all sidedly in conjunction with the accompanying drawings, wherein provide one exemplary embodiment of the present invention.Yet the present invention can realize with a lot of different forms, and should not be understood that to be confined to these given embodiment here; Or rather, these embodiment that provided are in order to make the disclosure more thorough and complete, and all sidedly notion of the present invention are conveyed to those skilled in the art.
Fig. 5 has shown a floating boom stacked nonvolatile memory 50, and it comprises a substrate 51 that for example is made of silicon.Substrate 51 also can use other material, but silicon is the most general at present.In substrate 51, form source electrode 51a and drain electrode 51b, between them, form channel region 51c.Should be noted that in this example, wide in range explanation should be done in term " substrate ", comprise wafer or other rigidity or flexible substrate format, also comprise that deposition or growth have the example of different extra plays simultaneously.Can form substrate 51 and source electrode, drain electrode and channel region 51a-51c by any suitable mode.
On channel region, form gate stack 56.From substrate 50, gate stack 56 comprises tunnel layer 52, electric charge capture layer 53, barrier layer 54 and control grid 55 according to the order of leaving substrate 50.Pile up in 56 at floating boom shown in Figure 5, electric charge capture layer 53 is the floating booms that are made of electric conducting material such as metal or metalloid material.Tunnel layer 52 is dielectric layers, and barrier layer 54 also is a dielectric layer.Electronics stops that by electric charge dielectric layer 54 controls to the frequency of floating boom 53 tunnellings from control grid 55.If use hafnium as the tunnel dielectric layer, floating boom should be metal or the metalloid material with high work function.
Electric charge stops that dielectric layer 54 preferably is made of the material with high-k κ, for example insulator.Consider the dielectric material on metal, barrier layer 54 of control grid 55 and being with of junction structure place that constitutes the floating boom of electric charge capture layer 53, be appreciated that the effect of work function aspect the barrier height that increases the barrier layer that improves metal gate layer 55, as being laid down a definition below in conjunction with Fig. 7 a and 7b.
Fig. 6 have one with Fig. 5 in the similar structure of memory 50, just represent the flash non-volatile memories part 60 of a charge trap-type.The embodiment of similar Fig. 5, for instance, substrate 61 can be made of silicon or other backing material that is fit to.In the substrate 61, between source electrode 61a and drain electrode 61b, form channel region 61c.On channel region 61c, form gate stack 66.Gate stack 66 orders comprise electric charge capture layer 63, barrier layer 64 and the control grid 65 of tunnel layer 62, dielectric form.
Tunnel layer 52,62 preferably is made of the dielectric resemble the thermal oxide, more preferably is to be selected from by SiO 2, Al 2O 3, MgO, SrO, SiN, BaO, TiO, Si 3N 4, Ta 2O 5, BaTiO 3, BaZrO, ZrO 2, HfO 2, Y 2O 3, ZrSiO, HfSiO and LaAlO 3A kind of dielectric in the group that constitutes.Fig. 8 has provided the dielectric constant of the part in these materials, and what Fig. 9 had provided other part in these materials can be with arrangement.Typical thickness is in the scope of several nanometers, and for example 1-3nm is preferably 2nm.
The material that is used for electric charge capture layer 53,63 is different at Fig. 5 with the embodiment shown in 6.In Fig. 5, electric charge capture layer is a floating boom, preferably by being selected from the group that constitutes by polysilicon, such as the high work function metal of platinum (Pt), gold (Au), titanium-aluminium alloy (TiAlN), palladium (Pd), or a kind of material of selecting in the metal composite group that is made of metal nitride, metal boron nitride, metal silicon nitride, metal aluminum nitride and metal silicide constitutes.Preferably use metal as floating gate electrode, particularly for using high κ material as tunnel dielectric layer with high work function.
In Fig. 6, electric charge capture layer 63 is to capture dielectric layer, preferably constitutes by being selected from by the GeO of the GeN of the GeON of the SiOx of the SiON of the SiN of SiN, rich Si, rich Si, rich Si, rich Ge, rich Ge, rich Ge, the GeO that mixes Si, the GeON that mixes Si, the GeN that mixes Si, a kind of material that mixes in the group that the SiN of Ge constitutes.
1.[mix M 1M 2N mixes M 1M 2ON mixes M 1M 2Ox.In this case, M 1And M 2Different.M 1And M 2Be metal, Si or Ge].
2.[the MNx of rich M, the MON of rich M, the MOx of rich M.In this case, M is metal, Si or Ge]
Barrier layer 54,64 also is a dielectric.Barrier layer 54,64 is preferably a kind of thermal oxide, more preferably is to be selected from by SiO 2, Al 2O 3, MgO, SrO, SiN, BaO, TiO, Si 3N 4, Ta 2O 5, BaTiO 3, BaZrO, ZrO 2, HfO 2, Y 2O 3, ZrSiO, HfSiO and LaAlO 3The group that constitutes.
Control grid the 55, the 65th, a kind of electric conducting material is preferably a kind of metal, and has the specific work function greater than 4.9eV.
The explanation of being done as Fig. 7 a and 7b, the absolute value of the work function by improving the control grid, for instance, the Fermi level (E of metal gate layers 55,65 F) and stop the conduction level (E of dielectric layer 54,64 C) between difference can relatively increase, therefore, may reduce the probability of electron tunneling electric charge barrier layer 54,64.Shown in Fig. 7 a and 7b, the energy band diagram of Fig. 7 a has shown traditional N +-polysilicon gate construction.Electronics from the control grid can pass through Fowler-Nordheim (FN) tunneling effect tunnel barriers oxide arrival charge storage dielectric layer.By contrast, shown in Fig. 7 b, have relatively large electronic work function, cause bigger barrier height according to the optionally energy band diagram of (alternative) grid material of the present disclosure.Electronics from grid must be by the whole width of Fowler-Nordheim tunneling effect tunnel barriers 54,64.For instance, the Fowler-Nordheim tunnelling is defined as, the electric current of the MOS structure in the oxide of for example flowing through under high electric field.The probability of Fowler-Nordheim tunnelling is relevant with the width of electron institute tunnelling.In most of the cases, think that this is the thickness of oxide, for example, as shown in Figure 2.Yet disclosed here present embodiment is set the Fowler-Nordheim tunnelling by the metal that optionally uses high κ material and high work function.
Therefore, control the absolute value of the work function of grid by improving metal, for instance, the Fermi level (E of metal gate layers 55,65 F) and stop that the difference between the dielectric layer 54,64 can relatively increase.The work function Φ of metal increases, then the Fermi level E of metal fDescend, the barrier height of knot raises, thereby has reduced the probability of electron tunneling electric charge barrier layer 54,64.So,, might reduce the probability of electron tunneling electric charge barrier layer by the dielectric layer of selecting barrier layer 54,64 and the metal of controlling grid 55,65.In disclosed embodiment of this invention, the reverse tunnel of electronics can be inhibited.
Should be noted that work function be normally defined in the solid valence electron that weak beam ties up must have, can make its absolute zero (0K) down kinetic energy be the minimum potential energy that is discharged into external vacuum under zero the situation.Can be used as control grid possible metal in list following these, be their work function in the bracket, Hf[3.9], Zr[4.05], Ta[4.25], Al[4.28], Nb[4.3], Ti[4.33], W[4.55], Mo[4.6], Ru[4.71], Au[5.1], Ni[5.15], Ir[5.27] and Pt[5.65].In the middle of them, high work function metal is preferably as the traditional material of the semiconductor device that is used for these types.Should be noted that also high κ dielectric is generally understood as κ more than or equal to 4.0 (SiO 2), be preferably more than the κ value (4.1) of polysilicon.
Fig. 8 has shown the dielectric constant of different oxides and the relation between the band gap, comprises SiO 2, Al 2O 3, MgO, HfO 2, SrO, SiN, Ta 2O 5, BaO and TiO 2Wherein, the intrinsic property of electric charge capture is desirable for the electric charge capture flash memory device shown in memory device among Fig. 6 60 among the SiN.
What Fig. 9 had shown different oxides can be with arrangement (eV), wherein the conduction band offset of oxide be expressed as on the occasion of, the valence band offset of oxide is expressed as negative value, certainly, they are different materials.
Figure 10 and Figure 11 have shown principal character of the present disclosure.Figure 10 has shown the band gap of oxide of different materials and the relation of dielectric constant.Obviously, the band gap of oxide increases along with dielectric constant and descends.The conduction band offset of oxide is proportional to the band gap of oxide.Can not be expressed as equation when not considering the reverse tunnel effect of electronics:
Metallicl work function=7.8-0.85* barrier height
Metallicl work function=6.85-0.25* band gap
So improving barrier height has direct relation by the selection of metallicl work function with band gap.As shown in figure 11, the relation that has shown the metallicl work function and the dielectric constant of different barrier oxide.Here, SiO shown in 2And Al 2O 3Form the Trendline of a metallicl work function, promptly the barrier height of barrier oxide reduces along with the increase of metallicl work function.For better write/erase characteristic, our preferred high K barrier dielectric.For high K barrier dielectric, preferably use metal gates with higher work function.
Figure 12 has shown the write diagnostics of an one exemplary embodiment, and it has provided grid/SiO 2The barrier height on barrier layer.N +Polysilicon 3.1eV (polysilicon/SiO 2) barrier height (the barrier height value of being given among the figure adds that 1eV represents the metallicl work function of 4.1eV) represent by the metallicl work function that equals 4.1eV.Simultaneously also shown the barrier height of 3.6eV or the metallicl work function of 4.6eV, and the metallicl work function of the barrier height of 4.1eV or 5.1eV.As shown in figure 12, variation V under the varying level of 14 volts that apply, 12 volts and 10 volts ThChange.Similarly, Figure 13 a, b and c have shown the erasing characteristic of-10 volts of bias voltages ,-12 volts of bias voltages and-14 volts of bias voltages under the same barrier height respectively.As can be seen, for 10 -3Second erasing time, embodiments of the invention are expected to realize the target of negative 3 volts threshold voltages of expecting by simulation program, particularly negative 12 with bear under 14 volts of bias voltages.
Figure 14 has shown the threshold value V of an exemplary O/N/H/M stacked structure Th(V) with the relation in erasing time.Vertical chain nodel line is represented the erasing time that industry is desired and require.The dotted line of level is represented the desired threshold voltage that is used for erasable nonvolatile memory.As shown in figure 14, according to computer simulation, each embodiment of the present invention can realize the result of these expectations.
Especially, when the barrier layer mainly be by SiO 2During formation, the special metal work function of metal should be equal to or greater than 4.4eV.When the barrier layer was different high κ dielectric, when promptly having the dielectric greater than dielectric Changshu value of 4.1eV, the special metal work function of control grid should be more than or equal to 4.9eV and be less than or equal in the scope of 5.5eV.It should be noted that these values will add or deduct 0.2eV as a rule, some fermi level pinnings that may cause because barrier layer 54,64 and metal are controlled the impurity that exists at the interface of grid 55,65 with reflection.
For another floating boom embodiment, when tunnel layer was high-k dielectrics, floating boom 53 was by having more than or equal to 4.9eV and being less than or equal to the metal gates that the metal of the special metal work function in the scope of 5.5eV constitutes.Like this, can wipe and write step by the barrier height control that improves the electron tunneling tunnel layer better.In fact, because high barrier height and good retention performance, when we adopt high κ tunnel layer and P +Polysilicon is during as floating boom because as the fermi level pinning effect of in Fig. 4, being discussed, expectation obtains the barrier height of lower electronics by tunnel oxide P+ polysilicon (poly-Si) grid.For the advantage of the good write/erase characteristic of the good retention performance that utilizes high work function floating boom and high κ tunnel layer, preferably use the metal floating boom of high work function.
By the above sufficiently clear ground is shown that in the industry cycle the dielectric introducing of high κ comparatively recently is a gate-dielectric, so far, mainly use of the application of O/N/O device as SONOS type flash memory.By using P +Polysilicon gate and relative thicker barrier layer oxide can alleviate the problem of wiping.Yet because design rule reduces, scaled further is inevitably, thereby has improved the demand to high κ dielectric material.Problem be no matter annealing temperature what kind of is, high κ dielectric since above-mentioned Fermi's pinning effect and can not with P +The polysilicon compatibility.Embodiments of the invention have been avoided these problems by using metal gates.In order to improve efficiency of erasing and to prevent the electronics reverse tunnel, used the metal gates of high work function.
For the O/N/O device, estimate that the metal gates with 4.6eV metallicl work function will satisfy the requirement of Asia 52 or 57nm flash memory, and can not show any tangible electron back under the bias condition to tunneling effect in given wiping.Metal gates or O/N/H (wherein H represents high κ dielectric) with 5.1eV metallicl work function will satisfy the requirement of Asia 52 or 57nm flash memory, and can not show any tangible electron back under the bias condition to tunneling effect in given wiping.So embodiments of the invention can greatly reduce known SONOS device etc. is had the electron back that has a strong impact on to tunneling effect.
According to the simulation of the embodiment of the invention, the writing speed that non-volatile memory semiconductor device should have is at 17V (respective threshold variation (V Th) from-3V to 1V) time be 20 microseconds.Erasing speed is at 18V (respective threshold variation (V Th) from 1V to-should be 2 milliseconds 3V) time.Electric current is preferably more than 500nA in the unit.Persistence (variation of threshold voltage shift) 100000 times the circulation in (for write state) less than 0.3V.Greater than 350nA, and the retentivity (retention) (variation of threshold voltage shift) under 250 degrees centigrade of 2 hours conditions will be less than 0.3V 100000 circulation planted agents for the cycling element electric current.At last, read upset (variation of threshold voltage shift) and reading circulation and will be in 10000 write/erases circulations for 100000 times less than 1V.
The present invention is described by one exemplary embodiment, but is not limited to these embodiment.Without departing from the present invention, those skilled in the art can make different variations and modification.For example, compared with prior art, embodiments of the invention can be realized bigger bi-directional scaling, keep simultaneously or improve efficiency of erasing, no matter and high work function metal gates O/N/H, O/H/H, O/H/O or H/H/H sequence that to be the O/N/O in capturing dielectric layer embodiment, high κ pile up, still O/FG/H, O/FG/O or the H/FG/H sequence in floating boom (FG) embodiment.
The application is pursuant to the korean patent application that was submitted to Korea S Department of Intellectual Property on October 8th, 2004 and requires priority 10-2004-0080354 number, and its disclosed full content is quoted as a reference at this.

Claims (12)

1. non-volatile memory semiconductor device comprises:
Source region, drain region and the channel region that provides between described source region and described drain region are provided for substrate, described substrate; And
Be positioned at the gate stack of described channel region top, described gate stack comprises tunnel layer, electric charge capture layer, barrier layer and the control grid of sequence stack, and wherein said tunnel layer is adjacent with described channel region, and
Wherein said control grid is when the barrier layer is the high κ dielectric that has greater than 4.1 dielectric radio, is equal to or greater than the metal gates that 4.9eV constitutes to the metal that is equal to or less than the special metal work function in the 5.5eV scope by having.
2. non-volatile memory semiconductor device as claimed in claim 1, wherein said memory device are that a kind of floating-gate memory spare and described electric charge capture layer are floating boom.
3. non-volatile memory semiconductor device as claimed in claim 1, wherein said memory device are that a kind of electric charge capture flash memory and described electric charge capture layer are the electric charge capture dielectric.
4. non-volatile memory semiconductor device as claimed in claim 1, wherein said gate stack comprises a kind of multiple-level stack that is selected from the multiple-level stack group that is made of O/N/O/M, O/N/H/M, O/H/H/M, O/H/O/M, H/H/H/M or H/N/H/M, and wherein O is that oxide material, N are that SiN, H are that hafnium, the M that has greater than 4.1 dielectric radio is the metal with described specific work function.
5. non-volatile memory semiconductor device as claimed in claim 1, wherein said tunnel layer are a kind of being selected from by SiO 2, Al 2O 3, MgO, SrO, SiN, BaO, TiO, Si 3N 4, Ta 2O 5, BaTiO 3, BaZrO, ZrO 2, HfO 2, Y 2O 3, ZrSiO, HfSiO and LaAlO 3Dielectric in the group that constitutes.
6. non-volatile memory semiconductor device as claimed in claim 2, wherein said floating boom comprise the material in a kind of metal composite group that is selected from the group that is made of polysilicon, platinum, gold, titanium-aluminium alloy, palladium or is made of metal nitride, metal boron nitride, metal silicon nitride, metal aluminum nitride and metal silicide.
7. non-volatile memory semiconductor device as claimed in claim 3, wherein said capture dielectric be selected from by the GeO of the GeN of the GeON of the SiOx of the SiON of the SiN of SiN, rich Si, rich Si, rich Si, rich Ge, rich Ge, rich Ge, mix Si GeO, mix Si GeON, mix Si GeN, mix the group that the SiN of Ge constitutes.
8. non-volatile memory semiconductor device as claimed in claim 1, wherein said substrate are the Si substrates.
9. floating gate non-volatile semiconductor storage unit comprises:
Source region, drain region and the channel region that provides between described source region and described drain region are provided for substrate, described substrate; And
Be positioned at the gate stack of described channel region top, described gate stack comprises tunnel layer, floating gate layer, barrier layer and the control grid of sequence stack, and wherein said tunnel layer is adjacent with described channel region, and
Wherein said floating gate layer is to be equal to or greater than metal gates that 4.9eV to the metal that be equal to or less than special metal work function 5.5eV scope in constitute by having when described tunnel layer when being κ greater than 4.1 high-k dielectrics.
10. floating gate non-volatile semiconductor storage unit as claimed in claim 9, wherein said gate stack comprises a kind of multiple-level stack that is selected from the multiple-level stack group that is made of H/N/O/M, H/N/H/M, H/H/H/M or H/H/O/M, and wherein O is that oxide material, N are that SiN, H be κ greater than 4.1 high κ material, M are the metal with described specific work function.
11. floating gate non-volatile semiconductor storage unit as claimed in claim 9, wherein said tunnel layer are a kind of being selected from by Al 2O 3, MgO, SrO, SiN, BaO, TiO, Si 3N 4, Ta 2O 5, BaTiO 3, BaZrO, ZrO 2, HfO 2, Y 2O 3, ZrSiO, HfSiO and LaAlO 3Dielectric in the group that constitutes.
12. floating gate non-volatile semiconductor storage unit as claimed in claim 9, wherein said substrate are the Si substrates.
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