CN100524710C - Focal plane device with lowered indium pin pad stress - Google Patents
Focal plane device with lowered indium pin pad stress Download PDFInfo
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- CN100524710C CN100524710C CNB2004100847936A CN200410084793A CN100524710C CN 100524710 C CN100524710 C CN 100524710C CN B2004100847936 A CNB2004100847936 A CN B2004100847936A CN 200410084793 A CN200410084793 A CN 200410084793A CN 100524710 C CN100524710 C CN 100524710C
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Abstract
The focal plane device with lowered indium pin pad stress includes array detector photosensitive element chip, and silicon signal read-out circuit connected via indium pins with the array detector photosensitive element chip. The present invention features that beside the indium pin area for electric interconnection, one or two indium pins with great bottom area and lowered stress are added, or around the indium pin area for electric interconnection of area array, one or two rows of indium pins with great bottom area and lowered stress are added. The selection and positioning of the indium pins with great bottom area and lowered stress is programmed with ANSYS finite element analysis software and run in WIN2000 platform of PC. The said structure has indium pin pad stress 70 % lowered.
Description
Technical field
The invention belongs to photoelectron integrated technology field, be specifically related to a kind of infrared focal plane device that can reduce the indium post solder joint stress of detector array chip and the interconnection of silicon reading circuit.
Background technology
Infrared focus plane (FPA) technology is in military affairs, and environment is civilian, and various fields such as industry and medical science have a wide range of applications, especially to the constantly growth of very large-scale FPA demand.Yet, extensive infrared FPA is by photosensitive element chip and silicon read output signal integrated circuits such as large-scale HgCdTe, quantum well, form a complete focal plane device by each self-growing indium post back-off bonding, its bonding quality directly influences the final Performance And Reliability of device.People are in order to reduce the stress that indium post solder joint bears, improve package reliability, developed substrate thinning, probe substrate removal, increase means such as indium post height, filling epoxy resin macromolecular material, but said method has all increased the complexity of technology inevitably, and in unusual large-scale F PA, indium post solder joint has extremely little inclination size, even still there is suitable stress in extremely little inclination size, such stress can cause the photosensitive first inefficacy probability in focal plane to increase.
Summary of the invention
Based on the problem that above-mentioned prior art exists, the objective of the invention is to propose a kind of infrared focal plane device that reduces the indium post solder joint stress of detector array chip and the interconnection of silicon reading circuit.This device only need just can prepare with the technology of routine.
Infrared focal plane device of the present invention comprises: detector array photosensitive element chip 1, by indium post 2 silicon read output signal integrated circuit 3, it is characterized in that with the interconnection of detector array photosensitive element chip: be used for electricity interlinkage indium post 2 regional edge add 1～2 floor space than interconnect indium column 2 big stress indium post 4 falls; Or add around peripheral in face battle array electricity interlinkage indium post 2 zone 1～2 row's floor space than interconnect indium column 2 big stress indium post 4 falls.This structure can make interconnect indium column 2 solder joint stress descend about 70%, can alleviate the reliability reduction that interconnect package indium post solder joint stress causes substantially.Fig. 1 adds the generalized section of falling stress indium post that floor space is bigger than interconnect indium column in the outside at alignment electricity interlinkage indium post two ends.Fig. 2 adds row's floor space schematic top plan view of falling stress indium post bigger than interconnect indium column around face battle array electricity interlinkage indium post.
Said selection and the accurate location that falls stress indium column dimension is by the programming of ANSYS finite element analysis software, moves on PC WIN2000 platform, judges according to the result who exports.Its process is as follows:
1.ANSYS finite element analysis software pre-treatment
A. the selected direct coupled field analysis of PLANE13 cell type;
B. with analyzed sample: the Young's modulus of probe substrate material, reading circuit Si material and In column material and thermal coefficient of expansion input, because the detecting material segment thickness of epitaxial growth on the probe substrate material is less than 6 microns, ignore the influence of its counter stress here, therefore do not consider;
C. set up geometrical model, be about to substrate, Si reading circuit and the input of In post physical dimension.
2.ANSYS finite element analysis software is found the solution:
A. set steady-state analysis, after promptly sample temperature is determined, do not change in time;
B. be provided with simulated object and vary with temperature after, the deformation that causes only occurs in In post and small size by on the interconnect die, large-size is by the fixed reference of interconnect die as whole simulated environment, i.e. its deformation is ignored, and initial temperature is set and needs to load the temperature that simulated.
C. set and enter non-linear analysis on Large Deformation; The convergence criterion of analysis environments is set; Carrying out computing finds the solution.To the result of calculation demonstration of tabulating, disposal data obtains the position that maximum stress takes place.
D. import the low stress effect indium post physical dimension of adding then, computing and so forth, the curve chart of electricity interlinkage indium post stress decrease obtains low stress effect indium column dimension thus behind the acquisition interpolation low stress effect indium post.
Outstanding advantage of the present invention is:
1. technology is simple
2. can effectively reduce the excessive stresses of interconnection solder joint, improve the device package reliability
Description of drawings
Fig. 1 adds the generalized section of falling stress indium post that floor space is bigger than interconnect indium column in the outside at detector line array electricity interlinkage indium post two ends.
Fig. 2 adds row's floor space schematic top plan view of falling stress indium post bigger than interconnect indium column around detector array electricity interlinkage indium post.
Fig. 3 is finite element analysis electricity interlinkage indium post stress and falls the flow chart that stress indium column dimension is selected.
Fig. 4 is that keep to the side the most equivalent stress of interconnect indium column varies with temperature curve.
Fig. 5 is the curve of interconnect indium column equivalent stress with its bottom surface vary in diameter.
Fig. 6 is 128 yuan of alignment indium posts, and adds two diameters at its ragged edge and be respectively 65,100 μ m when falling stress indium post, and the interconnect indium column equivalent stress is with the curve of its decentre point variable in distance.
Fig. 7 is 256 yuan of alignments, and to add two diameters at its ragged edge be that the interconnect indium column equivalent stress was with the curve of its decentre point variable in distance after stress indium post fell in 100 μ m.
Fig. 8 is the mesa technique schematic diagram.
Fig. 9 makes AuGeNi Ohm contact electrode process schematic representation.
Figure 10 is an indium post preparation technology schematic diagram.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is elaborated:
With indirect interconnection, GaAs-indium post-jewel sheet line array device is an example, at first adopts above-mentioned ANSYS finite element analysis software, calculates the maximum stress particular location of detector electricity interlinkage indium post 2, stress indium post 4 optimum positions and concrete size fall in insertion, and its concrete steps are as follows:
1. the Young's modulus and the thermal coefficient of expansion of analyzed sample are imported, detector (QWIP) backing material is that GaAs, reading circuit are got Si material and In column material, because the epitaxy layer thickness of material for detector is ignored the influence of its counter stress here less than 6 microns, therefore do not consider;
With the physical dimension input (considering interconnection indirectly, is example with GaAs-indium post-jewel sheet) of analyzed sample, probe substrate length is 12300 microns, and wide is 1500 microns, and thick is 500 microns; The indirect interconnection circuit size of jewel sheet is set greater than probe substrate GaAs; The In post shapes is a cydariform, and its physical dimension is three groups, is respectively:
128 indium post one rows, 33 microns of diameters, 12 microns of height, 92 microns of spacings;
64 indium post one rows, 33 microns of indium column diameters, 12 microns of height, 184 microns of spacings;
256 indium post one rows, 33 microns of indium column diameters, 12 microns of height, 46 microns of spacings.
Set steady-state analysis, after promptly sample temperature is determined, do not change in time; The deformation that variations in temperature causes is set only occurs on In post and the GaAs substrate, the deformation of larger-size jewel sheet is made as fixing, promptly ignores deformation, and the analog temperature scope is provided with 25K～300K.The results are shown in Figure 4-8.
Fig. 4 is that the equivalent stress of the interconnect indium column that keeps to the side most of simulation varies with temperature curve, and wherein the ■ line is 128 indium post one rows, 33 microns of diameters, 92 microns of spacings; ● line is 64 indium post one rows, 33 microns of indium column diameters, 184 microns of spacings; ▲ line is 256 indium post one rows, 33 microns of indium column diameters, 46 microns of spacings.The result shows that the interconnect indium column spacing is thin more, and it is big that the equivalent stress of bearing becomes.
Fig. 5 is the curve of interconnect indium column equivalent stress with its bottom surface vary in diameter, show when the indium column diameter is changed to 25 μ m by 15 μ m, its stress almost is plummet, just tends towards stability later on up to 60 μ m, illustrates that the floor space of indium post is very big to its stress influence that bears.
Fig. 6 is the curve of interconnect indium column equivalent stress with its decentre indium post solder joint variable in distance, and wherein the ■ line is 128 indium post one rows, 33 microns of diameters, 92 microns of spacings; As can be seen: indium post weld spacing central point is far away more, and the stress that is born is big more.▲ line is after the outermost end of 9 indium posts that keep to the side is most added the big indium post of bottom surface diameter 65 μ m, makes the stress of original 9 indium posts obviously descend.● line is that stress has had decline by a larger margin after the outermost end of 9 the indium posts that keep to the side is most added the big indium post of diameter 100 μ m.
Fig. 7 is the curve of interconnect indium column equivalent stress with its decentre indium post solder joint variable in distance, and wherein the ■ line is 256 indium post one rows, 33 microns of indium column diameters, and 46 microns of spacings, as can be seen: indium post weld spacing central point is far away more, and the stress that is born is big more.Add the big indium post of bottom surface diameter 100 μ m equally in the outermost end of 9 the indium posts that keep to the side most, write down 9 indium post stress decrease situations, plot ● line.After continuing then to add the big indium post of second bottom surface diameter 100 μ m, record stress decrease situation plots ▲ rules, and observes the 9th the indium post stress decrease amplitude of keeping to the side most, than ● it is more to rule, and stress has descended 70% altogether.
Draw by above-mentioned analysis result, what the present invention proposed adds 1～2 and falls stress indium post being used for electricity interlinkage alignment indium columnar region limit, or around face battle array electricity interlinkage indium columnar region periphery, it is very useful to decline electricity interlinkage indium post solder joint stress that stress indium post falls in interpolation 1～2 row.
According to above-mentioned analysis result, can draw the optimum position and the size of falling stress indium post then, design layout, technology is carried out flow routinely, and its process is as follows:
See Fig. 8-Figure 10, Fig. 8 is the mesa technique schematic diagram.The QWIP chip is successively by substrate 101, lower electrode layer 102, QWIP layer 103.(a) on the QWIP layer, apply photoresist; (b) exposure is developed and is left the table top window; (c) the etching table top is to lower electrode layer 102; (d) remove photoresist, the QWIP table top forms.
Fig. 9 makes AuGeNi Ohm contact electrode process schematic representation.(a) coating photoresist; (b) exposure, development windowing; (c) evaporation AuGeNi; (d) peel off; (e) alloying, on table top, form ohmic contact upper electrode layer 104.
Figure 10 is an indium post preparation technology schematic diagram.(a) coating thick photoresist; (b) photoetching, leave window; (c) evaporated metal indium; (d) peel off, form indium post 2,4.
At last the silicon read output signal integrated circuit of the quantum well of the indium post of having grown or HgCdTe photosensitive element chip, the indium post of having grown, be placed on Karl Suss (FC-150) the inverse bonding machine, aim at respectively with as the indirect jewel sheet circuit that interconnects hybrid package, interconnect indirectly, at room temperature plus-pressure is 6～10 kilograms, held time 10～20 seconds, so far finish the bonding of HgCdTe quantum well photosensitive element chip and silicon read output signal integrated circuit, form a complete focal plane device.
Above-described embodiment is only in order to illustrate technological thought of the present invention and characteristics; its purpose is to make those of ordinary skill in the art can understand content of the present invention and implements according to this; scope of the present invention also not only is confined to above-mentioned specific embodiment; be all equal variation or modifications of doing according to disclosed spirit, still be encompassed in protection scope of the present invention.
Claims (2)
1. focal plane device that reduces indium post solder joint stress comprises: detector array photosensitive element chip (1) by the silicon signal read circuit (3) of indium post (2) with the interconnection of detector array photosensitive element chip, is characterized in that:
Be used for electricity interlinkage indium post (2) regional edge add 1～2 floor space than interconnect indium column (2) big stress indium post (4) falls, or add around peripheral in face battle array electricity interlinkage indium post (2) zone 1～2 row's floor space than interconnect indium column (2) big stress indium post (4) falls.
2. according to a kind of focal plane device that reduces indium post solder joint stress of claim 1, it is characterized in that:
The selection that stress indium column dimension falls in said big floor space reaches and accurately locatees is by the programming of ANSYS finite element analysis software, moves on PC WIN2000 platform, and according to result's judgement of output, its process is as follows:
A. the selected direct coupled field analysis of PLANE13 cell type;
B. with analyzed sample: the Young's modulus of probe substrate material, reading circuit Si material and In column material and thermal coefficient of expansion input, because the thickness of the detecting material of epitaxial growth on the probe substrate material is less than 6 microns, ignore the influence of its counter stress here, therefore do not consider;
C. set up geometrical model, be about to probe substrate, Si reading circuit and the input of In post physical dimension;
D. set steady-state analysis, sample temperature does not change in time;
E. be provided with simulated object and vary with temperature after, the deformation that causes only occurs in In post and undersized by on the interconnect die, large-size by the fixed reference of interconnect die as whole simulated environment, i.e. its deformation is ignored, and initial temperature is set and need loads the temperature that simulated;
F. set non-linear analysis on Large Deformation; The convergence criterion of analysis environments is set; Carrying out computing finds the solution; To the result of calculation demonstration of tabulating, disposal data obtains the position that maximum stress takes place;
G. add then and fall stress indium post physical dimension, computing and so forth, the curve chart of the electricity interlinkage indium post stress decrease behind the stress indium post falls in acquisition interpolation at last, obtains to fall stress indium column dimension thus.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100847936A CN100524710C (en) | 2004-12-01 | 2004-12-01 | Focal plane device with lowered indium pin pad stress |
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| CNB2004100847936A CN100524710C (en) | 2004-12-01 | 2004-12-01 | Focal plane device with lowered indium pin pad stress |
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| CN1638135A CN1638135A (en) | 2005-07-13 |
| CN100524710C true CN100524710C (en) | 2009-08-05 |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100444381C (en) * | 2006-10-13 | 2008-12-17 | 中国科学院上海技术物理研究所 | Backward integrated micro-lens infrared focal plane detector and micro-lens producing method |
| CN100433328C (en) * | 2006-11-08 | 2008-11-12 | 中国科学院上海技术物理研究所 | Infrared focal plane detector with antireflective convergence microlens and microlens preparing method |
| CN102156763B (en) * | 2010-12-16 | 2012-10-03 | 河南科技大学 | Structure optimizing method for large-planar-array infrared detector without underfill |
| CN102185026B (en) * | 2011-04-06 | 2012-11-07 | 华中科技大学 | Method for manufacturing flexible infrared detector |
| CN103165472A (en) * | 2011-12-15 | 2013-06-19 | 北京大学深圳研究生院 | Fiber channel (FC)-ball grid array (BGA) packaging bump distributed heat dissipation novel method |
| CN103633107B (en) * | 2013-12-16 | 2016-05-11 | 中国电子科技集团公司第四十四研究所 | Focus planardetector mounting structure |
| CN104393097B (en) * | 2014-09-30 | 2017-02-08 | 中国空空导弹研究院 | Indium bump face-down bonding interconnection method |
| CN105244355B (en) * | 2015-09-30 | 2018-09-14 | 河南科技大学 | Infrared focal plane detector |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6541857B2 (en) * | 1999-10-25 | 2003-04-01 | International Business Machines Corporation | Method of forming BGA interconnections having mixed solder profiles |
| JP2003158303A (en) * | 2001-11-22 | 2003-05-30 | Kyocera Corp | Thermoelectric element module, package for accommodating semiconductor device, and semiconductor module |
| JP2004172433A (en) * | 2002-11-21 | 2004-06-17 | Fujitsu Ltd | Electronic parts and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6541857B2 (en) * | 1999-10-25 | 2003-04-01 | International Business Machines Corporation | Method of forming BGA interconnections having mixed solder profiles |
| JP2003158303A (en) * | 2001-11-22 | 2003-05-30 | Kyocera Corp | Thermoelectric element module, package for accommodating semiconductor device, and semiconductor module |
| JP2004172433A (en) * | 2002-11-21 | 2004-06-17 | Fujitsu Ltd | Electronic parts and its manufacturing method |
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