CN100524231C

CN100524231C - Method and apparatus for non-intrusive tracing

Info

Publication number: CN100524231C
Application number: CNB2005800348860A
Authority: CN
Inventors: 伊塔伊·佩莱德; 摩西·安舍尔; 尤里·达扬; 雅各布·埃弗拉特; 亚伯拉罕·霍恩
Original assignee: Freescale Semiconductor Inc
Current assignee: NXP USA Inc
Priority date: 2004-09-14
Filing date: 2005-09-13
Publication date: 2009-08-05
Anticipated expiration: 2025-09-13
Also published as: KR20070057944A; WO2006030381A3; EP1805615A2; EP1805615A4; TW200625071A; JP2008513875A; CN101040263A; WO2006030381A2; US7249288B2; US20060069952A1

Abstract

A method and apparatus non-intrusive tracing. The method includes: counting selected events by multiple counters; sampling the multiple counters to retrieve multiple counter values in response to predefined triggering events; receiving additional trace information that comprises at least one program counter value, and outputting, as a trace information, at least one of the multiple counters values and the additional trace information.

Description

The method and apparatus that is used for non-intrusive tracing

Technical field

The present invention relates to be used to follow the tracks of the method and apparatus that occurs in based on the incident on the equipment of processor, relate in particular to the method and apparatus system that is used for non-intrusive tracing.

Background technology

The Modern microprocessor high complexity.They generally include a plurality of parts, can carry out multiple-task with very high speed.Many modern comforts generally include one or more processors, controller and various memory module, comprise cache memory.

The known various system and method that is used to extract the information that can reflect how computerized system works.These devices comprise sheet debugging device, on-chip emulator etc.

IEEE-ISTO 5001 ^TMStandard is also referred to as NEXUS, has defined a kind of standard debug interface that embedded Control is used that is used for.NEXUS provides the Debugging message of relatively limited quantity, but can processor controls.The information of following the trail of can send via special I/O pin or via jtag interface, but and so nonessential.

Following United States Patent (USP) and patented claim are all incorporated by reference at this, the United States Patent (USP) 6 that is entitled as " System for tracing hardware counters utilizing programmed traceinterrupt after each branch instruction or at the end of each code basicblock " of the example of some state of prior art debugging and simulator and method: Smolders is provided, 253,338; The U.S. Patent application 2002/0049893 that is entitled as " Accessing diagnosticprogram counter value data within data processing system " of Williams etc.; The United States Patent (USP) 6,615,370 that is entitled as " Circuit for storing traceinformation " of Edwards etc.; And the United States Patent (USP) 6,134,676 that is entitled as " Programmable hardware event monitoring method " of VanHuben etc.

The bulk information of expression based on the behavior of the complication system of processor need be provided, the relevant information of dependent event mutually especially is provided.

Except the needed information of known standard, also need to provide trace information, and standard-track information providing on standard interface is not provided.

Summary of the invention

In order to overcome above one or more defectives of the prior art, according to a first aspect of the invention, provide a kind of device that is used for non-intrusive tracing, described device comprises: a plurality of counters are used for the incident of a plurality of selections is counted; Described device is characterised in that, comprising: a plurality of shadow registers, be connected to a plurality of counters, and be used for a plurality of counters being sampled, thereby a plurality of Counter Values are provided, with the response trigger event in seamless mode; Counter and register logical are connected to a plurality of counters and a plurality of shadow register, are used to control the operation of a plurality of counters and a plurality of shadow registers; And trace logic, be connected to a plurality of shadow registers, be suitable for: receive a plurality of Counter Values and reception comprise the additional trace information of at least one program counter value and export a plurality of Counter Values and additional trace information one of at least.

In order to overcome above one or more defectives of the prior art, according to a second aspect of the invention, provide a kind of method that is used for non-intrusive tracing, described method comprises: by a plurality of counters the incident of selecting is counted; Described method is characterised in that: a plurality of counters are sampled to extract a plurality of Counter Values, with response predetermined trigger incident in seamless mode by a plurality of shadow registers that are connected to a plurality of counters; Wherein said a plurality of counter and a plurality of shadow register are by counter and register logical control; Receive the additional trace information that comprises at least one program counter value by the trace logic that is connected to a plurality of shadow registers; And export a plurality of Counter Values and additional trace information one of at least by trace logic, as trace information.

The present invention allows to provide the trace information that can reflect a plurality of Counter Values, and these a plurality of Counter Values are that selected incident is counted.Except described these values, perhaps as to the substituting of described these values, trace information can also comprise additional trace information.Additional trace information comprise following at least one: the privilege level of program counter value, processor and task ID.

The present invention allows the content of one or more counters is sampled, the additional trace information that receives with response.

The present invention allows to provide the information about the incident of the information of the incident that is associated with processor and the parts outside the relevant processor.

The invention provides a kind of device that is used for non-intrusive tracing, this device comprises: (i) a plurality of counters are used for the incident of a plurality of selections is counted; (ii) a plurality of shadow registers are connected to a plurality of counters, be used in seamless mode a plurality of counters being sampled, thereby a plurality of Counter Values are provided, with the response trigger event; (iii) counter and register logical are connected to a plurality of counters and a plurality of shadow register, are used to control the operation of a plurality of counters and a plurality of shadow registers; And (iv) trace logic, be connected to a plurality of shadow registers, be suitable for: (i) receive a plurality of Counter Values, and receive comprise at least one program counter value and the indication of processor privilege level and task ID one of at least additional trace information and (ii) export a plurality of Counter Values and additional trace information one of at least.

The invention provides a kind of method that is used for non-intrusive tracing, this method comprises: (i) by a plurality of counters the incident of selecting is counted; (ii) a plurality of counters are sampled to extract a plurality of Counter Values, with response predetermined trigger incident; (iii) receive the additional trace information that comprises at least one program counter value, the indication of processor privilege level and/or task ID; And (iv) export a plurality of Counter Values or additional trace information, or these two all exports, as trace information.

Description of drawings

By following detailed, in conjunction with the accompanying drawings, with more fully understanding and cognition the present invention, in the accompanying drawings:

Fig. 1 is the synoptic diagram of system according to an embodiment of the invention;

Fig. 2 is the schematic depiction of debugging according to an embodiment of the invention with simulation unit;

Fig. 3-5 illustrates various according to an embodiment of the invention control registers; And

Fig. 6-the 7th is according to the process flow diagram of the method that is used for non-intrusive tracing of the embodiment of the invention.

Embodiment

Fig. 1 illustrates system 100 according to an embodiment of the invention.System 100 comprises digital signal processor (being called DSP or processor) 110, data channel 130, Memory Management Unit (MMU) 300, instruction path 340, one-level RAM storer 370 and interface unit 380.

Processor 110, instruction path 340, shared storage 370 and MMU300 are connected to a program bus 120.Instruction path 340 comprises instruction cache module 350 and is responsible for instruction cache module 350 is instructed the instruction fetch unit (IFU) 360 of getting and looking ahead.

DSP 110 has first FPDP 116 and second FPDP 118.First FPDP 116 is connected to first port one 32 of data channel 130 via first data bus (XA) 122, is connected to MMU 300 and is connected to one-level RAM storer 370.Second FPDP 118 is connected to second port one 34 of data channel 130 via second data bus (XB) 124, is connected to MMU 300 and is connected to one-level RAM storer 370.In order to simplify explanation, the address bus that is associated with each data and address bus does not show.

Data channel 130 is got bus 126 via data and is connected to interface 380, and interface 380 is connected to one or more additional storeies again, such as high-grade storer 50.Annex memory can be the part of multilevel cache framework, and the data cache module in the data channel is a first order cache module, and other storer is second level cache and/or storer.They also can be parts that is called as the external memory storage of primary memory.

MMU 300 comprises hardware protection unit 320, is used to provide program and data hardware protection, also comprises converting unit 310, is used for the conversion of high speed virtual address to physical address.MMU 330 can also provide various high-speed caches and bus control signal.Virtual address is the address that is generated by processor 100, checks by the code of being carried out by processor 110.Physical address is used to visit various memory set.

Data channel 130 comprises: follow the tracks of write buffer (TWB) 160; A plurality of memory entities (system is designated as 162) are such as cache memory and one or more additional write buffer; And DCU data control unit (DCU) 150, it is arbitrated between the bus request of TWB 160 and other memory entities 162.DCU 150 can use various known arbitration schemes.Easily, DCU 150 arbitrates between various bus request according to predetermined priority.TWB 160 issues the low priority bus request from TWB 160 usually, but also can issue the high priority bus request in some cases.

Fig. 2 debugs and the schematic depiction of emulation (profiling) unit (DPU) 500 according to an embodiment of the invention.

DPU 500 comprises a plurality of counters, such as counter 611-616, it is arranged to two groups, every group of 3 counters, DPU 500 also comprises a plurality of shadow registers (shadow register) 621-626, counter and register logical 610, ID Compare Logic 645, NEXUS interface 675, interface 629 and a plurality of trace logics unit, and administrative unit 640, first switch unit 650, compressor reducer 655, second switch unit 670 and trace information logic 652 are write in a plurality of trace logics unit such as tracking.DPU 500 is connected to on-chip emulator (being also referred to as EOnCE) unit 502, is connected to the high-grade trace information parts such as NEXUS piece 504, and is connected to TWB160.According to other embodiments of the invention, trace logic can comprise following at least one: ID Compare Logic 645, NEXUS interface 675, interface 629, increase unit or reduce the unit on the basis of the above.Simulation unit on the sheet such as EOnCE unit 502, is well known in the art.EOnCE unit 502 is at SC140e ^TMIn the 4th chapter of DSP Core Reference Manual description is arranged, incorporated by reference at this.

The visit that EOnCE unit 502 allows the specified quantitative of various registers, programmable counter (PC) etc.It is connected with the jtag interface unit so that JTAG compatible signal (test data input TDI, test data output TDO, test clock input TCK, test pattern are selected input TMS and test reset TRST) to be provided.

Briefly, EOnCE unit 502 comprises EOnCE controller, event counter, tracking cell, event detection unit, incident selector switch and lock unit.The event detection unit comprises six address events sense channel EDCA5～EDCA0, each can both with address wire that the first or second data bus XA 122 and XB 124 are associated on detect the appearance of particular address (address that perhaps belongs to particular address range).

EOnCE unit 502 can work in various operator schemes, and be used to follow the tracks of variety of event, comprise: (i) TEXEXT-follows the tracks of the PC that each carries out set, (ii) TMARK-follows the tracks of the PC of the execution set that comprises the MARK instruction, (iii) TCHOF-follows the tracks of and comprises that predetermined stream changes the source and target PC of the instruction set of instruction, (iv) TLOOP-follows the tracks of the execution of hardware loop, for long circulation, follow the tracks of the PC of FA final address and start address, for short circulation, only follow the tracks of the PC of FA final address, (v) TSUB-follows the tracks of the source and target PC of the execution set that comprises subroutine call or link order, (vi) TRTE-follows the tracks of the source and target PC comprise the execution set of returning from exceptional instructions, and (vii) TINT-follows the tracks of and interrupts and the unusual point of interruption and target P C.In addition, when the incident of tracking, can lock-on counter value and extension counter value.

Usually, in case having taken place, stream changes the task sign that EOnCE unit 502 can provide one or more program counter value and be used to reflect the privilege level of processor.

Counter and register logical 610 comprise a plurality of control registers, such as control register 710-736, be used for determining counter 611-616 to which incident counts, and which incident will make shadow register 621-626 with non-invasive mode sample counter 611-616.

Each counter all is 31 following counter registers among the counter 611-616, and it can be operated in single step count mode and tracing mode.In preceding a kind of pattern, counter is counted from certain programmed value to 0, sets up incident then and stops counting.This incident can trigger the unusual or debugging interruption of debugging so that processor 110 enters debugging mode.In a kind of pattern in back, counter keeps counting, reaches 0, and Cyclic Rings is around also continuing counting.The content of counter 611-616 is read by shadow register 621-626 when the incident of tracking.

DPU 500 can write virtual trace buffer (VTB) 670 via the trace information that TWB 160 generates EOnCE or DPU 500 generates.It can also write trace information outside NEXUS piece 504.

Easily, VTB 670 is the storage spaces in the high-grade memory module 50, and by the start address and the end address definition that are stored in each control register, the back will be described.Control register is also preserved the pointer that sensing should receive the current storage clauses and subclauses of trace information.

The process that administrative unit 640 control trace informations are write VTB 670 is write in tracking.Trace information can write out from VTB 670 with three kinds of possible patterns.When working in Overtype Mode, to follow the tracks of write address and be recycled to start address, tracking data is rewritten old data.This tracing mode makes it possible to check the trace information that is directed to breakpoint or erroneous point.When working in single address pattern, trace information is written into a programmable address.This allows trace information is write peripherals such as serial interface unit.When working in tracking event request pattern, in case VTB 670 is filled, the information among the VTB 670 can be read termly.DPU 500 can generate the interruption that activates VTB 670 read operations, for example passes through DMA.Trace information can comprise the trace information that the EOnCE unit of trace information (such as the content of six register 611-616) that DPU generates, trace information that the EOnCE unit generates and compression generates.First and

second switch units

650 and 670 receiving control informations are used for selecting which information of output.According to one embodiment of the invention, trace information can comprise the combination of these information.According to another embodiment of the present invention, VTB 670 can receive specific tracking information, and NEXUS piece 504 receives other trace informations simultaneously.This differentiation can obtain simply utilizing by existing logical block.

The information that the EOnCE unit generates is compressed unit 655 compressions, and compression unit 655 can provide below with compression scheme or the various known compression scheme mentioned.According to one embodiment of the invention, compressor reducer compresses the trace information that the EOnCE unit generates by deleting redundant cyclical information.For example, if trace information reflects the appearance of short hardware loop, only write the round-robin FA final address and carry out the round-robin number of times.If trace information reflects the appearance of long hardware or software cycles, only write round-robin FA final address or round-robin start address and carry out the round-robin number of times.DPU comes the appearance of the short hardware loop of mark by short circulation sign, and indicates the appearance of Great Wall Software's part or hardware loop with long circulation sign.

TWB 160 has the degree of depth of eight 256 clauses and subclauses.When TWB 160 filled up, it sent the high priority bus request to DCU 150, otherwise it sends the low priority bus request to DCU150.

The quantity by determine wanting tracked information and the control signal of type can control to the visit of VTB 670, and the trace information that arrive VTB 670 to TWB 160, subsequently flows.

Trace information can comprise a plurality of tracking marks.Each tracking mark has unique value, and it can not be interpreted as other trace information, such as the program address.Tracking mark, except virtual mark, the type of indicators track information.Tracking mark comprises that user task sign, power user's task sign, short circulation sign, long circulation sign, VTB fill up sign and virtual mark.

Two kinds of task signs are arranged---user task sign and power user's task sign.Therefore, the task sign has reflected the privilege level of task.User task sign instruction processorunit is operated in user privilege level, also comprises task ID.Power user's task sign instruction processorunit is operated in supervisor privilege level.VTB is empty to indicate that with filling up being used for TWB fills up, and does not transmit trace information.

According to one embodiment of the invention, table 1 has illustrated the tag format of example.The value of position 0 is that X represents that it can be 0 or 1, depends on the environment (referring to table 2) that uses this sign.

Table 1

Mark name	Position 31-20	Position 19-17	Position 16-1		Position 0
Mark name	Position 31-20	Position 19-17	Position 16-1		Position 0	The user task sign	The DPU base address	000	Task ID		X

Power user's task sign	The DPU base address	001	16′h0	X
Power user's task sign	The DPU base address	001	16′h0	X	Short circulation sign	The DPU base address	010	16′h1	0
Long circulation sign	The DPU base address	010	16′h2	0	Short circulation sign	The DPU base address	010	16′h1	0
Long circulation sign	The DPU base address	010	16′h2	0	VTB fills up sign	The DPU base address	010	16′hFFFF	1
Virtual mark	The DPU base address	010	16′h0	0	VTB fills up sign	The DPU base address	010	16′hFFFF	1

The DPU base address is the unique address that can not be interpreted as program counter value.

In first operator scheme, when the generation task was switched, DPU 500 can preserve following message: a PC of the last PC of last task, the value of counter 611-616, new task and the task sign of new task.EOnCE unit 502 will be programmed, and interrupt and the RTE instruction thereby follow the tracks of simultaneously.The task sign comprises the indication of relevant processor privilege level.

In second operator scheme, when processor jumps to subroutine or interrupt routine or when subroutine or interrupt routine return, DPU 500 preservation information.In case such incident has taken place, EOnCE unit 502 sends source PC and target P C to DPU 500.In case it is right to receive such PC, the sampling of the 500 pairs of following messages of DPU: jump to subroutine or interrupt routine or return from subroutine or interrupt routine before value, task sign and the stream of last PC, the counter 611-616 PC after changing.EOnCE unit 502 is programmed, and changes instruction thereby follow the tracks of following stream: jump to interrupt routine, return, jump to subroutine and return from subroutine from interrupt service routine.

In the 3rd operator scheme, during the sampling in PD_TC 740 is set (SAMPLE) position, DPU 500 preserves following message: value and the virtual mark of task sign, counter 611-616, virtual mark is 256 bits in order to the size of guaranteeing each tracking message.In case the first information partly is sent to TWB 160, sample bits resets.

In the 4th operator scheme, when the address events sense channel EDCA5 of EOnCE generation incident, when it can be the breakpoint of this detected any kind in unit, DPU 500 preservation information.Preserve following message: value and the virtual mark of task sign, counter 611-616.

In the 5th operator scheme,, then its content is written to TWB 160 in case carry out the write access of tracking data register (in Fig. 5, being designated as DP_TD 750).

With specific format trace information is written to TWB 160.Following the tracks of clauses and subclauses is write operations from DPU 500 of any number, and it generates the result who follows the tracks of incident as.Mention at least one in the sign above the tracking clauses and subclauses comprise, and easily, have the form shown in the table 2.Those skilled in the art will recognize that, also can use other form.

Table 2

According to above-mentioned form, first trace information that writes TWB 160 is characterised in that the LSB value is 1, and what follow thereafter is additional trace information, it is characterized in that the LSB value is 0.This makes trace information resolve easily.

DPU 500 comprises a plurality of control registers.Most of these control registers belong to counter and register logical 610, but some belongs to follow the tracks of and writes administrative unit 640 and ID Compare Logic 645.These registers comprise general control register, counter control register and trace buffer register.

Trace information logic 652 is connected to

first switch unit

650, and 502 receive trace informations from the EOnCE unit, some this information and predetermined (normally programming) value more at least, and, can begin one or more trigger events in response to described part.Trace information logic 652 is connected to counter and register logical 610 so that provide about the indication of one or more trigger events occurring.

Fig. 3 illustrates various according to an embodiment of the invention general control registers.General control register comprises control register (DP_CR) 700, status register (DP_SR) 702, and control register (DP_MR) 704, PID detect reference value register (DP_RPID) 706 and DID detects reference value register (DP_RDID) 708.

Control register (DP_CR) 700 comprises two ID relatively position (TIDCM, position 29-28), and whether its definition ID Compare Logic 645 is considered data task ID and/or instruction task ID or do not considered.

Some position (position 27-14) various EOnCE of indication generate incident (ISEDACA5～ISEDACA0, position 27-16), EOnCE generates 0,1 or 2 interrupt request whether interrupt request (EIS, position 14) can cause program interrupt controller (PIC) (not shown).The position that DP_CR70 is left (position 13-0) indicates whether that interrupt request is sent to the PIC request of maybe will debugging sends to EOnCE unit 502, generates incident (DECB2～DECA0, position 11-0) or the incident (DETB, position 13-12) relevant with tracking with the response count device.

Status register (DP_SR) 702 comprises trace buffer significance bit (TWBA, position 6), whether there is trace information not arrive VTB 670 among the expression TWB 160, also comprises six counter enable bit (ENCB2～ENCA0, position 5-0), whether every bit representation starts or each counter of stopping using.

Control register (DP_MR) 704 comprises the full position of trace buffer (TBF, position 9), and expression TWB 160 is full, also comprises a plurality of positions (DRA, DRN, DRTB, DRCB2～DRCA0), existing debugging request of expression or the reason of interrupting.These reasons can be the incidents that external debug request, NEXUS debug request, tracking incident or be associated with one of six counters.

PID detects reference value register (DP_RPID) 706 and comprises that 8 referral procedure ID values (RPID, position 7-0) are so that compared by ID Compare Logic 645.

DID detects reference value register (DP_RDID) 708 and comprises that 8 reference data ID values (RDID, position 7-0) are so that compared by ID Compare Logic 645.

Fig. 4 illustrates some counter control register according to an embodiment of the invention.Counter control register comprises first counter set register (DP_TAC) 710, second counter set register (DP_TBC) 712, first to the 6th counter control register (DP_C1～DP_C6) 714-724, and first to the 6th Counter Value register (726-736 of DP_C1～DP_C6).

First counter set register (DP_TAC) 710 comprises set disable mode privilege level position (TDMP, position 29-28), outside its ID value of to need determining, can forbid the privilege level (user or power user) of the operation that counter gathers.DP_TAC further comprises the position (TDM, position 27-24) of the incident that is used for the set of regulation disable register, and stipulates that especially which EDCA is associated with the incident that can forbid the counter set.Except above-mentioned position, DP_TAC also comprises register set syntype privileged bit (TENMP, position 21-20), its definition can the enabling counting device the privilege level of incident (being also referred to as the tracking incident), the position (TENM, position 19-16) that also comprises the incident that starts set of registers, and counting event group privilege level position (CEGP, position 13-12), it has defined the privilege level of the task of comprising the tracking incident.After these positions is counter event group position (CEG, position 8-4), which its expression followed the tracks of event sets and counted to, also has counter set syntype register-bit (CMODE, position 2-1), whether its definition counter set operates in single step count mode or tracing mode, is TCEN position (position 0) at last, and whether separately it determine register Be Controlled or be subjected to collective's control.

Second counter set register (DP_TBC) 712 is identical with first counter set register 710, but controls second counter set 614-616.

(each among the 714-724 of DP_C1～DP_C6) is all similar to counter set register DP_TAC, but controls independent counter rather than control register set for six counter control registers.Least significant bit is disabled.

(each among the 726-736 of DP_C1～DP_C6) is all preserved each 31 bit counter value of six counters, and it is as initial count value and the ongoing Counter Value after starting for six Counter Value registers.

Fig. 5 illustrates various tracking cell registers, such as: tracking Control register (DP_TC) 740, VTB initial address register (DP_TSA) 742, VTB end address register (DP_TSA) 744, tracking event request register (DP_TER) 746, tracking write pointer register (DP_TW) 748 and tracking data register (DP_TD) 750.

Tracking Control register (DP_TC) 740 comprises privileged bit (PROV, position 21), the privilege of expression VTB write access.DP_TC 740 also comprises global operation attribute (GLOBAL, position 20-19), expression is to the burst sizes position (BURST-SIZE of the burst sizes (common, two, four or eight BDU) of the write operation of VTB670, position 17-16) and temporary transient unused bit (TMPDIS, position 12), be used to allow to refresh the content of TWB160, all arrive VTB 670 so that verify all trace informations.DP_TC 740 further comprises virtual trace buffer WriteMode position (VTBWM, position 9-8), and whether the expression trace information will or be followed the tracks of the event request pattern and write with Overtype Mode, single address pattern.After these positions is that samples counter value arrives VTB position (SAMPLE, position 6) and tracing mode position (TMODE, position 4-1), the trace information that expression is being exported generates trace information, compression EOnCE generation trace information (and the task sign that adds), has the value of six counters of additional trace information such as EOnCE.The least significant bit of DP_TC 740 is enable bit (EN), and whether expression starts tracking.

VTB initial address register (DP_TSA) 742 stores 32 physical addresss of the beginning of virtual trace buffer 760.VTB end address register (DP_TSA) 744 stores 32 physical addresss of the ending of virtual trace buffer 760.Follow the tracks of 32 bit address that event request register (DP_TER) 746 stores in the VTB 670, should generate at this and interrupt or the debugging request.When DPU 500 is operating as tracking event request event schema, this address is write.Follow the tracks of 32 pointers that write pointer register (DP_TW) 748 is stored into VTB 670 clauses and subclauses, write current trace information at this.Tracking data register (DP_TD) 750 stores the data that write VTB 670 with certain operational modes.

Easily, the incompatible track of events set of counter set can be set.Table 3 illustrates the variety of event set that the set of three registers is followed the tracks of.

Table 3

Thing second rolling counters forward the 3rd rolling counters forward of event sets title first rolling counters forward

The incident of the incident of part

Instruction cache instruction cache miss instruction cache instruction cache is pre-

Hit-miss incident hit incident is got the hit incident

Data cache data cache miss data cache data cache is pre-

Hit-miss incident hit incident is got the hit incident

High-speed cache wobble data high-speed cache since high data cache by

Speed buffer memory miss incident and in scanning swing and pendulum x

Swing is moving

The processor delay cycle in armed statees such as processor delay rate, clock period week

The waiting period

The processor delay base is because the high-grade storage because data high-speed is slow of instruction cache

The processor of the processor delay device module that this division processor delay cycle deposits

The cycle delay cycle

Since instruction at a high speed since high-speed cache since non-high-speed cache because instruction is slow at a high speed

The processor miss of buffer memory is the high processor of competition of depositing to the at a high speed slow property miss of instruction to instruction

The processor of the visit that delay is deposited prolongs the delay period of the visit of fast buffer memory

Slow period treatment device delay period

The incident of the incident of part

Since data high-speed since high-speed cache since non-high-speed cache because data high-speed is slow

The processor miss of buffer memory deposits the processor of competition to the slow property miss of data high-speed to the data height

Slow period treatment device delay period

Since high-speed cache since high-speed cache write by writing and freeze continuously because high-speed cache is write

Write by the competition in the buffer buffers device to locate by impact damper be full processor delay week

Processor delay cycle of processor delay reason device delay period

Phase

Because high-grade depositing because the competition among the HLMM is competed because data-data are competed owing to program-data

The processor delay that the processor delay striven of the processor delay cycle of memory modules is striven

(HLMM) cycle in processing cycle

Device postpones

When bus was busy when interface instruction bus clock cycle bus was waited for service the time

The clock clock of load

When bus was busy when interface data bus clock cycle bus was waited for service the time

The clock clock of load

Since write the VTB clock period since write VTB owing to write VTB's

The interface data bus when bus is busy when waiting for service the time

The clock clock of linear load

VTB writes processor clock cycle owing to write the processor delay cycle of VTB

Postpone the processor delay cycle

The DMA interface locked clock cycle connects the processor delay cycle owing to write DMA

The processor of retardation rate mouth locking

Delay period

Fig. 6 is the process flow diagram that is used for the method 800 of non-intrusive tracing according to an embodiment of the invention.Method 800 starts from step 810, by a plurality of counters selected incident is counted.Referring to the example described in Fig. 2, counter and register logical 610 determine counter register 611-616 to which tracking incident counts.Should determine the content in response to various control registers, these contents help to control separately each counter, or even help to control based on event sets.Control register can be configured during preliminary configuration step 805.Method 800 execution in

step

820 and 830 when the arrow presentation of events from frame 810 to himself is counted.

Method 800 further comprises the step 820 of a plurality of counters of sampling, in order to extract a plurality of Counter Values in the non-intruding mode, with response predetermined trigger incident.Referring to the described example of Fig. 2, shadow register 621-626 is suitable for when receiving trigger event the content of counter 611-616 being sampled.Trigger event is scheduled to, and especially uses various control registers.Each shadow register can be carried out sampling operation, and no matter the situation of other shadow registers.

After the step 820 steps 830 of a plurality of Counter Values of output as trace information.Referring to the example described in the prior figures, interface 645 is output tracking information in every way.

Fig. 7 is the process flow diagram of method 900 according to an embodiment of the invention.

Method 900 starts from step 805, is thereafter step 810 and 820.

Parallel with these steps, method 900 comprises step 910, receives additional trace information, such as the trace information of EOnCE generation.After the step 910 is step 920 and 925.Step 920 comprises the compression trace information.Step 925 comprises that ID is generated trace information with EOnCE compression or that do not have compression to be associated, and ID can be data ID or Information ID.

After the

step

925 and 820 is step 860, and which information selection should export as trace information.This can be one of three kinds of trace information types or its can be their combination.Easily, if select the trace information of output compression, then can only add task ID information, and not add Counter Value.

After the step 860 is step 960, output tracking information.This can comprise information is write VTB 670 via TWB 160, and/or some information writes NEXUS piece 504 via NEXUS interface 675 at least.

The variation of embodiment described here, modification and other realizations are obvious to those skilled in the art, do not deviate from the present invention's spirit and scope required for protection.Therefore, the present invention is not limited to the illustrative of front and describes, but is limited by the spirit and scope of claim.

Claims

1. device (10) that is used for non-intrusive tracing, described device comprises: a plurality of counters (611-616) are used for the incident of a plurality of selections is counted; Described device (10) is characterised in that, comprising:

A plurality of shadow registers (621-626) are connected to a plurality of counters, be used in seamless mode a plurality of counters being sampled, thereby a plurality of Counter Values are provided, with the response trigger event;

Counter and register logical (610) are connected to a plurality of counters and a plurality of shadow register, are used to control the operation of a plurality of counters and a plurality of shadow registers; And

Trace logic (629,640,645,650,655,670,675), be connected to a plurality of shadow registers, be suitable for: (i) receive a plurality of Counter Values and reception comprise the additional trace information of at least one program counter value and (ii) export a plurality of Counter Values and additional trace information one of at least.

2. device as claimed in claim 1 (10) further comprises following the tracks of and writes administrative unit (640), is suitable for controlling the write process of trace information to virtual trace buffer (670).

3. device as claimed in claim 2 (10) further comprises and follows the tracks of write buffer (160), is used to receive trace information and is used for trace information is offered virtual trace buffer.

4. device as claimed in claim 1 (10) further comprises compressor reducer (655), is suitable for compressing trace information.

5. device as claimed in claim 4 (10), wherein said compressor reducer (655) are suitable for compressing trace information by the trace information that the deleted representation round-robin occurs.

6. device as claimed in claim 5 (10), wherein said compressor reducer (655) are suitable for by providing the circulation sign that the indication that occurs for round-robin is provided, and this indication has reflected circulation repetition number and circulation address.

7. as any described device (10) in the claim 1～6, wherein said a plurality of counter (611-616) is arranged to counter set, wherein said counter and register logical (610) thus being used for set of registers programmed follows the tracks of event sets.

8. as any described device (10) in the claim 1～6, be further adapted in response to incident and begin to interrupt.

9. as any described device (10) in the claim 1～6, being further adapted for provides trace information to high-grade trace information assembly (504).

10. as any described device (10) in the claim 1～6, wherein, at least one trigger event is the reception of predetermined additional trace information.

11. as any described device (10) in the claim 1～6, wherein, at least one trigger event is a stream change incident.

12. as any described device (10) in the claim 1～6, wherein, at least one trigger event is the change of the privilege level of tracked processor.

13. as any described device (10) in the claim 1～6, wherein said additional trace information further comprises the indication of processor privilege level.

14. as any described device (10) in the claim 1～6, wherein said additional trace information comprises tracking mark.

15. device as claimed in claim 14 (10), wherein said tracking mark is selected from: task sign, power user's task sign, short circulation sign, long circulation sign and virtual trace buffer VTB fill up sign.

16. a method (900) that is used for non-intrusive tracing, described method comprises: by a plurality of counters the incident of selecting is counted (810); Described method (900) is characterised in that:

In seamless mode a plurality of counters are sampled (820) to extract a plurality of Counter Values, with response predetermined trigger incident by a plurality of shadow registers that are connected to a plurality of counters; Wherein said a plurality of counter and a plurality of shadow register are by counter and register logical control;

Receive the additional trace information (910) that comprises at least one program counter value by the trace logic that is connected to a plurality of shadow registers; And

Export a plurality of Counter Values and additional trace information one of at least by trace logic, as trace information (830).

17. method as claimed in claim 16 (900) further comprises trace information is write virtual trace buffer.

18. method as claimed in claim 16 (900) further comprises the additional trace information (920) of trace information so that compression to be provided of compression.

19. method as claimed in claim 18 (900), wherein said compression (920) comprise the trace information that the deleted representation round-robin occurs.

20. method as claimed in claim 18 (900), wherein said compression (920) have produced the indication for the round-robin appearance that comprises the circulation sign, this indication has reflected number and the circulation address that circulation repeats.

21., comprise that further the set of configuration counter is with the preliminary step to the event sets counting as any described method (900) in the claim 16～20.

22. as any described method (900) in the claim 16～20, wherein, at least one trigger event is the reception of predetermined additional trace information.

23. as any described method (900) in the claim 16～20, wherein, at least one trigger event is a stream change incident.

24. as any described method (900) in the claim 16～20, wherein, at least one trigger event is the change of the privilege level of tracked processor.

25. as any described method (900) in the claim 16～20, wherein said additional trace information further comprises the indication of processor privilege level.

26. as any described method (900) in the claim 16～20, wherein said additional trace information comprises tracking mark.

27. method as claimed in claim 26 (900), wherein said tracking mark is selected from: task sign, power user's task sign, short circulation sign, long circulation sign and virtual trace buffer VTB fill up sign.

28. a device that is used for non-intrusive tracing, described device comprises:

A plurality of counters are used for the incident of a plurality of selections is counted;

A plurality of shadow registers are connected to a plurality of counters, be used in seamless mode a plurality of counters being sampled, thereby a plurality of Counter Values are provided, with the response trigger event;

Counter and register logical are connected to a plurality of counters and a plurality of shadow register, are used to control the operation of a plurality of counters and a plurality of shadow registers; And

Trace logic is connected to a plurality of shadow registers, one of is suitable for exporting in a plurality of Counter Values at least.

29. a method (800) that is used for non-intrusive tracing, described method comprises:

By a plurality of counters the incident of selecting is counted (810);

By a plurality of shadow registers that are connected to a plurality of counters a plurality of counters are sampled (820) to extract a plurality of Counter Values, with response predetermined trigger incident; And

Export a plurality of Counter Values by the trace logic that is connected to a plurality of shadow registers, as trace information (830); Wherein said a plurality of counter and a plurality of shadow register are by counter and register logical control.