GB2380827A

GB2380827A - Debugging of processors using two separate event detectors

Info

Publication number: GB2380827A
Application number: GB0124555A
Authority: GB
Inventors: David Alan Edwards
Original assignee: Siroyan Ltd
Current assignee: Siroyan Ltd
Priority date: 2001-10-12
Filing date: 2001-10-12
Publication date: 2003-04-16
Also published as: GB0124555D0

Abstract

Processor circuitry such as a "system-on-chip" (SOC) device comprises one or more processing units (40, 42), at least first and second debug event detectors (12, 14), each for detecting when a debug event occurs in one of the processing units, and a debug correlation element (16) comprising a counter (18) for holding a count value (20). Interconnection circuitry (22) provides a first signal path (24) between the first debug event detector and the debug correlation element and a second signal path (26) between said second debug event detector and the debug correlation element. Each signal path serves to transmit at least one control signal to/from the debug correlation element so as to establish a debug relationship between the first and second debug event detectors. In such processor circuitry complex debug relationships can be established between the debug event detectors involving filtering and counter functions.

Description

DEBUGGING OF PROCESSORS The present invention relates to debugging of processors. In particular, but not exclusively, the present invention relates to debugging of processor systems having a plurality of independently-operable processing units, for example a plurality of processor cores in a system-on-chip (SOC) device or a single processor core having a plurality of individual processing units.

Fig. 1 is a schematic view of a debugging system suitable for debugging a processor core (CPU core) 2 in an SOC device 1. The aim of the debugging process is to identify and correct any problems associated with programs executed by the processor core 2. The debugging system comprises a debug module 3 forming part of the SOC device 1, a debug adaptor 4 and a host computer 5 running debugger software 6. The debug module 3 and debug adaptor 4 are able to communicate with one another via a debug link 7. The debug adaptor 4 can provide debug control signals to the debug module 3 via the debug link 7 and can receive debug information generated by the debug module 3 via the debug link 7. The debug adaptor 4 and host computer 5 are able to communicate with one another via a data link 8, which is also a bi-directional link such as an Ethernet connection or a PCI bus.

The debug adaptor 4 comprises a combination of hardware and software capable of interfacing between the host computer 5 and the debug module 3, for example translating between different communication protocols used by the links 7 and 8, and buffering debug information received from the debug module 3 prior to onward transmission to the host computer 5.

Although Fig. 1 shows only a single processor core 1 being debugged, the Fig. 1. system may be used to debug an SOC (processor system) including a plurality of processor cores (processing units). In this case, the debug module 3 preferably supports all the processor cores, enabling each

of them to be linked to the debug adaptor 4 via the debug link 7. Similarly, if the processor core in Fig. 1 has more than one individual processing unit (e. g. a VLIW processor core), the debug module 3 may handle debug information for all the individual processing units.

Incidentally, instead of using a debug adaptor 4 linked to a host computer 5 running debugger software 6 as shown in Fig. 1, it is possible to arrange for the debugger software 6 to be executed by the or each processor core being debugged. Such an arrangement has the advantage of dispensing with the debug adaptor 4 and host computer 5 but suffers from the disadvantage of being very intrusive in the normal execution of the processor core (s).

In the Fig. 1 debugging system several mechanisms may be provided for generating debug information and supplying it to the debugger software 6 running on the host computer 5. These mechanisms include breakpoints, watchpoints, branch trace messaging and CPU event detectors.

A breakpoint can be set in the processor core 2 to raise a debug exception when a specified event occurs during execution of a program by the processor core 2. This debug exception causes a debug exception handler to execute in preference to the normal execution of the program being debugged. The breakpoint may be a data breakpoint or an instruction breakpoint. A data breakpoint triggers a debug exception when a load/store operation is performed in a specified address range. An instruction breakpoint triggers a debug exception when an instruction within a specified address range is executed. Breakpoints are inherently intrusive monitoring mechanisms because they involve suspending the normal execution of the program being debugged so that the debug exception handler can execute.

By slowing or pausing the normal execution, some types of error may not be reproduced, and thus cannot be detected or corrected. This can result in so-called"Heisenbugs" (named after the Heisenberg Uncertainty Principle), i. e. situations in which the presence or operation of the debugging system

perturbs the normal operation or the processor core such that the bug is no longer manifested.

A watchpoint is similar to a breakpoint but, instead of raising a debug exception when the specified event occurs, the watchpoint causes some other action to take place, for example generating a signal made available externally of the processor core 2 by the debug module 3 or generating a trace message. For example, a data watchpoint may generate a data trace message when a load/store operation is performed within a specified address range. Similarly, an instruction watchpoint may generate an instruction trace message when an instruction within a specified address range is executed.

Instruction breakpoints/watchpoints (IBWs) allow the debugger software 6 to detect execution of specific lines of source code in the processor core when the breakpoint/watchpoint is set to a single address, or to detect execution of specific functions in the processor core when the instruction breakpoint/watchpoint is set to a range of addresses. Data breakpoints/watchpoints (DBWs) allow the debugger software 6 to detect when the processor core reads or writes to specific source-code variables and/or to specific memory mapped registers.

The processor core 2 can be programmed to monitor nonsequential execution events within the core, for example conditional branches, unconditional branches, subroutine calls and returns, system calls, exceptions and interrupts.

When these events occur a branch trace message (BTM) can be generated by the debug module 3 comprising, for example, the program counter values before and after the branch is taken.

Such branch trace messaging allows the debugger software 6 to monitor the control flow of the processor core 2.

The processor core 2 may also include CPU event detectors (CEDs) used to monitor various CPU events such as retiring of an instruction, a cache hit, a cache miss, a translation lookaside buffer (TLB) hit, a TLB miss, a pipeline stall etc. The processor core 2 may also include counters so that each time a particular event is detected by

a CED a count value is incremented. The information gathered using CEDs can be used to optimise the processor core and/or the design of the overall system in which it operates.

Advantageously a filtering mechanism may be provided within the device for carrying out a filtering operation in relation to an event detector (breakpoint or watchpoint etc. ) such that the event detector only triggers in very specific circumstances. For example, it may be desirable to permit a particular data breakpoint to trigger only when one or more specified instruction breakpoints have triggered.

Such a filtering mechanism is useful for a number of reasons. Firstly, when applied to operations such as breakpoints, which would raise debug exceptions, the filtering mechanism can limit the conditions under which the exceptions are raised so that they are more specific. This makes the debugging operation much less intrusive, as the program being debugged (the"debuggee") is only stopped in a set of very specific circumstances. This avoids the need to carry out filtering using the debug exception handler software to check to see if the filtering conditions have been met. Such use of the debug exception handler to carry out the filtering risks affecting the performance of the debuggee, possibly leading to Heisenbugs. Also, when the filtering mechanism is applied to operations which would generate trace information (e. g. watchpoints and branch trace messaging) the filtering operation can limit the circumstances under which trace information is generated so that it is more specific. This makes more effective use of the available bandwidth of the debug link 7 for supplying trace information to the debug adaptor, and so can prevent loss of trace information, as well as limiting the amount of stalling of the processor core necessary when generating trace information.

EP-A-1089184 discloses a single-chip microcomputer (SOC) comprising a CPU and a CPU watchpoint controller which outputs debug information to an on-chip debug module. The

debug module is also linked to a system bus analyser which analyzes signals transmitted on an on-chip system bus. The system bus analyser is capable of setting watchpoints for the system bus. The debug module is also capable of setting further watchpoints. Each watchpoint comprises a programmable precondition register and a programmable action register. A set of latches (referred to as chain latches) is distributed amongst the CPU watchpoint controller, system bus analyser and debug module. A chain latch can be configured to receive an input from the action register of any selected one of the watchpoints and to supply an output derived from that input to the preconditioned register of a selected further one of the watchpoints. This creates a relationship between the two watchpoints linked via the chain latch and, for example, can permit a filtering operation to be implemented.

However, although this debugging system provides enhanced flexibility and features compared to prior systems, it still suffers from certain problems and disadvantages, as follows.

Firstly, the chain latch used to create a relationship between two watchpoints is capable of assuming only one of two states (set, reset). This limits the scope of the relationships that can be created between different watchpoints. It is desirable to be able to establish more complex relationships requiring more than two states.

Secondly, in processor systems having more than one processor core or more than one processing unit within the same processor core, it is desirable to limit the conditions under which one particular processing unit's debug event detectors (e. g. watchpoints) will trigger depending on the occurrence of debug events within another processing unit.

For such systems having plural processing units it has heretofore not been considered feasible to carry out filtering operations involving complex relationships between watchpoints defined in different processor units because the amount of interconnect required to link debug event

detectors in different processor units was considered prohibitively extensive and expensive.

Thirdly, although a watchpoint in the EP-A-1089184 system has counters which can be incremented or decremented when the watchpoint is triggered, relationships between two watchpoints involving the counters rely on separate hardware elements to carry out linking (a chain latch connected between the two watchpoints) and counting (a counter belonging to one of the watchpoints). It is desirable to improve the design of these hardware elements.

According to a first aspect of the present invention there is provided processor circuitry comprising: one or more processing units; at least first and second debug event detectors, each for detecting when a preselected debug event occurs in one of said processing units; a debug correlation element comprising a counter for holding a count value ; and interconnection means for providing a first signal path between said first debug event detector and said debug correlation element and a second signal path between said second debug event detector and said debug correlation element, each said signal path serving to transmit at least one control signal to/from said debug correlation element so as to establish a debug relationship between said first and second debug event detectors.

According to a second aspect of the present invention there is provided a method of debugging a program for a processor using processor circuitry embodying the first aspect of the present invention, comprising: (a) employing said interconnection means to provide said first and second signal paths; (b) establishing such a debug relationship between said first and second debug event detectors; and (c) using the first and second debug event detectors having the established debug relationship to debug the program.

According to a third aspect of the present invention there is provided the debugged program produced by a debugging method embodying the second aspect of the invention. The debugged program may be stored on a

recording medium such as a read-only memory (ROM) so that it can be supplied and used with production devices not including the debug correlation element or parts of the interconnection circuitry.

According to a fourth aspect of the present invention there is provided processor circuitry comprising: one or more processing units; a processor debug unit corresponding to one of said processing units; wherein said processor debug unit includes: a debug event detector for detecting when a. preselected debug event occurs in said corresponding processor unit ; a plurality of action outputs; and action signal generation means connected with said debug event detector and said plurality of action outputs and operable to generate an action signal when said debug event detector detects said preselected debug event and further operable to supply the generated action signal to a selected one of said action outputs.

According to a fifth aspect of the present invention there is provided processor circuitry comprising: one or more processing units ; a processor debug unit corresponding to one of said processing units; wherein said processor debug unit includes: a debug event detector for detecting when a preselected debug event occurs in said corresponding processing unit; a plurality of result inputs, each for receiving a result signal; and result signal supply means connected to said plurality of result inputs of said processor debug unit and to said debug event detector and operable to supply the result signal received at a selected one of said result inputs, or a signal derived therefrom, to said debug event detector, said debug event detector being operable to employ the supplied signal to influence its response to said preselected debug event.

The first and second debug event detectors may be within the same processing unit or within different processing units.

Reference will now be made, by way of example, to the accompanying drawings, in which:

Fig. 1 discussed hereinbefore, is a schematic view showing parts of a conventional debugging system ; Fig. 2 is a schematic view showing parts of a debugging system embodying the present invention; Fig. 3 shows a block diagram of a first example of a debug correlation element suitable for use in a debugging system embodying the present invention; Fig. 4 is a schematic view showing parts of another debugging system embodying the present invention; Fig. 5 is a block diagram of a first embodiment of the Fig. 4 debugging system for use in a clustered processor; Fig. 6 is a block diagram of a second embodiment of the Fig. 4 debugging system for use with a processing system having a plurality of processor cores ; Fig. 7 shows a first example of parts of a processor debug unit for use in a processing unit embodying the present invention; Fig. 8 shows a second example of parts of a processor debug unit for use in a processing unit embodying the present invention; Fig. 9 shows a second example of a debug correlation element for use in an embodiment of the present invention; and Figs. 10 to 14 show examples for use in explaining different ways of using debugging systems embodying the present invention.

Fig. 2 shows parts of a debugging system embodying the present invention. The Fig. 2 debugging system comprises first and second debug event detectors 12 and 14. Each of these debug event detectors is contained in a processing unit and is used to detect one or more preselected debug events occurring in that processing unit. These debug events may be, for example, instruction breakpoints or watchpoints (IBWs), data breakpoints or watchpoints (DBWs), branch events requiring generation of branch trace messaging (BTM), or other CPU events (cache hit, cache miss, etc) The debug event detectors 12 and 14 are preferably

implemented within the pipeline logic of the processor unit or units to which they belong due to timing constraints and a requirement for close integration with pipeline behaviour (i. e. to ensure that precise debug exceptions can be generated).

The constitution of each type of event detector is dependent on the event being detected, but is well-known in the art. For example an IBW event detector comprises address comparators which compare the current program counter value with a single programmable address or with programmable start and end addresses defining an address range. The comparators match when the current program counter value is equal to the single address or is within the specified address range. In a processing unit capable of executing more than one process the IBW match operation can preferably be enabled/disabled on a per-process basis.

In the case of a breakpoint, when a match occurs the event detector triggers the debug exception handler of the processing unit. The instruction breakpoint occurs prior to the triggering instruction committing so that the sideeffects of the triggering instruction are voided. In the case of a watchpoint the event detector may trigger further circuitry to generate an instruction trace message for output from the processing unit, for example via a debug link 7 connecting the processing unit to a debug adaptor 4 as shown in Fig. 1.

A DBW event detector is constituted in generally the same way as an IBW event detector except that in place of instruction addresses data addresses are compared by the comparators. The DBW comparators match when an executing instruction performs a load or store operation at a single specified address or within a specified range of addresses.

Again, the DBW match operation can preferably be enabled or disabled on a per-process basis. When a DBW match occurs the debug exception handler may be triggered in the case of a breakpoint, or further circuitry may be triggered to

generate a data trace measure for output externally of the processing unit in the case of a watchpoint.

Other event detectors are contained within or connected to relevant parts of the processing unit where the event to be detected will occur. For example event detectors for events such as cache hit and cache miss may be provided in a cache loading unit of the processing unit.

The first and second debug event detectors 12 and 14 may be included within the same processing unit or within different processing units. In the latter case the two different processing units may be part of the same processor or processor core (e. g. different processing units of a VLIW processor) or may be in different processors or processor cores of a multiprocessor system.

The Fig. 2 debugging system further comprises a debug correlation element 16. The debug correlation element 16 has a counter 18 which holds a count value 20. The first and second debug event detectors 12 and 14 are connected to the debug correlation element 16 by interconnection circuitry 22 which provides a first signal path 24 between the first debug event detector 12 and the debug correlation element 16 and a second signal path 26 between the second debug event detector 14 and the debug correlation element 16.

In the example shown in Fig. 2 itself the first signal path is used to transmit a control signal from the first debug event detector 12 to the debug correlation element 16, and the second signal path 26 is used to transmit a control signal from the debug correlation element 16 to the second debug event detector 14. Accordingly, in this example the debug correlation element receives a control signal (action control signal) from the first debug event detector 12 when that debug event detector is triggered (i. e. when it detects its preselected debug event). The counter 18 in the debug correlation element 16 is responsive to the control signal received via the first signal path 24 to change the count value 20. For example, the count value 20 may be

incremented, decremented, cleared or set to a certain value.

The possible changes in a preferred embodiment of the invention will be explained in more detail later in the present specification.

In the Fig. 2 example a control signal (result control signal) dependent on the element's count value 20 is transmitted from the debug correlation element 16 to the second debug event detector 14. For example, the result control signal may be sent to the second debug event detector 14 when the element's count value 20 is zero. The second debug event detector 14 may employ the result control signal to influence its response to its debug event.

Because both the first and second debug event detectors 12 and 14 are connected in common to the debug correlation element 16 a debug relationship is established between those two debug event detectors. As will be described later in more detail with reference to specific examples, the relationships that can be created are numerous and flexible.

For example, the second debug event detector 14 may be enabled or disabled according to one or more count value changes in the debug correlation element 16 brought about by events detected by the first debug event detector 12.

Also, in practice multiple debug event detectors and multiple debug correlation elements may be provided. Thus, more than two debug event detectors may be connected to the same debug correlation element to establish a debug relationship between those debug event detectors. More than one action control signal and/or more than one result control signal may be transmitted between the debug event detectors connected together via the debug correlation element, enabling complex relationships to be established.

Different action control signals may bring about different count-value changes. For example, a first action control signal could bring about an absolute change in the count value, i. e. a change to the same new value irrespective of the existing value. A second action control signal could bring about a relative change in the count value, i. e. a

change in which the new count value is dependent on the existing count value. An example of an absolute count value is clearing of the count value. An example of a relative count value change is incrementing of the count value. Two different debug event detectors may supply the same action control signal to the debug correlation element. Different result control signals may be used to indicate different count values of the element. For example, a first result control signal could indicate that the element has a first count value and a second result control signal could indicate that the element has a second count value.

Fig. 3 shows parts of the debug correlation element 16 in a preferred embodiment of the present invention. In Fig.

3, the debug correlation element 16 comprises a counter/modifier circuit 30 and a value register 32. The counter/modifier circuit 30 has inputs for receiving three control signals (action control signals), namely a clear signal ZERO, an increment signal INCR and a decrement signal DECR. The counter/modifier circuit 30 also has an output for outputting a control signal (result control signal) EQUALZERO. A clock signal CLOCK is also applied to a clock input of the counter/modifier circuit 30.

The counter/modifier circuit 30 includes an n-bit counter which holds a count value COUNT VALUE. n is, for example, 48 bits. The value register 32 is also an n-bit register. The counter/modifier circuit 30 also has a data input/output connected to the value register 32. COUNT VALUE can be written into the value register 32 upon request, and COUNT VALUE can be set to (seeded from) a value held in the value register 32 upon request.

The action control signals ZERO, INCR and DECR are used by the counter/modifier circuit 30 to change COUNT VALUE.

The actions brought about by these control signals are shown in Table 1 overleaf.

ZERO INCR DECR ACTION 0 0 0 no change 0 0 1 decrement value 0 1 0 increment value 0 1 1 no change 1 0 0 clear value to 0 (follow 0) 1 0 1 clear value to 0 (follow 0) 1 1 0 set value to 1 (follow 1) 1 1 1 clear value to 0 (follow 0) Table 1 When the clear control signal ZERO is activated (1) and the other control signals INCR and DECR are both inactive (0) COUNT VALUE is cleared (becomes 0). Similarly, when the increment control signal INCR is active and the other control signals ZERO and DECR are both inactive, COUNT VALUE is incremented. Also, when the decrement control signal DECR is active and the other two control signals ZERO and INCR are inactive, COUNT VALUE is decremented. In this embodiment, if the counter has reached its maximum count value (2n-1) the COUNT VALUE remains at that maximum value when an increment operation is requested (i. e. COUNT VALUE does not return to zero). Similarly, when COUNT VALUE has its minimum value (0) it remains at that value if a decrement operation is requested.

As shown in Table 1, the counter/modifier circuit 30 responds in special ways to combinations of two or more active control signals. In particular, if INCR and DECR are both active, i. e. both an increment and a decrement operation are requested at the same time, COUNT VALUE is left unchanged. If ZERO and DECR are both made active at the same time, a clear operation is performed, i. e. the ZERO

signal is given precedence. The same is true if all three signals are made active together. Finally, referring to Table 1 it can be seen that COUNT VALUE can be set to 1 as well as cleared to 0. This enables a"follow operation"to be implemented in which a result control signal follows a trigger signal generated by a debug event detector. The follow operation will be described in more detail with reference to Fig. 7.

As will be described later in more detail, the actions carried out in response to these different combinations of active control signals are chosen to permit more than one debug event detector to be connected to the same input of the counter/modifier circuit 30.

The EQUAL~ZERO result control signal is produced by the counter/modifier circuit 30 whenever COUNT VALUE is zero.

In the Fig. 3 embodiment, the counter/modifier circuit 30 holds an n-bit count value, and effectively has as many different states as there are different possible count values (2n-1). This enables a far greater number of states to be achieved than in the chain latch arrangement of EP-A- 1089184 described in the introduction, without requiring complex hardware. Because there are more than two states, useful relationships between more than two debug event detectors can easily be established. Indeed, with 2n-1 states, sequencing of up to 2n-1 events is possible.

Also, as will be explained in more detail later in the present specification, the use of a counter in the debug correlation element 16 enables a very powerful combination of counting and filtering operations to be carried out within the debug correlation element, enabling very sophisticated relationships between different debug event detectors to be established. As will also be apparent from the later description, the counter has a number of possible states which is much greater than the number of action control signals needed to bring about state changes, making it possible to achieve powerful and flexible debug

relationships without using large numbers of action control signals.

In Fig. 2, the first and second debug event detectors 12 and 14 may be included in the same processing unit. In this case, the debug correlation element 16 may be conveniently incorporated within the processing unit concerned, as part of the processing unit's processor debug unit (PDU).

However, in processor. systems having a plurality of processing units, it is also desirable to be able to establish debug relationships between debug event detectors in different processing units. Such an arrangement is shown in Fig. 4.

Fig. 4 shows a first debug event detector included in the PDU of a first processing unit 40, and a second debug event detector 14 included in the PDU of a second processing unit 42.

In this case, a debug correlation element 16 is provided in a system debug unit (SDU) 44 separate from the PDUs of the processing units 40 and 42. When the processing units 40 and 42 are formed in the same chip (e. g. SOC device) the SDU 44 is preferably also formed in the chip as well. In this way, the debug correlation element 16 can be shared by the debug event detectors in different processing units.

Next, two practical realisations of the Fig. 4 debugging system will be described with reference to Figs. 5 and 6.

In Fig. 5 a processor core 50 has a so-called clustered architecture. In this kind of architecture small groups of processing units are clustered around separate partitions of a register file. The present applicant's Opus architecture is one example of such a clustered architecture. The processing units of the different clusters may execute different instructions belonging to the same VLIW instruction packet in parallel with one another.

In Fig. 5 the processor core 50 has C+1 clusters 520 to 52c, each comprising at least one processing unit (not shown). Each cluster 52 includes a processor debug unit PDU 540 to 54c. Each PDU comprises one or more debug event detectors (not shown) each corresponding to the first and second debug event detectors 12 and 14 of Fig. 4.

The number of event detectors provided in each PDU may be different. For example, one of the clusters, such as cluster 0, may be a master cluster and the remaining clusters may be slave clusters. In such a case, the processor core may be operable selectively in scalar and VLIW modes. In the scalar mode, instructions are issued only to the master cluster and effectively it behaves as a regular microprocessor. When the processor core is in VLIW mode a packet containing at least one instruction for each cluster is issued in parallel to all clusters, and the clusters execute the issued instructions in parallel. Thus, the number of debug event detectors needed in the master cluster may be greater than the number required in each of the slave clusters.

The system debug unit SDU 44 comprises one or more debug correlation elements 160 to 16MAXcoR'Each of these debug correlation elements corresponds to the debug correlation element 16 shown in Fig. 4.

The debug correlation'elements 160 to 16MAXcoR are interconnected to the PDUs 540 to 54c of the different clusters by interconnection circuitry 22. This interconnection circuitry 22 provides each debug correlation element 160 to 16MAXCOR with an action bus 560 to 56MAXCOR and a result bus 580 to 58MAXcoR- Each action bus comprises one or more signal paths for transmitting action control signals to the debug correlation element concerned. For example, when the debug correlation elements are constituted as shown in Fig. 3, each action bus 56 comprises three signal paths for transmitting the ZERO, INCR and DECR control signals respectively.

Similarly, each result bus 58 comprises one or more signal paths for transmitting result control signals output by the corresponding debug correlation element. When the debug correlation element is constituted as shown in Fig. 3, each result bus 58 comprises a single signal path for transmitting the EQUAL~ZERO signal output by the debug correlation element.

In the Fig. 5 example it is desired to enable the PDU 54 of each cluster to have access to any of the different debug correlation elements 16 in the SDU 44. Accordingly, each PDU 540 to 54c has an action output 600 to 60MAXCOR for each debug correlation element and a result input 620 to MAXCoR for each debug correlation element. Each action output 600 to 60MAXCOR has the same set of signals as the action buses 560 to 56MMCOR. Each result input 620 to 62MAxcoR has the same set of signals as the result buses 580 to 58S CoR. For example, in the Fig. 3 example, each action output 600 to 60MAXCOR outputs the three control signals ZERO, INCR and DECR and each result input inputs the single control signal EQUALZERO.

As shown schematically in Fig. 5 all of the action outputs 600 of the different clusters are combined together by action signal combiner circuitry 640 to produce a combined set of signals to be carried to the debug correlation element 160 via the action bus 560 This combiner circuitry may be OR gate circuitry when the debug correlation element is constituted as shown in Fig. 3. Similarly, all of the action outputs 60MAXCOR of the different clusters are combined (ORed) together by action signal combiner circuitry (OR circui try) 64MAXCOR to produce a combined set of signals to be transmitted to the debug correlation element 116MAXCOR by the action bus 56MAXoR- It will be appreciated that each set of OR circuitry 64 ORs the respective ZERO signals of all the clusters to form a combined ZERO signal on the action bus, and separately ORs the respective INCR signals of all the clusters to form a combined INCR signal on the action bus, and separately ORs

the respective DECR signals of all the clusters to form a combined DECR signal on the action bus.

The result bus 580 to 58mucor for each debug correlation element is simply connected directly to the C+l corresponding result inputs 620 to 62ncoR of all the different clusters.

It will be appreciated that, in Fig. 5, the amount of interconnect required within the processor core 50 itself and between the processor core 50 and the SDU 44 is relatively small. For example, when the debug correlation elements 116 are constituted as shown in Fig. 3, there are {4 (C+1) (MAXCOR +1)} signal paths in total, and {3 (MAXCOR + 1) (C+1)} -input OR gates. Between the processor core 50 and the SDU 44 there are only {4 (MAXCOR + 1)) signal paths in total.

To keep the amount of interconnect desirably small, it is of course desirable to limit the number of different types of control signal which need to be input to and output from the debug correlation elements to establish the desired debug relationship between different debug event detectors.

It is therefore highly advantageous to design the control signals, especially the action control signals, of the debug correlation elements so that as many different operations as possible can be selected using the minimum number of control signals. For example, with a set of i action control signals i. e. an i-bit action bus, the maximum number of different operations that can be selected is 2l.

However, it will be seen that in Table 1 above, some of the control signal combinations result in the same operation being selected, for example"no change"is selected by two different combinations and a clear operation is selected by three different combinations. As this shows, in practice it may be desirable to limit the available number of operations to less than the maximum number that are theoretically available (2i), bearing in mind the desirability of being able to combine action control signals generated by different PDUs using simple circuitry such as the OR gate

circuitry 64 shown in Fig. 5. For example, if two different debug event detectors in different respective clusters are linked via OR gate circuitry 64 to the same action bus 56, it can be seen from Table 1 that each debug event detector sharing the same action bus will obtain the same operation as it would have done had it been connected exclusively to the debug correlation element involved, provided that any other debug event detector sharing the same action bus is requesting"no operation".

Even if more than one debug event detector sharing the same action bus requests an operation at the same, Table 1 shows that sensible outcomes will still result. For example, if one debug event detector requests an increment operation at the same time. as another debug event detector requests a decrement operation, the result is"no operation". Similarly, the clear operation (an absolute count value change) is given precedence over the increment/decrement operation (a relative count value change) when either the zero and decrement operations are requested at the same time or the zero, increment and decrement operations are requested at the same time.

By making it possible for two or more debug event detectors to share the same action bus the interconnect circuitry 22 provided between the processing units and the system debug unit does not need to have a request/grant mechanism, so reducing the complexity and cost of the circuitry and increasing its speed of operation.

Fig. 6 shows a second example of the implementation of the Fig. 4 debugging system for a processor system having a plurality of processor cores 700 to 70R. Each processor core 70 may include one or more processing units, and the number of processing units in the different cores may be different.

The processor cores may, for example, be VLIW processor cores, and/or have a clustered architecture such as the processor core 50 in Fig. 5.

In this case, each processor core 70 has a PDU 54 similar to the PDU 54 in Fig. 5. The interconnect circuitry

22 used to connect the PDUs in the processor cores 700 to 70R to the SDU 44 is basically the same as in Fig. 5, except that all the elements are now outside the processor cores 70. Otherwise, the operation and advantages obtained are the same as in Fig. 5.

Fig. 7 shows a first example of the constitution of one of the PDUs 54 in Fig. 5 or Fig. 6. In the case of Fig. 5, the Fig. 7 circuitry is provided per cluster 52, whereas in Fig. 6 the Fig. 7 circuitry is provided per processor core 70.

In the description with reference to Fig. 7, it will be assumed for the purposes of explanation that the debug correlation elements are of the form described above with reference to Fig. 3, so that each action bus 56 comprises three signal paths for transmitting the ZERO, INCR and DECR signals respectively, and each result bus 58 comprises a single signal path for transmitting the EQUAL~ZERO control signal. Those skilled in the art will readily be able to modify the described circuitry to deal with debug correlation elements using control signals other than these four signals.

The Fig. 7 circuitry comprises a plurality of event detectors 800 to SOa, of which only the detector 800 is shown in Fig. 7. Each of these debug event detectors is used to detect one or more preselected debug events occurring in the cluster 52 or processor core 70 to which the PDU 54 belongs.

For example, these events may include instruction breakpoints or watchpoints (IBWs), data breakpoints or watchpoints (DBWs), branch trace messaging (BTM) events and CPU events (CEDs). The types of events that can be detected by each event detector 80 are not limited in this invention.

Each debug event detector 80 has a trigger input TRIGGERIN and a filter input FILTERN, and a trigger output TRIGGEROUT.

The PDU 54 in this example further comprises a filter register 82, an action register 84, a demultiplexer 86 and a multiplexer 88. These elements are provided for the event

detector 800. The same elements are provided for each further event detector 801 to BOD- The filter register 82 has an ID field 90 and a FILTEROP field 92. The ID field 90 stores an ID value identifying one of the debug correlation elements 160 to 16MAXCOR in the SDU 44. This stored ID value is applied to a selection input of the demultiplexer 86. The demultiplexer 86 has (MAXCORt1) signal inputs connected respectively to the result inputs 620 to 62MAXCOR in Fig. 5/6. The demultiplexer 86 also has a single signal output connected to the TRIGGERIN input of the debug event detector 800.

Thus, the demultiplexer 86 selects one of the result inputs 62o to 62MAXCOR according to the debug correlation element ID held in the ID field 90 and connects that selected result input to the TRIGGERIN input of the debug event detector 80o. In this way a signal path corresponding to the second signal path 26 shown in Fig. 4 is established between a selected one of the debug correlation elements in the SDU 44 and the debug event detector 800. This signal path delivers the result control signal EQUALZERO to the debug event detector 80o.

The FILTEROP field 92 of the filter register 82 is a two-bit field which stores a FILTEROP value defining the type of filter operation (if any) associated with the selected debug correlation element. The FILTEROP value is applied to the FILTERN input of the debug event detector 800.

When the FILTEROP value is"00"or"01"this indicates that the debug event detector should ignore the TRIGGER~IN input during operation. In other words, in this case the debug event detector 800 operates as normal without taking account of any debug relationship with another debug event detector. Incidentally, even in normal use a debug event detector may simply be disabled so that it never triggers even when the event that it is intended to detect occurs.

When the FILTEROP value is"10"the debug event detector 800 should trigger only if its TRIGGER~IN input is

inactive i. e. in this example when the count value held by the selected debug correlation element 16 is not equal to zero. When the FILTEROP value is"11"the debug event detector 800 should trigger only when the TRIGGER~IN input is active, i. e. in this example when the count value held in the selected debug correlation element 16 is equal to zero.

When the FILTERN input has the value "10" or "11" the debug event detector 800 takes the EQUALZERO signal into account in its response to detection of its preselected debug event. The event detector is only triggered in response to the detected event if the EQUALZERO signal meets the appropriate filtering condition defined by the FILTEROP value. In this way, the selected debug element can establish a debug relationship involving filtering, i. e. the debug events being detected by one debug event detector can be filtered based on the state (count value) of the debug correlation element 16 set by one or more other debug event detectors. Because that debug correlation element 16 can be changed in state by one or'more other debug event detectors and/or by debugger software forming part of the debug tool (e. g. the debugger software 6 running on the host computer 5 in Fig. 1) the filtering possibilities are very flexible and powerful.

The action register 84 also has two fields, namely an ID field 94 and an ACTION field 96. The ID field stores an ID value identifying one of the debug correlation elements in the SDU 44 to which the debug event detector 800 is to supply one or more action control signals when it triggers.

In this embodiment, this ID value may be the same as or different from the ID value held in the filter register 82.

The ID value held in the field 94 is applied to a selection input of the multiplexer 88. The ACTION field 96 of the action register 84 is a two-bit field which stores an ACTION value defining which of its possible operations the selected debug correlation element 16 is to carry out when the debug event detector 800 triggers. The four possible operations in Fig. 3 are an increment operation, a decrement operation, a

clear operation and a follow operation. When the ACTION value is"00"the increment operation is specified. When the ACTION value is "01" the decrement operation is specified. When the ACTION value is"10"the clear operation is specified. When the ACTION value is"11"the follow operation is specified.

The multiplexer 88 has (MAXCOR+1) signal outputs which are connected respectively to the action outputs 600 to 60MAXCOR of the PDU 54. The multiplexer 88 selects one of the result outputs 600 to 60MAXCOR according to the ID value held in the ID field 94. In this way, a signal path corresponding to the first signal path 24 in Fig. 4 is provided between the debug event detector 800 and the selected debug correlation element.

The multiplexer 88 contains a decoder circuit (not shown) which receives by a TRIGGERED signal produced at the TRIGGEROUT output of the debug event detector 800. The TRIGGERED signal is set to 1 when the detector is triggered, and is otherwise 0. The decoder circuit also receives the ACTION value held in the action field 96 and decodes the received value and the TRIGGERERD signal to produce a set of the ZERO, INCR and DECR control signals needed to bring about the operation specified by the ACTION value and the TRIGGERED signal. For example, when the increment operation is specified the decoder sets ZERO to 0, INCR to 1 and DECR to 0. When the TRIGGERED signal is 0 and the ACTION value is"00","01", or"10"the decoder circuit sets each of the ZERO, INCR and DECR signals to 0. In the case of the follow operation (ACTION value ="il"), the decoder circuit also takes the TRIGGERED signal into account in setting the ZERO, INCR and DECR control signals. In particular, if the TRIGGERED signal is 0 the decoder circuit sets ZERO to 1 and INCR and DECR to 0. IF the TRIGGERED signal is 1 the decoder circuit sets ZERO and INCR to 1 and DECR to 0. The operation of the decoder circuit can be understood from Table 1.

In Fig. 7, the elements 82,84, 86 and 88 are provided per debug event detector 80. Accordingly, each debug event detector can modify any selected debug correlation element, independently of the selections made by other debug event detectors in the same PDU 54. Similarly, each debug event detector can be influenced by any selected debug correlation element, independently of the selections made by other debug event detectors in the same PDU 54.

Although this kind of flexibility may be needed in some processor systems to be debugged, in many systems more limited flexibility may be sufficient. For example, it may be adequate in some situations to provide for some or all of the different debug event detectors within the same PDU 54 to always select the same debug correlation element to receive results from and/or to provide actions to.

Similarly, the filter operations and/or action operations may be made common for some or all debug event detectors within the same PDU. By reducing the flexibility in this way the complexity of the circuitry needed within the PDU can be simplified, saving costs.

Fig. 8 shows a second example of the implementation of the PDU 54 in Figs. 5 and 6. In this example, all debug event detectors 800 to 80D within the same PDU 54 use a single selectable correlation element 16 which both supplies an EQUALZERO result signal to all the debug event detectors in common and carries out actions (operations) when any of the debug event detectors is triggered.

Referring to Fig. 8, in this case the action registers 84 of Fig. 7 are omitted and a single demultiplexer 86 and a single multiplexer 88 are provided in common for all the debug event detectors of the PDU 54. The same debug correlation element, specified by the ID value in the ID field 90 of the filter register 82, is selected by both the demultiplexer 86 and the multiplexer 88. The EQUAL~ZERO result signal output by the selected debug correlation element 16 is supplied in common to the respective TRIGGERIN inputs of all of the debug event detectors 800 to

80D. Also, the same FILTEROP value, as held in the FILTEROP field 92 of the filter register 82, is supplied in common to the respective FILTERN inputs of all of the debug event detectors 800 to 8 aD, Each debug event detector 80 in this example has a set of control registers 98 including a FILTER~ENABLE field 100 and ACTION field 102. The FILTER ENABLE field is a one-bit field which stores a FILTERENABLE flag which specifies whether or not its particular debug event detector 80 should carry out any filtering operation based on the EQUALZERO signal. When the FILTER~ENABLE flag is 0 the debug event

detector 80 does not take account of the EQUALZERO signal applied thereto dhen an event is detected, and operates normally. However, when the FILTERENABLE flag is 1 the debug event detector 80 takes account of the EQUALZERO signal applied thereto when determining how to respond to a detected event. As in the Fig. 7 example, the response in this case is dependent on the type of filtering operation specified in the FILTEROP field 92. When the FILTEROP value is"10"the debug event detector 80 triggers when the EQUAL~ZERO signal is inactive, whereas when the FILTEROP value is "11" the debug event detector triggers when the EQUAL~ZERO signal is active. Incidentally, because each debug event detector in Fig. 8 includes its own individually-controllable FILTERENABLE flag it is not necessary for the FILTEROP field 92 to store a two-bit value as in Fig. 7. The FILTEROP field 92 could be a single-bit field to determine the type of filtering operation to be performed.

The ACTION field 102 within the set of registers 98 of each debug event detector is a two-bit field similar to the ACTION field in the action register 84 of Fig. 7. This stores an individually-controllable ACTION value for the debug event detector concerned.

When a debug event detector is triggered the ACTION value held in the action field 102 is output via an ACTIONOUT output of the detector. The respective

ACTION OUT outputs of the debug event detectors within the PDU 54 are combined appropriately in a combiner circuit 104.

If a single debug event detector 80 is triggered the combiner circuit 104 supplies the ACTION value output by that single event detector to the signal input of the multiplexer 88. If two or more debug event detectors are triggered at the same time, the combiner circuit 104 examines the different ACTION values of the triggered debug event detectors and determines what operation (if any) should be selected. In this case, it supplies to the signal input of the multiplexer 88 a combined ACTION value appropriate for the determined operation. The multiplexer 88 decodes the ACTION value received at its signal input and outputs a set of the control signals ZERO, INCR and DECR corresponding to the received ACTION value. This set of control signals is supplied to the action output 60 specified by the ID value in the filter register 82.

In the Fig. 8 example, each debug event detector 800 to 80D has its own ACTION field 102, enabling a different operation to be specified by each different detector.

However, it would also be possible to use a single ACTION field for all the different detectors. In this case, in place of the ACTION field 102 within the set of registers 98 in each debug event detector 80, a single-bit APPLY field could be provided. This APPLY field stores a APPLY flag specifying whether or not the commonly-specified operation (as specified in the single ACTION field) should be applied when the detector concerned is triggered. Each debug event detector 80 then has a TRIGGEROUT output as in Fig. 7 at which it outputs the APPLY flag when triggered. These APPLY flags are ORed together to form a TRIGGERED signal for application to the multiplexer 88, in a similar way to that shown in Fig. 7.

In Figs. 7 and 8 all of the event detectors can access any selected one of the debug correlation elements 160 to 16MRXCOR. However, it may be sufficient to tie at least some of the event detectors to particular ones of the debug

correlation elements. For example, if the event detectors 800 to 803 are IBW event detectors, these detectors could be tied respectively to the debug correlation elements 160 to 163, with other event detectors such as DBW event detectors still having flexible access to all the debug correlation elements. This can enable some of the filter-register ID fields 90, demultiplexers 86 and multiplexers 88 to be omitted.

Referring back to Fig. 3, it was mentioned earlier that the debug correlation element has a VALUE register 32 which can be used to read the count value held in the counter/modifier circuit 30 or to"seed"the count value with a value pre-wricten in the VALUE register 32. If two or more debug correlation elements are being used to count different events (e. g."paired"events such as cache hits versus cache misses) there may also be a requirement to read and/or seed the count values of the two or more different debug correlation elements in a time-coherent manner.

Heretofore this has been problematic to achieve.

In prior debugging systems, two basic methods have been used to read count values of events. The first method is to interrupt the processor core being debugged and to arrange for it to execute special code to read out the or each required count value. This special code executes in a mode which does not result in the count values being updated further, so the count values can be read individually as required. This method is, however, intrusive, as the processor core that is being debugged must have its execution halted whilst the special code executes.

The second method is to read the or each count value via the debug link 7 using the debug adaptor 4 (Fig. 1).

This does not require the processor core to be interrupted and so its execution is not disturbed. However, only a single count value can be read in a single debug-link operation and so"paired"information will not contain count values that are time-coherent.

A further problem is that, in general, for performance monitoring purposes it is desirable for the count values to have a large number of bits (e. g. 48 bits) to allow the gathering of large samples. However, whether the first or second method of reading the count values described above is used, the normal width of the memory path may be insufficient to enable the entire count value to be read in one operation. For example, only 8,16 or 32-bit reads and writes may be available from the processor core's instructions in the first method or on the debug link 7 in the second method. This means that it will be necessary to perform two or more read or write operations when reading or seeding a particular count value. This can result in an incorrect value being read or written if the counter is still counting whilst the read or write operation is in progress.

To overcome these problems, it is possible to modify the Fig. 3 debug correlation element to have the construction shown in Fig. 9. In Fig. 9, a debug correlation element 216 includes a counter/modifier circuit 30 and a value register 32 as described previously with reference to Fig. 3. Interposed between the counter/modifier circuit 30 and the value register 32 are a read latch 220 and a write latch 222. Each of the latches 220 and 222 has the same number of bits as the count value and the value register 32. The read latch 220 has a data input coupled to the counter/modifier circuit 30 for receiving the count value held thereby. The read latch 220 also has a data output coupled to the value register 32 for supplying a latched count value to the value register 32.

The write latch 222 has a data input coupled to the value register 32 for receiving a seed value prewritten in the value register 32. The write latch 222 also has a data output coupled to the counter/modifier circuit 30 for supplying thereto a latched seed value.

The read latch has a clock input connected to a read bus 232 for receiving a read signal, and the write latch 222

has a clock input connected to a write bus 234 for receiving a write signal.

The read bus 232 and write bus 234 originate elsewhere in the SOU 44 and are provided in common for all of the debug correlation elements within the SDU.

The SDU further comprises a VALUEOP register 224 and gate circuitry including gates 226 and 228. The read bus is connected to the output of the gate 228 and the write bus is connected to the output of the gate 226.

The VALUEOP register is a 2-bit register. This register can be written to, either by the processor core being debugged or by the debug tool via the debug link, to bring about simultaneous reading or seeding of the comet values of all debug correlation elements 216 connected to the read and write buses.

Assume that initially the value held in the VALUEOP register is"00"or"01". If the value"10"is then written into the VALUEOP register 224 the output of the gate 226 changes from 0 to 1, causing the write signal on the write bus 234 to become active. In response to this, the write latch 222 latches a seed value pre-written into the value register 32 by the processor core being debugged or by the debug tool and supplies the latched seed value to the counter/modifier circuit 30. In this way, the count value becomes equal to the seed value. The same seeding operation is carried out simultaneously in all other debug correlation elements connected to the write bus 234, enabling desired seed values to be applied simultaneously to the counter/modifier circuits 30 of those different debug correlation elements.

Writing of the seed values into the value registers 32 is carried out before the simultaneous seeding takes place, so it does not matter if the memory path widths available to the processor core being debugged or the debug tool (as the case may be) are smaller than the widths of the value registers, nor does it matter that the value registers of different elements must be seeded one after another. As

long as the seed values have all been written into the value registers prior to the change in the VALUEOP register 224 to "10"all count values can be seeded simultaneously. This is extremely useful if the debugging system is trying to collect paired information such as cache hits and cache misses, since the counting of both events can be initiated precisely simultaneously.

When the VALUEOP register is changed from"00"or"01" to"11"the output of the gate 228 changes from 0 to 1, causing the read signal on the read bus 232 to become active. This causes the read latches 220 in all debug correlation elements connected to the read bus 232 to latch simultaneously the respective count values held in the counter/modifier circuits 30 of their own elements. The latched count values are therefore available in the value registers 32 for subsequent reading by the processor core being debugged or the debug tool as the case may be. Again, it does not matter if the memory-path width available for reading the count values from the values registers is smaller than the width of the count values, since each count value has been latched by the read latch 220. Thus, the latched count value can be read in two or more individual read operations and/or the count values of several different debug correlation elements 216 can be read one after another, with time-coherence between the read values being guaranteed.

As described above, a debugging system embodying the present invention can facilitate complex filtering and other functions such as counting at a reasonable hardware/interconnect cost. The filtering facilities provided enable less intrusive debugging and therefore improve the debugging process as a whole. Such improvements in the debugging process assist end-users of the processing system to achieve shorter times-to-market. Furthermore, the debugging system is simple to configure (program) and to present as a"user model"in the debug tool (e. g. debugger software running on the host computer 5 in Fig. 1). The

registers such as the VALUE register 32, the filter register 82, the action register 84, and the relevant fields of the set of registers 98 may be memory-mapped registers for ease of programming.

The powerful and flexible facilities provided by a debugging system embodying the present invention will now be illustrated with reference to several examples.

In the first example, shown in Fig. 10, three debug event detectors 80x, 80y and 8z are connected to a debug correlation element 16 to establish a debug relationship between them. In this example, the event detector 80x is a CPU event detector (CED). Each time a particular CPU event is detected by the detector 80x it activates the INCR signal for the debug correlation element 16, so that the element counts the number of occurrences of the particular CPU event. The event detector 80y is an instruction breakpoint/watchpoint (IBW) which, via OR gate circuitry 64, causes the ZERO signal of the debug correlation element 16 to be activated when an instruction within a specific instruction address range is executed. The event detector 80z is a data breakpoint/watchpoint (DBW) which, via OR gate circuitry 64, also causes the ZERO signal to become active when a memory location within a specific address range has been accessed. Thus, the zeroing of the count value in this example is made dependent on either of two further events other than the event being counted.

It will be appreciated that the connections shown in Fig. 10 are only schematic. In practice, if this example were implemented in the Fig. 5 or 6 system each of the debug event detectors 80x, 80y and 80z would be configured to select the same debug correlation element in the SDU 44, and they would share the same action bus 56.

Fig. 11 shows a second example of a debug relationship between two debug event detectors 80x and 80y which in this

case are both DBWs. In this example, the debug relationship involves filtering. The detector 80x is configured to supply the DECR signal to the debug correlation element 16. The

detector 80y is configured to receive the EQUAL~ZERO signal from the element 16. The detector 80y is also configured, as explained above with reference to Figs. 7 and 8, to trigger only when the received EQUAL ZERO is active (i. e. the count value held in the element 16 is equal to zero).

Initially, the count value in the element 16 is seeded with the value N by the debugger software in the debug tool (or by software running on the processor core to be debugged). After this seeding of the element, the count value is decremented each time the detector 80x is triggered, i. e. each time a memory access occurs within the specific memory address range set in the DBW of detector box. Until N such accesses have taken pi. ice, the EQUALZERO signal remains inactive so that the DBW of the detector 80y does not trigger. Only when N accesses have been detected by the DBW in detector 80x is the detector 80y enabled.

The element 16 in Fig. 11 may also be configured to have its count value modified by any number of other event

detectors apart from the detector 80x, so that the N events may be a complex mixture of different IBW/DBW/BTM/CED events.

Fig. 12 shows a third example in which the debug relationship also involves filtering. Initially, the debug correlation element 16 is seeded by the debugger software with the value 1. An event detector 80z is configured to respond to the element's EQUALZERO signal. The detector 80z is a DBW so that, when triggered in response to a memory access within a specified address range, it raises a debug exception (breakpoint) or generates trace information (watchpoint). The detector 80z is configured so that its triggering is enabled only when the EQUAL~ZERO signal is active, i. e. the element 16 has its count value equal to zero.

The DECR signal for the element 16 is supplied by either of two further event detectors 80 and 80y which, in this example, are an IBW and a DBW respectively. For example, the IBW may be set to detect execution of line 42

of code foo. c, and the DBW may be set to detect writing of data to variable"munge"which is located at the address Am in memory. Thus, when either of these two events occurs, the count value is decremented to zero, enabling subsequent triggering of the DBW of detector 80z.

Again, in this example, further event detectors other than the detectors 80x and 80y may be configured to influence the count value of the element 16, enabling the events resulting in the enabling of the detector 80z to be expanded.

Fig. 13 shows a fourth example in which the debug relationship also involves filtering. In this case the relationship is similar to that of Fig. 12, except that the count value is initially seeded by the debugger software with the value zero, and either of the debug event detectors 8 Ox and 80y can increment the count value by activating the

INCR signal of the element. The DBW of detector 80z is enabled whilst EQUALZERO is active (the count value is 0) but is disabled as soon as an event is detected by either of the detectors 80x and 80y. Again, further IBW/DBW/BTM/CED detectors other than the detectors 80x and 80y can be used to influence the count value of the element 16 to enable more complicated relationships to be established.

Finally, Fig. 14 shows a fifth example involving a follow operation. The detector 80y is configured so that it only triggers when EQUALZERO is inactive, i. e. the count value in the element 16 is not equal to zero. The element 16 is initially seeded by the debugger software with the value zero. Accordingly, initially the detector 80y is disabled.

The detector 80x, for example an IBW, is configured to bring about the follow operation in the element 16 when triggered. If the IBW is triggered, the count value of the element 16 is set to 1, but otherwise the count value is set to 0, on a cycle-by-cycle basis. Thus, the DBW of detector 80y is only enabled in any cycle if the IBW triggers. This function-specific filtering is usable, for example, in situations in which a debug exception should only be raised

by the DBW if a particular instruction specified by the IBW has actually been executed. Without the"follow"facility the DBW would raise the debug exception every time the particular memory location the subject of the DBW is accessed, potentially causing a significant number of unwanted exceptions.

In the five examples described with reference to Figs.

10 to 14 the event detectors may be within the same processing unit or be in different processing units. In the latter case, very sophisticated filtering facilities are available between different processing units, for example between different clusters or different processor cores.

Referring to Figs. 5 and C it can be seen that processor circuitry embodying the present invention separates the or each PDU from the SOU by interconnection circuitry such as the action and result buses 56 and 58.

This is in contrast to conventional processing circuitry which has tended to have"closely-coupled"PDUs and SDUs with no clear division between them. There are some situations in which it may be desirable to be able to omit the SDU from production devices, for example because the SDU could be used by hackers/counterfeiters to obtain access to restricted information contained within the device or for reducing the amount of circuitry included in the production devices. In the closely-coupled conventional processor circuitry the omission of the SDU is not readily achievable.

In processor circuitry embodying the present invention, on the other hand, omission of the SDU from production devices is possible. In this case, omission of parts of the interconnection circuitry (22 in Figs. 5 and 6) outside each processing unit is also possible. For example, in Fig. 5 the buses 56 and 58 outside the processor core 50 could be omitted. In Fig. 6, as well as the buses 56 and 58, the other parts of the interconnection circuitry 22 linking the buses 56 and 58 to the action outputs 60 and result inputs 62 of the PDUs 54 could also be omitted.

Each PDU 54 in the production device may still be constituted as in Fig. 7 or 8, i. e. with the functionality to connect a debug event detector to a selected one of the PDU's result inputs 620 to 62MAXCOR and/or to a selected one of the PDU's action outputs 600 to SOMxcon. Because the SDU is not present in the production device, the debug event detector, although present, will be disabled. Additionally,

the FILTEROP value applied to the FILTERN input of the debug event detector may be set to "00" or "01" so that the detector is not affected by any signal applied to the TRIGGERIN input. Similarly, the event detectors will not be triggered in production devices, so the TRIGGER~OUT output in Fig. 7 and the ACTION~OUT output in Fig. 8 will not become activated.

Thus, a production device embodying a further aspect of the present invention comprises one or more processing units and a PDU corresponding to one of the processing units. The processing unit includes a debug event detector operable to detect when a preselected debug event occurs in its corresponding processing unit.

In one embodiment, the PDU has a plurality of action outputs and includes action signal generation circuitry connected with the debug event detector and the plurality of action outputs and operable to generate an action signal when the debug event detector detects the preselected debug event. The action signal generation circuitry is operable to supply the generated action signal to a selected one of the plurality of action outputs. In Fig. 7 the action signal generation circuitry comprises the action register 84 and the multiplexer 88. In Fig. 8 the action signal generation circuitry comprises the control register 98, combiner circuitry 104 and the multiplexer 88.

In another embodiment the PDU has a plurality of result inputs, each for receiving a result signal, and includes result signal supply circuitry. The result signal supply circuitry is connected to the plurality of result inputs and to the debug event detector. The result signal supply

circuitry is operable to supply the result signal received at a selected one of the result inputs, or a signal derived therefrom, to the debug event detector. The debug event detector is operable to respond to the preselected debug event in dependence upon the supplied signal. In Fig. 7 and 8 the result signal supply circuitry comprises the filter register 82 and demuliplexer 86.

To enable debugging of programs for production devices omitting the debug correlation elements, it is of course necessary to produce test devices including one or more debug correlation elements (e. g. in the SDU) and suitable interconnection circuitry for connecting the debug correlation elements to the processing unit or units. Such a test device can be employed in a method of debugging a program embodying another aspect of the present invention.

That method comprises using the interconnection circuitry to provide a first signal path between a first debug event detector and a debug correlation element and to provide a second signal path between a second debug event detector and the same debug correlation element. Each of the signal paths serves to transmit at least one control signal to/from the debug correlation element so as to establish a debug relationship between the first and second debug event detectors. The method also comprises using the first and second debug event detectors having the established debug relationship to debug the program. For example, a programmer may use debug information produced by one of the debug event detectors to modify or correct the program.

Processor circuitry embodying the present invention may be included in a highly-integrated"system-on-a-chip" (SOC) for use in multimedia applications, network routers, video mobile phones, intelligent automobiles, digital television, voice recognition, 3-D games, etc.

Claims

CLAIMS :

1. Processor circuitry comprising: one or more processing units; at least first and second debug event detectors, each for detecting when a preselected debug event occurs in one of said processing units; a debug correlation element comprising a counter for holding a count value; and interconnection means for providing a first signal path between said first debug event detector and said debug correlation element and a second signal path between said second debug event detector and said debug correlation element, each said signal path serving to transmit at least one control signal to/from said debug correlation element so as to establish a debug relationship between said first and second debug event detectors.

2. Processor circuitry as claimed in claim 1, wherein said debug correlation element is external to each of said one or more processing units.

3. Processor circuitry as claimed in claim 1 or 2, wherein said first and second debug event detectors are included in first and second processing units respectively.

4. Processor circuitry as claimed in claim 3, having a clustered configuration comprising a plurality of clusters, wherein each said cluster includes one or more processing units and said first and second processing units belong to different respective clusters.

5. Processor circuitry as claimed in any one of claim 3, comprising a plurality of processor cores, wherein said first and second processing units belong to different respective processor cores.

6. Processor circuitry as claimed in claim 1, wherein said first and second debug event detectors and said debug correlation element are included in the or one said processing unit.

7. Processor circuitry as claimed in any preceding claim, wherein one said control signal is an action control

signal transmitted from one of said debug event detectors to said debug correlation element, and said debug correlation element has count value changing means for changing said count value in response to said action control signal.

8. Processor circuitry as claimed in claim 7, wherein the count value changing means are operable to bring about more than one different count value change in said debug correlation element in response to the same action control signal.

9. Processor circuitry as claimed in claim 7 or 8, wherein said debug correlation element receives two or more such action control signals and said count value changing means are operable to bring about different respective count value changes in response to said two or more action control signals.

10. Processor circuitry as claimed in claim 9, wherein said count value changing means are operable to bring about an absolute count value change in response to one said action control signal and to bring about a relative count value change in response to another said action control signal.

11. Processor circuitry as claimed in any one of claims 7 to 10, wherein said debug correlation element receives such action control signals from at least two different debug event detectors.

12. Processor circuitry as claimed in any one of claims 7 to 11, wherein a total number of count value changes that said count value changing means are operable to bring about is greater than a total number of such action control signals received by said debug correlation element.

13. Processor circuitry as claimed in any preceding claim, wherein one said control signal is a result control signal transmitted from said debug correlation element to one of said debug event detectors, and said debug correlation element is operable to generate said result control signal in dependence upon its said count value.

14. Processor circuitry as claimed in claim 13, wherein the debug event detector that receives said result control signal is operable to employ that signal to influence its response to said preselected debug event.

15. Processor circuitry as claimed in any preceding claim, wherein said debug correlation element receives at least two such action control signals and comprises operation selection means operable, in dependence upon the received action control signals, to select one of a plurality of available count value changing operations to be carried out in the debug correlation element in response to the action control signals.

16. Processor circuitry as claimed in claim 15, wherein said operation selection means are operable, when two or more of the received action control signals are activated simultaneously, to select a single appropriate one of said available count value changing operations.

17. Processor circuitry as claimed in claim 15 or 16, wherein one said action control signal is a zero signal, and said debug correlation element is operable to set said count value to zero in response to said zero signal.

18. Processor circuitry as claimed in claim 15,16 or 17, wherein one said action control signal is an increment signal, and said debug correlation element is operable to increment said count value in response to said increment signal.

19. Processor circuitry as claimed in any one of claims 15 to 18, wherein one said action control signal is a decrement signal, and said'debug correlation element is operable to decrement said count value in response to said decrement signal.

20. Processor circuitry as claimed in any one of claims 15 to 19, wherein one of said available count value changing operations is a set operation in which said count value is changed to a predetermined value other than zero.

21. Processor circuitry as claimed in any preceding claim, wherein:

at least one said debug event detector has follow operation control means operable to set one or a set of action control signals output by that debug event detector to a first value or a first set of values when its preselected debug event is detected and to set that one or that set of action control signals to a second value or a second set of values when that event is not detected; and said count value changing means are responsive to said first value or said first set of values to set said count value to a first follow value and are responsive to said second value or said second set of values to set said count value to a second follow value.

22. Processor circuitry as claimed in claim 21, wherein said first and second follow values are such that a result control signal output by said debug correlation element indicates whether or not said preselected debug event is detected by the debug event detector.

23. Processor circuitry as claimed in any preceding claim, wherein said interconnection means are operable to employ a common signal path to provide a portion of each of said first and second signal paths.

24. Processor circuitry as claimed in any preceding claim, wherein said interconnection means provide said debug correlation element with an action bus for transmitting the or each action control signal to the debug correlation element, and further comprise action signal combiner means operable to connect to the action bus the or each debug event detector that is to transmit such an action control signal to that debug correlation element.

25. Processor circuitry as claimed in any preceding claim, wherein said interconnection means provide said debug correlation element with a result bus for transmitting the or each result control signal to the debug correlation element, and further comprise result connection means for connecting to said result bus the or each said debug event detector that is to receive such a result control signal from said debug correlation element.

26. Processor circuitry as claimed in any preceding claim, comprising a plurality of such debug correlation elements, wherein said interconnection means are operable, for at least one said debug event detector, to select one of said debug correlation elements from amongst said plurality of debug correlation elements and to provide a signal path between that debug event detector and the selected debug correlation element for transmitting a control signal therebetween.

27. Processor circuitry as claimed in claim 26, wherein said interconnection means are operable, for said at least one debug event detector, to select first and second different debug correlation elements from amongst said plurality of debug correlation elements, and to provide one signal path between the debug event detector and the selected first debug correlation element for transmitting a control signal from the debug event detector to the first debug correlation element, and to provide another signal path between the debug event detector and the selected second debug correlation element for transmitting a control signal from the second debug correlation element to the debug event detector.

28. Processor circuitry as claimed in claim 26 or 27, wherein said interconnection means select the same debug correlation element for a set of two or more debug event detectors.

29. Processor circuitry as claimed in any preceding claim, wherein said debug correlation element comprises seeding means for seeding said count value with a desired seed value.

30. Processor circuitry as claimed in claim 29, wherein said seeding means comprise a value register into which said seed value is pre-written, and a write latch interposed between said value register and said counter and operable, in response to a write signal, to latch the prewritten seed value and to supply the latched value to the counter as said count value.

31. Processor circuitry as claimed in claim 30, comprising a plurality of such debug correlation elements, wherein two or more of said debug correlation elements each comprise such seeding means, and the processor circuitry further comprises write signal applying means for applying said write signal substantially simultaneously to the respective write latches in those two or more correlation elements.

32. Processor circuitry as claimed in any preceding claim, wherein said debug correlation element comprises reading means for reading said count value and making it available outside said debug correlation element.

33. Processor circuitry as claimed in c'. aim 32, wherein said reading means comprises a value register accessible from outside said debug correlation element, and a read latch interposed between said counter and said value register and operable, in response to a read signal, to latch said count value and to supply the latched value to said value register.

34. Processor circuitry as claimed in claim 33, comprising a plurality of such debug correlation elements, wherein two or more of said debug correlation elements each comprise such reading means, and the processor circuitry further comprises read signal applying means for applying said read signal substantially simultaneously to the respective read latches in those two or more debug correlation elements

35. Processor circuitry as claimed in any one of claims 29 to 34, wherein a width of said count value is greater than a memory-path width of said processor circuitry, and the or each said latch has at least said count-value width.

36. A method of debugging a program for a processor using processor circuitry as claimed in any preceding claim, comprising: (a) employing said interconnection means to provide said first and second signal paths ;

(b) establishing such a debug relationship between said first and second debug event detectors; and (c) using the first and second debug event detectors having the established debug relationship to debug the program.

37. A method as claimed in claim 36, further comprising: (d) modifying the program taking account of the results in step (c).

38. Processor circuitry comprising: one or more processing units; a processor debug unit corresponding to one of said processing units; wherein said processor debug unit includes: a debug event detector for detecting when a preselected debug event occurs in said corresponding processor unit ; a plurality of action outputs; and action signal generation means connected with said debug event detector and said plurality of action outputs and operable to generate an action signal when said debug event detector detects said preselected debug event and further operable to supply the generated action signal to a selected one of said action outputs.

39. Processor circuitry comprising: one or more processing units; a processor debug unit corresponding to one of said processing units ; wherein said processor debug unit includes: a debug event detector for detecting when a preselected debug event occurs in said corresponding processing unit ; a plurality of result inputs, each for receiving a result signal; and result signal supply means connected to said plurality of result inputs of said processor debug unit and to said debug event detector and operable to supply the result signal received at a selected one of said result inputs, or a signal derived therefrom, to said debug event detector,

said debug event detector being operable to employ the supplied signal to influence its response to said preselected debug event.

40. Processor circuitry substantially as hereinbefore described with reference to any of Figs. 2 to 14 of the accompanying drawings.

41. A method of debugging a program for a processor substantially as hereinbefore described with reference to any of Figs. 2 to 14 of the accompanying drawings.