JPH11102310A - Program tracer and trace data compressing and recording method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To compress the amount of trace data by counting and recording the loop frequency of a loop process and also recording only passage address information of the instruction sequence of a final loop. SOLUTION: A head address register 5 holds the head address of the loop process of the instruction sequence of a program. A storage address register 6 holds the address of a tracer memory 1 where the head address is written. Comparing circuits 7 and 8 compare the head address with the head address of a next loop. Selectors 3, 9 and 10 switch the write address of the tracer memory 1 to the address held in the storage address register 6 when the comparing circuits 7 and 8 detect matching. When the loop process operation of a firmware instruction is decided and the same loop process is executed repeatedly, data stored in the tracer memory 1 in the 1st loop process are read out and written back to the same address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program tracer and a method for compressing and recording trace data, and more particularly to a program tracer and a method for compressing and recording trace data which efficiently collect passing address information of a running program.

[0002]

2. Description of the Related Art A program tracer collects and records information relating to the execution and operation of a program, and is used to investigate the cause of a failure when it occurs. Since the information collected by such a programmed laser is generally enormous, it is necessary to suppress the recording of information when the corresponding program is not being executed or when the passing address information has not changed. We try to record only information for as long as possible.

For example, according to Japanese Patent Application Laid-Open No. 62-11334, when tracing pass address information corresponding to a branch instruction in a program, first means for holding the pass address information corresponding to the above branch instruction And second means for holding pass address information corresponding to a branch instruction executed after the branch instruction, and comparing means for comparing pass address information held in the first and second means. And the writing of the passing address information to the trace memory is controlled based on the comparison result.

[0004]

The conventional program tracer as described above has the following problems.

The first problem is that tracing is performed in accordance with a specific condition (tracing only a branch instruction), so that it is impossible to record passing address information relating to other wide-ranging instruction sequences. That is,
The information of the branch source address and the branch destination address is recorded, but the information of the normal processing without the branch instruction is not recorded.

A second problem is that when the program enters a loop state, the passing address information corresponding to the same branch instruction is not recorded redundantly, so that the information at the time of the second or subsequent loop is not recorded. Therefore, since the number of times the loop process has been executed is not traced, sufficient information for determining the cause of the program failure cannot be obtained.

SUMMARY OF THE INVENTION It is an object of the present invention to improve the above-mentioned drawbacks, to eliminate the same repetitive information as much as possible and to record necessary and sufficient information in order to efficiently analyze the execution state of a program, and to record a necessary and sufficient information in a trace data compression recording. Is to provide a way.

[0008]

According to the present invention, there is provided a program tracer for recording pass address information of a program being executed, wherein when an instruction sequence of the program executes a loop process, the number of times of loop of the loop process is increased. Is recorded, and only the passing address information of the instruction sequence of the final loop is recorded.

A program tracer according to the present invention is a program tracer for recording pass address information of a program being executed, wherein a start address register for holding a start address of a loop process of an instruction sequence of the program; A storage address register for holding the address of the tracer memory to be written, a comparison circuit for comparing the start address with the start address of the next loop, and a write address of the tracer memory when the match is detected by the comparison circuit. A selector for switching to an address held in the storage address register.

[0010] Furthermore, the program tracer of the present invention comprises:
An adder circuit for reading out specific data already stored in the tracer memory when a match is detected by the comparison circuit and adding 1 to a counter area of the data, and selecting the data corrected by the adder circuit to select the tracer memory And a selector for writing to

In the trace data compression recording method according to the present invention, when recording the passing address information of the program being executed, when the instruction sequence of the program executes the loop processing, the number of times of the loop processing and the number of times of the loop processing can be reduced by one. This is realized by recording the passing address information for the loop and not recording the passing address information for the other loops.

That is, the program tracer according to the present invention discriminates loop processing in an instruction sequence, suppresses writing to the tracer when executing the same loop processing a plurality of times, and starts the first address of the first loop processing. Is read out, and 1 is added to the counter value in the data to perform write back. This makes it possible to determine how many times the loop processing has been executed, and to store trace data efficiently.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, a program tracer according to the present invention comprises a tracer memory 1 for storing trace data.
A trace data register 2 for temporarily storing trace data received from the outside, a tracer address register 4 for storing an address for writing trace data in the tracer memory 1, and a start address of a loop processing operation of an instruction sequence included in the trace data. , A storage address register 6 for storing the address of the tracer memory 1 for writing the start address of the loop processing operation, a comparison circuit 7 for comparing the start address register 5 with the start address of the next loop processing, 8
And selector 9 for switching the address pointing to tracer memory 1 to storage address register 6 when a match is detected.
A selector 10 for storing a value obtained by adding 1 to the value of the storage address register 6 in the tracer address register 4;
An adding circuit 1 for adding 1 to a counter value of data read from the tracer memory 1 specified by the selector 9
1 and a selector 3 for writing back the added data to the tracer memory 1.

FIG. 2 is an explanatory diagram showing the format of data stored in the tracer memory 1 described above. In the figure, for example, when tracing firmware processing, the data format stored in the tracer memory 1 counts an area for storing the address of the executed firmware instruction (program passing address) and the number of times of loop processing. And an area for storing a counter value.

Next, the operation of the program tracer will be described.

First, the address of the firmware instruction which is the data to be traced is stored in the trace data register 2.
Is stored in The trace data register 2 stores the address of the firmware instruction and a counter value (initial value is “0”) for counting the number of loops. This is the data format defined in FIG.

In the case of the firmware instruction sequence of the normal processing operation without loop processing, the data of the trace data register 2 is stored at the address of the tracer memory 1 pointed to by the tracer address register 4. Thereafter, the tracer address register 4 is selected by the selector 10, and a value obtained by adding 1 to the original value by the adding circuit 12 is stored in the tracer address register 4. With this operation, the tracer address register 4 points to the address where the next trace data is stored.

Next, the processing of the firmware instruction sequence having a loop processing is roughly divided into A and A of the normal processing operation.
(The number of instructions is n steps) and B (the number of instructions is m steps) and X (the start address is x and the number of instructions is 1 step) of the loop processing operation, and the order of the processing is AX (1st time) -X (2nd time) -X (3rd time) -X
(Fourth) -X (fifth) -B, and the value of the tracer address register 4 is "an".

First, when the execution of the firmware instruction sequence of the normal processing operation A is completed, the value of the tracer address register 4 indicates a. Thereafter, when the processing enters the loop processing operation X, the loop processing head instruction 101 becomes 1, and it is recognized that the execution of the firmware instruction (address x) at the head of the loop processing has started.

At this time, since the value has not yet been set in the start address register 5, the comparison circuit 7 becomes 0 and the comparison circuit 8 becomes 1. When the value of the comparison circuit 8 becomes 1, the value a of the tracer address register 4 is stored in the storage address register 6. Further, the address x of the firmware instruction to be stored in the tracer is stored in the head address register 5 according to the loop processing head instruction 101.

Since the comparison circuit 7 becomes 0, the selector 10
Selects the tracer address register 4 and stores the value a + 1 resulting from the addition of +1 in the tracer address register 4. When the final firmware instruction of the loop processing operation X is completed, the value of the tracer address register 4 becomes a + 1.

When the head firmware instruction of the second loop processing X is executed, the loop processing head instruction 101 becomes 1 again. Using this instruction as a trigger, the comparison circuit 7 compares the value x of the head address register 5 stored at the start of the previous loop processing operation with the address x of the current firmware instruction. As a result of the comparison, a match is detected if the processing operation is in the same loop.

When a match is detected, the selector 9 switches the address of the tracer memory from the value a + 1 of the tracer address register 4 to the value a indicated by the storage address register 6. Further, the value a of the storage address register 6 is selected by the selector 10, and the value a + 1 obtained by adding +1 is stored in the tracer address register 4. Also, the selector 9
The data of the tracer memory 1 is read from the address selected by the above, and the counter value in the data (initial value “0”)
Is added to the tracer memory 1 again by the selector 3 at the same address in the tracer memory 1.

FIG. 3 is an explanatory diagram showing an example of the above operation.
In the conventional tracer control circuit, the addresses written in the tracer memory are AX (first) -X (second) -X
(3rd) -X (4th) -X (5th) -B, but in the present invention, it is AX (5th) -B. That is, even when the loop processing operation X loops five times, only one data (one step) is written as the trace data, and the trace data can be stored efficiently.

[0026]

As described above, according to the present invention, the following effects can be obtained.

The first effect is that the loop processing operation of the firmware instruction is determined, and when the same loop processing is executed a plurality of times, the data in the tracer memory stored in the first loop processing is read out and written back to the same address. By doing so, the capacity of the trace data can be compressed. The reason is that the address of the tracer that stores the start address of the loop processing operation of the firmware instruction is stored, and when the same loop processing operation is executed again, 1 is stored.
This is because data is written back to the tracer address stored in the second loop processing.

A second effect is that by embedding a counter value for counting how many times the loop processing has been executed in the trace data, it is possible to recognize how many times the loop processing of the compressed trace data has been executed. . The reason is that when the second and subsequent loop processes are executed, the trace data stored during the first loop process is read, the counter value is incremented by +1 and rewritten.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a data format of trace data.

FIG. 3 is an explanatory diagram showing an example of a trace operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Tracer memory 2 Trace data register 3, 9, 10 Selector 4 Tracer address register 5 Start address register 6 Storage address register 7, 8 Comparison circuit 11, 12 Addition circuit

Claims (4)

[Claims] In a program tracer for recording pass address information of a program being executed, when the instruction sequence of the program executes a loop process,
A program tracer which counts and records the number of times of loop processing and records only passing address information of an instruction sequence of a final loop. 2. A program tracer for recording passing address information of a running program, comprising: a start address register for holding a start address of a loop process of an instruction sequence of the program; and a tracer memory address for writing the start address. A storage address register, a comparison circuit for comparing the start address with the start address of the next loop, and when the match is detected by the comparison circuit, the write address of the tracer memory is held in the storage address register. A program tracer comprising: a selector for switching to an address. 3. The program and laser according to claim 2, wherein, when a match is detected by said comparison circuit, an adder circuit reads out specific data already stored in a tracer memory and adds 1 to a counter area of said data; A selector for selecting data corrected by the adding circuit and writing the selected data to the tracer memory. 4. When recording pass address information of a program being executed, when an instruction sequence of the program executes a loop process, a loop count of the loop process and pass address information for one loop are recorded. A trace data compression recording method characterized by not recording pass address information for other loops.