CN100517434C - Driving unit and display apparatus having the same - Google Patents
Driving unit and display apparatus having the same Download PDFInfo
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- CN100517434C CN100517434C CNB2005101283028A CN200510128302A CN100517434C CN 100517434 C CN100517434 C CN 100517434C CN B2005101283028 A CNB2005101283028 A CN B2005101283028A CN 200510128302 A CN200510128302 A CN 200510128302A CN 100517434 C CN100517434 C CN 100517434C
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- signal
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- clock
- driving stage
- substrate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
Abstract
In a driving unit (e.g., a gate driving unit) and a flat panel display apparatus having the driving unit, a circuit portion of the driving unit includes a plurality of driving stages cascade-connected to one another and outputs a (gate) driver signal (a plurality of gate-driving signals) based on a plurality of control signals. The line portion comprises a first signal line and a second signal line, each of which transmits control signals from the outside, and a first connection line connecting the first signal line to the driving stages, and a second connection line connecting the second signal line to the driving stages. The second signal line is positioned at a different (metallization) layer from the first signal line and the first and second connection lines. Therefore, malfunctioning of the driving unit caused by corrosion may be prevented.
Description
Technical field
The present invention relates to a kind of driver element and a kind of display device, relate in particular to a kind of driver element that can prevent fault and have the display device of this driver element with this driver element.
Background technology
Usually, display device (for example, LCD) comprising: display board, this display board have many gate lines and many data lines; Gate drivers, this gate drivers is sidelong along one of display board to be put, and is used for to gate line output gate drivers signal (a plurality of signal); And data driver, this data driver is placed on the top of display board, is used for to data line output data driver signal (a plurality of data-signal).
Have the grid of " built-in (built-in) " structure and data driver and be and be assemblied in the chip on the display panel substrate or be formed on integrated circuit on the display panel substrate.When display device had built-in gate drivers, the size of the circuit relevant with driver of this display device had reduced valuably.
Gate drivers comprises: the shift register of being made up of a plurality of driving stages, transmit many signal line of various signals and many connecting lines that signal wire are electrically connected to a plurality of driving stages the shift register from the outside to gate drivers.Usually, signal wire all is formed on the layer of the layer that is different from connecting line, thereby signal wire is electrically connected on the connecting line by a plurality of contact electrodes.
Display board comprises: array base palte, this array base palte have many gate lines and many data lines that form thereon; With the corresponding pseudo-colour filtering substrate in the position of array base palte; Place the liquid crystal layer between array base palte and the pseudo-colour filtering substrate; And the sealant that array base palte and pseudo-colour filtering substrate junction are lumped together.The pseudo-colour filtering substrate comprises black matrix", and it passes the light of the uncontrollable part of liquid crystal layer in order to obstruction.Generally speaking, black matrix" comprises metal material, for example has the chromium (Cr) of 3.5 optical density, perhaps organic material, for example carbon (C).
In the display panel structure that has built-in gate drivers, at gate drivers be formed between the public electrode of the pseudo-colour filtering substrate on the black matrix" and formed stray capacitance.This stray capacitance can cause gate drivers to break down.
Recently, in order to reduce stray capacitance, between gate drivers and public electrode, insert sealant.
But, in the display panel structure that has built-in gate drivers, be formed on the black matrix" with the corresponding public electrode of gate drivers.When having than public electrode than the gate drivers of low potential and public electrode electrical short, the black matrix" that comprises chromium (Cr) is owing to the electric potential difference between public electrode and the gate drivers is corroded.Especially, when sealant between array base palte and pseudo-colour filtering substrate during misalignment, sealant is not inserted between public electrode and the gate drivers, thereby black matrix" can be corroded.Equally, when sealant being inserted between public electrode and the gate drivers because the high osmosis of sealant, gate drivers can with the public electrode electrical short.Therefore, when using sealant, the fault of gate drivers is inevitable.
Summary of the invention
Embodiments of the invention provide a kind of driver element that can prevent fault.An alternative embodiment of the invention provides a kind of display device with above-mentioned driver element.
In one aspect of the invention, driver element comprises circuit part and circuit pack.Circuit part comprises: a plurality of driving stages are used for according to a plurality of control signal output driver signals (for example, a plurality of signals).All cascades and export grid (driving) signal each other of each level of described driving stage.
Circuit pack comprises first signal wire, secondary signal line, described first signal wire is electrically connected to first connecting line of described driving stage and second connecting line that described secondary signal line is electrically connected to described driving stage.Each bar in described first and second signal wires will send driver element to from the control signal of outside.Described first signal wire and described first and second connecting lines are positioned at (for example, being formed at) (plating) layer different with described secondary signal line.
In another aspect of this invention, (for example utilize a plurality of signals, the gate drivers signal) and a plurality of data-signal (for example, the data driver signal) come the display device of display image to comprise: data driver is used to produce the data-signal that will be applied to described display board; And gate drivers, be used to produce the signal that will be applied to described display board.
Described gate drivers comprises circuit part and circuit pack.Described circuit part comprises a plurality of (grid) driving stages and exports gate drivers signal (a plurality of grids (driving) signal) according to a plurality of control signals.Each utmost point of described driving stage is cascade and export in grid (driving) signal one each other all.
Described circuit pack comprises first signal wire, secondary signal line, described first signal wire is electrically connected to first connecting line of described driving stage and second connecting line that described secondary signal line is electrically connected to described driving stage.Each bar in described first and second signal wires all will send described driver element from the control signal of (outside) to.Described first signal wire and described first and second connecting lines are positioned at (being formed at) (plating) layer different with described secondary signal line.
In another aspect of the invention, display device comprises array base palte and opposing substrates.
Described array base palte comprises first substrate, driver and pel array.Described first substrate is divided into viewing area and the external zones adjacent with described viewing area.Described driver be formed on corresponding described first substrate of described external zones on.Described pel array be formed on corresponding described first substrate in described viewing area on.Described driver output driver signal, and described pel array receives described driver signal from described driver.
Described relative substrate comprises second substrate right with described first real estate, and forms black matrix" with blocks light on described second substrate.Described black matrix" has the opening (opening) that forms in described external zones.
According to an aspect of the present invention, described first signal wire and described circuit part separate certain distance, and are in (being formed at) identical (plating) layer with described first and second connecting lines and form as one with described first connecting line corresponding to this.Therefore, the contact electrode that described first signal wire is electrically connected to the first in addition required connecting line can be omitted, thereby prevents the fault of the driver element that the corrosion owing to connecting line causes.
Description of drawings
In conjunction with the accompanying drawings and with reference to following detailed description, those skilled in the art will be readily appreciated that of the present invention above and further feature.Should be appreciated that, do not departing under the situation of the present invention in this disclosed principle, below described one exemplary embodiment of the present invention the variation and the modification of multitude of different ways can be arranged, therefore scope of the present invention can not be subject to following these certain embodiments.More definite is that it is in order to pass on notion of the present invention by exemplary rather than restrictive mode to those skilled in the art that these embodiment are provided.
Hereinafter, will describe the present invention with reference to the accompanying drawings in detail.In the accompanying drawings, identical Reference numeral is represented components identical, and:
Fig. 1 is the block scheme that shows the gate drivers of an one exemplary embodiment according to the present invention;
Fig. 2 is the plan view of the part (I) of the gate drivers in the displayed map 1;
Fig. 3 is the cross sectional view that II-II ' along the line cuts in the part (I) of the gate drivers 160 among the Fig. 1 shown in Fig. 2;
Fig. 4 is the first driving stage SRC of the gate drivers 160 of displayed map 1
1Circuit diagram;
Fig. 5 is the plan view that shows according to the display device of another one exemplary embodiment of the present invention;
Fig. 6 is the cross sectional view of the display device among Fig. 5 of cutting of III-III ' along the line;
Fig. 7 is the cross sectional view of the amplification of the array base palte 100 shown in Fig. 6;
Fig. 8 is the cross sectional view that shows according to the array base palte of another one exemplary embodiment of the present invention;
Fig. 9 is the cross sectional view that shows according to the display device of another one exemplary embodiment of the present invention; With
Figure 10 is the plan view of the array base palte in the displayed map 9.
Embodiment
Fig. 1 is the block scheme that shows the gate drivers 160 of an one exemplary embodiment according to the present invention.With reference to figure 1, gate drivers 160 comprises circuit part CS and the circuit pack LS adjacent with this circuit part CS.
This circuit part CS comprise that cascade each other connects first to last (the 1st to (n+1), is represented by subscript) driving stage SRC
1To SRC
N+1, be used for exporting in turn the 1st to n signal OUT
1To OUT
n, wherein, ' n ' is even number.
First to (n+1) driving stage SRC
1To SRC
N+1In each all comprise: the first clock end CK1, second clock end CK2, first input end IN1, the second input end IN2, cut-out () voltage end V1, reset terminal RE, carry end CR and output terminal OUT.
First clock signal CKV is applied to odd number driving stage SRC
1, SRC
3..., SRC
N+1The first clock end CK1.The second clock signal CKVB that will have the phase place of different with first clock signal CKV (for example, opposite) is applied to even number driving stage SRC
2..., SRC
nThe first clock end CK1.In addition, second clock signal CKVB is applied to odd number driving stage SRC
1, SRC
3..., SRC
N+1Second clock end CK2, and second clock signal CKV is applied to even number driving stage SRC
2..., SRC
nSecond clock end CK2.
Be applied to first to (n+1) driving stage SRC with start signal STV or from the signal of last driving stage
1To SRC
N+1In the first input end IN1 of each grade.Start signal STV is applied to the first driving stage SRC
1First input end IN1 so that the operation of beginning circuit part CS.Start signal STV also is applied to last (n+1) driving stage SRC
N+1The second input end IN2.
Next carry signal from the carry end CR of next driving stage is applied to n+1 driving stage SRC
1To SRC
nAmong the second input end IN2 of each n.Last (n+1) driving stage SRC
N+1Be virtual driving stage, it is provided to n driving stage SRC
nThe second input end IN2 apply next carry signal.Next carry signal is not applied to (n+1) driving stage SRC
N+1The second input end IN2, but start signal STV is applied to (n+1) driving stage SRC
N+1The second input end IN2.
To cut off () voltage Voff is applied to first to (n+1) driving stage SRC
1To SRC
N+1Each grade cut-out () on the voltage end V1.Will be from (n+1) driving stage SRC
N+1(n+1) individual signal of output terminal OUT output be applied to first to (n+1) driving stage SRC as reset signal
1To SRC
N+1In the reset terminal RE of each grade.
(subscript 2 expressions the 2nd) are to last (n+1) driving stage SRC from second
2To SRC
N+1The carry signal of carry end CR output be applied to the second input end IN2 of last driving stage.Equally, from first (subscript 1 expression the 1st) to n driving stage SRC
1To SRC
nFirst to n signal OUT of output terminal OUT output
1To OUT
nBe applied to the first input end IN1 of next driving stage.
Circuit pack LS comprises the start signal line SL that is substantially parallel to each other
1, the first clock line SL
2, second clock line SL
3, cut off () pressure-wire SL
4With reset line SL
5
Start signal line SL
1Start signal STV (for example, from last driving stage) being applied (or transmission) arrives first (1
St) driving stage SRC
1First input end I N1 place and last (n+1) driving stage SRC
N+1The gate drivers 160 at the second input end IN2 place on.
The first clock line SL
2Send from the first outside clock signal CKV to gate drivers 160, and second clock line SL
3Send from outside second clock signal CKVB to gate drivers 160.Cut off equally, () pressure-wire SL
4To gate drivers 160 send from outside cut-out () voltage Voff.Reset line SL
5Will be from last (n+1) driving stage SRC
N+1(n+1) individual signal of output terminal OUT output be applied to first to last (n+1) driving stage SRC
1To SRC
N+1Reset terminal RE.
Fig. 2 is the plan view of the part (I) of the gate drivers 160 among Fig. 1.
With reference to figure 2, circuit pack LS further comprises and being used for respectively with signal wire SL
4, SL
2, SL
3In each bar be connected to driving stage SRC
1To SRC
N+1Many (level) connecting lines of each grade: the first connecting line CL
1, the second connecting line CL
2With the 3rd connecting line CL
3(see figure 2).
The first connecting line CL
1To cut off () pressure-wire SL
4Be electrically connected to circuit part CS first to (n+1) driving stage SRC
1To SR
N+1Cut-out () voltage end V1.The second connecting line CL
2With first clock line (CKV) SL
2Be electrically connected to odd number driving stage SRC
1, SRC
3..., SRC
N+1The first clock end CK1 and to even number driving stage SRC
2, SRC
4..., SRC
nSecond clock end CK2.The 3rd connecting line CL
3With second clock line (CKVB) SL
3Be electrically connected to even number driving stage SRC
2, SRC
4..., SRC
nThe first clock end CK1 and to odd number driving stage SRC
1, SRC
3..., SRC
N+1Second clock end CK2.
With reference to figure 2, circuit part CS first to n driving stage SRC
1To SRC
nIn each level all comprise: be electrically connected to output terminal OUT, be used for controlling first the first circuit part CS to the output of n signal
1, and be used to control the first circuit part CS
1Second circuit portion C S
2
Circuit pack LS comprises: start signal line SL
1, the first clock line SL
2, second clock line SL
3, cut off () pressure-wire SL
4With reset line SL
5Circuit pack LS also comprises the first connecting line CL
1, the second connecting line CL
2With the 3rd connecting line CL
3.
Fig. 3 is the cross sectional view that II-II ' along the line cuts in the part (I) of the gate drivers 160 shown in Fig. 2, among Fig. 1.
As shown in Figure 3, start signal line SL
1, the first clock line SL
2, second clock line SL
3, and reset line SL
5Be formed in the first metal layer and place on first substrate 110.
To cut off () pressure-wire SL
4, and first, second and the 3rd connecting line CL
1, CL
2And CL
3Be formed in second metal level.To cut off () pressure-wire SL
4, and first, second and the 3rd connecting line CL
1, CL
2And CL
3Be deposited on the gate insulating film 120.As first, second and the 3rd connecting line CL
1, CL
2And CL
3Be with start signal line SL
1, the first clock line SL
2, second clock line SL
3With reset line SL
5During different (plating) layer, then first, second and the 3rd connecting line CL
1, CL
2And CL
3With start signal line SL
1, the first clock line SL
2, second clock line SL
3With reset line SL
5Electrical isolation.
To cut off () pressure-wire SL
4With the first connecting line CL
1Be deposited on the gate insulating film 120, thereby cut off () pressure-wire SL
4With the first connecting line CL
1Formed pattern (pattern) simultaneously, deposited and formed as one each other.Therefore, will cut off in addition () pressure-wire SL
4Be electrically connected to the first connecting line CL
1Contact electrode can be omitted.
On gate insulating film 120, form passivating film 130, on this gate insulating film 120, formed cut-out () pressure-wire SL
4And first, second and the 3rd connecting line CL
1, CL
2And CL
3Passivating film 130 comprises inorganic insulating membrane 131 and organic insulating film 132.
Pass passivating film 130 and pass gate insulating film 120 to first clock line SL
2Formed the first contact hole H
1And pass passivating film 130 to second connecting line CL
2Formed the second contact hole H
2The first and second contact hole H
1And H
2Make the first clock line SL
2With the second connecting line CL
2Part exposes.Therefore, the first contact electrode CE
1(be formed on the first and second contact hole H
1And H
2Within and between) be electrically connected respectively by the first and second contact hole H
1And H
2The first clock line SL that part exposes
2With the second connecting line CL
2Equally, pass passivating film 130 and gate insulating film 120 to second clock line SL
3Formed the 3rd contact hole H
3Pass passivating film 130 to the 3rd connecting line CL
3Formed the 4th contact hole H
4The third and fourth contact hole H
3And H
4Make second clock line SL respectively
3With the 3rd connecting line CL
3Part exposes.Therefore, the second contact electrode CE
2(be formed on the third and fourth contact hole H
3And H
4Within and between) be electrically connected by the third and fourth contact hole H
3And H
4The second clock line SL that part exposes
3With the 3rd connecting line CL
3The first and second contact electrode CE
1And CE
2In each all can comprise conductive material, for example, indium tin oxide (ITO) or indium-zinc oxide (IZO).
The first clock line SL
2With the second connecting line CL
2Be positioned on the layer that differs from one another and by the first contact electrode CE
1(equally with reference to figure 2) is electrically connected to each other.Second clock line SL
3With the 3rd connecting line CL
3Be positioned on the layer that differs from one another and by the second contact electrode CE
2(equally with reference to figure 2) is electrically connected to each other.
First, second and the 3rd connecting line CL
1, CL
2And CL
3Be positioned at and be different from start signal line SL
1, the first clock line SL
2, second clock line SL
3With reset line SL
5(plating) layer on, thereby make first, second and the 3rd connecting line CL
1, CL
2And CL
3In each all with start signal line SL
1, the first clock line SL
2, second clock line SL
3, and reset line SL
5Electrical isolation.
Cut off () pressure-wire SL
4Approach a side of first substrate 110.Therefore, cut off () pressure-wire SL
4Compared with beginning signal wire SL
1, the first clock line SL
2, second clock line SL
3With reset line SL
5More approach this side of first substrate 110, thus make cut-out () pressure-wire SL
4Be not overlapped in the second and the 3rd connecting line CL
2And CL
3On.
Therefore, cut off () pressure-wire SL
4Can be deposited over and first, second and the 3rd connecting line CL
1, CL
2And CL
3On the identical layer.In this one exemplary embodiment of the present invention, provide in addition with cut-out () pressure-wire SL
4Be electrically connected to the first connecting line CL
1Contact electrode can by and be omitted, thereby the quantity of the contact electrode that forms has been reduced.Cut off in addition, () pressure-wire SL
4With the first connecting line CL
1Between line resistance also reduced, and can prevent the corrosion of the gate drivers 160 that caused by institute's abridged contact electrode.
Fig. 4 is the first driving stage SRC of the gate drivers 160 of displayed map 1
1Circuit diagram.The first driving stage SRC
1With second to (n+1) driving stage SRC
2To SRC
N+1Basic identical, thus relevant any to second to (n+1) driving stage SRC
2To SRC
N+1Further explain and to be omitted.
With reference to figure 4 and Fig. 1, the first driving stage SRC
1Comprise that lifting (pull-up) part 161 and reduction (pull-down) part 162, lifting driver portion (comprising first live part 163 and first discharge portion 165 and bumper portion 164), retaining part 16, second discharge portion 167, switch sections 168, carry portion 169, ripple prevent part 170 and the part 171 that resets.
Lift portion 161 will be from grid (driving) signal boost (rising to first clock signal CKV) of output terminal OUT (as shown in fig. 1) output.Reduce part 162 based on from next driving stage (for example, second driving stage SRC
2) next carry signal of (as shown in fig. 1) makes signal reduce (drop to cut-out () voltage Voff).
Lift portion 161 comprises first (N-FET) transistor NT
1The first transistor NT
1Has the first node of being electrically connected to N
1Grid, be electrically connected to the drain electrode of the first clock end CK1 and be electrically connected to the source electrode of output terminal OUT.Reduce part 162 and comprise second (N-FET) transistor NT
2Transistor seconds NT
2Have the grid that is electrically connected to the second input end IN2, the drain electrode that is electrically connected to output terminal OUT and source electrode.Cut off () voltage Voff is applied to transistor seconds NT
2Source electrode.
The first driving stage SRC
1Also comprise promote driver portion (by live part 163, and first discharge portion 165, and bumper portion 164 form).Promote that driver portion is connected lift portion 161 based on start signal (by the STV of IN1) and based on from next (for example, second) driving stage SRC
2Next carry signal turn-off lift portion 161.The lifting driver portion comprises: first live part 163, and first discharge portion 165, and bumper portion 164.
Live part 163 has the 3rd transistor NT
3The 3rd transistor NT
3Have the grid that is electrically connected to first electrode and is electrically connected to first input end IN1, be electrically connected to the drain electrode of first input end IN1 and be connected to first node N
1Source electrode.Bumper portion 164 comprises the first capacitor C
1The first capacitor C
1Has the first node of being electrically connected to N
1First electrode and be electrically connected to Section Point N
2(OUT) second electrode.Discharge portion 165 comprises the 4th transistor NT
4The 4th transistor NT
4Have the grid that is electrically connected to the second input end IN2, be electrically connected to first node N
1Drain electrode and source electrode.Cut off () voltage Voff is applied to the 4th transistor NT
4Source electrode.
As the 3rd transistor NT
3During connection (for example), give the first capacitor C by the electric charge that stored charge (for example, from start signal STV) forms based on start signal STV
1Charging.When being stored in the first capacitor C
1Interior electric charge has the first transistor of being higher than NT
1Threshold voltage according the time, the first transistor NT so
1Connect (bootstrapping), with give output terminal OUT export (by) have (first) clock signal CKV of high level.As the 4th transistor NT
4(in the discharge portion 165) when connecting according to next carry signal, make to be stored in the first capacitor C
1In charge discharge to cut off () voltage Voff.
The first driving stage SRC
1Also comprise retaining part 166, second discharge portion 167 and switch sections 168.The extremely cut-out of level of retaining part 166 inhibition (hold down) signals () voltage Voff.The operation of switch sections 168 control retaining parts 166.Second discharge portion 167 based on second clock signal CKVB make signal (at node N2 and OFF) be discharged to cut-out () voltage.
Retaining part 166 comprises the 5th transistor NT
5The 5th transistor NT
5Have and be connected to the 3rd node N
3Grid, be connected to Section Point N
2(OUT) drain electrode and source electrode.Cut off () voltage Voff is applied in the 5th transistor NT
5Source electrode.Second discharge portion 167 comprises the 6th transistor NT
6The 6th transistor NT
6Have the grid that is connected to second clock end CK2, be connected to Section Point N
2Drain electrode and source electrode.Cut off () voltage Voff is applied to the 6th transistor NT
6Source electrode.
Switch sections 168 comprises the 7th transistor NT
7, the 8th transistor NT
8, the 9th transistor NT
9, the tenth transistor NT
10, the second capacitor C
2, and the 3rd capacitor C
3
The 7th transistor NT
7Have the grid that is electrically connected to the first clock end CK1, be electrically connected to the drain electrode of the first clock end CK1 and be electrically connected to the 3rd node N
3Source electrode.The 8th transistor NT
8Have the drain electrode that is electrically connected to the first clock end CK1, via the second capacitor C
2Be electrically connected to the grid of the first clock end CK1 and be electrically connected to the 3rd node N
3Source electrode.The 3rd capacitor C
3Be connected the 8th transistor NT
8Grid and source electrode between.
The 9th transistor NT
9Has the Section Point of being electrically connected to N
2(OUT) grid, be electrically connected to the 7th transistor NT
7The drain electrode and the source electrode of source electrode.Cut off () voltage Voff is applied in the 9th transistor NT
9Source electrode.The tenth transistor NT
10Has the Section Point of being electrically connected to N
2(OUT) grid, be electrically connected to the 3rd node N
3Drain electrode and source electrode.Cut off () voltage is applied in the tenth transistor NT
10Source electrode.
When first clock signal CKV (via CK1) output to (by) output terminal OUT and the 7th and the 8th transistor NT
7And NT
8During by the first clock signal CKV conducting, to Section Point N
2(OUT) provide the signal that is in high state.When to Section Point N
2When (OUT) providing the signal that is in high state, the 9th and the tenth transistor NT
9And NT
10Conducting is by the 7th and the 8th transistor NT
7And NT
8The voltage of output is via the 9th and the tenth transistor NT
9And NT
10Be discharged to cut-out () voltage Voff.So, the 3rd node N
3Maintain low level, thereby make the 5th transistor NT
5End.
When next carry signal makes signal (Section Point N
2, OUT) be discharged to cut-out () during voltage Voff, Section Point N
2Level drop to low level step by step.So the 9th and the tenth transistor NT
9And NT
10End, be added to the 3rd node N
3On the level of signal by the 7th and the 8th transistor NT
7And NT
8The voltage of output increases gradually.When being added to the 3rd node N
3On the level of signal when increasing, the 5th transistor NT
5Conducting, and be added to Section Point N
2The level of the signal (OUT) is by the 5th transistor NT of conducting
5Be reduced to rapidly cut-out () voltage Voff.
When making the 6th transistor NT by second clock signal CKVB is added to second clock end CK2
6During conducting, be added to Section Point N
2The level of signal (OUT) be discharged to cut-out () voltage Voff..
Carry portion 169 comprises the 11 transistor NT
11The 11 transistor NT
11Has the first node of being electrically connected to N
1Grid, be electrically connected to the first clock end CK1 (for example, drain electrode CKV) and be connected to the source electrode of carry end CR.As first node N
1Level when increasing, the 11 transistor NT
11Conducting, and export first clock signal CKV, this clock signal is added to the 11 transistor NT
11Drain electrode as adding to the carry signal of carry end CR.Thereby, from odd number driving stage SRC
1, SRC
3..., SRC
N+1First clock signal CKV of carry end CR (with output terminal OUT) output, from even number driving stage SRC
2..., SRC
nThe second clock signal CKVB of carry end CR (with output terminal OUT) output.
Ripple prevents that part 170 from comprising the tenth two-transistor NT
12With the 13 transistor NT
13The tenth two-transistor NT
12Have and be electrically connected to the first clock end CK1 (for example, CKV) grid is electrically connected to the 13 transistor NT
13The drain electrode of source electrode and be electrically connected to Section Point N
2(OUT) source electrode.The 13 transistor NT
13Have the grid that is electrically connected to second clock end CK2, be electrically connected to the drain electrode of first input end IN1 and be electrically connected to the 11 transistor NT
11The source electrode of drain electrode.
As first grid signal (Section Point N
2, OUT) be discharged to cut-out () during voltage Voff, ripple prevents that part 170 from preventing the first grid signal because the first and second clock CK1 and CK2 play ripple.
The part that resets 171 comprises the 14 transistor NT14.The 14 transistor NT
14Have the grid that is electrically connected to reset terminal RE, be electrically connected to the drain electrode of the IN1 of first input end, and source electrode.Cut off () voltage Voff is added to the 14 transistor NT
14Source electrode.When (n+1) individual signal is added to reset terminal RE ((n+1) driving stage SRC
N+1) time, the 14 transistor NT
14Conducting, and make through first input end IN1 and to be added in the 14 transistor NT
14The signal of source electrode be discharged to cut-out () voltage Voff.So, the 3rd transistor NT
3Not by the signal conduction that applies through first input end IN1.
Fig. 5 is the planimetric map of expression display device of another one exemplary embodiment according to the present invention.Fig. 6 is the sectional view that cuts along the line III-III ' shown in Fig. 5.
With reference to figure 5 and Fig. 6, display device 400 comprises display board 300, data driver 150 and gate drivers 160.Display board 300 comes display image according to first (data) drive signal and second (grid) drive signal.Data driver 150 and gate drivers 160 are exported first and second drive signals respectively.
On first substrate 110 of the array base palte 100 in the DA scope of viewing area, form first to n bar gate lines G L
1To GL
nWith first to m bar data line DL
1To DL
mFirst to n bar gate lines G L
1To GL
nWith first to m bar data line DL
1To DL
mIntersect.First to n bar gate lines G L
1To GL
nWith first to m bar data line DL
1To DL
mElectrical isolation.On same first substrate 110 in the DA of viewing area, form a plurality of thin film transistor (TFT)s (TFFs, for example, T
R1) and a plurality of liquid crystal capacitor (Cl
C1).
For example, a plurality of (for example, the first film transistor Tr in the thin film transistor (TFT) of 3 * n * m)
1Grid and first grid polar curve GL
1Be electrically connected.The first film transistor Tr
1The source electrode and the first data line DL
1Be electrically connected.The first film transistor Tr
1Drain electrode and a plurality of (for example, first liquid crystal capacitor Cl in the liquid crystal capacitor of 3 * n * m)
C1Be electrically connected.
Comprise corresponding to the pseudo-colour filtering substrate 200 of (interior) viewing area DA and to be adjacent to second plate 210 and to comprise red filtering part R, green filtering part G and the pseudo-colour filtering layer 220 of the blue color filtered part B and first black matrix" 230.First black matrix" 230 places between the pseudo-colour filtering part of redness, green and blue color filtered part R, G and two vicinities of B.Equally, second black matrix" 240 places on second plate 210 corresponding to (interior) potted line district SA.Be adjacent to second substrate 210 and pseudo-colour filtering layer 220, and first and second black matrix" s 230 and 240 form public electrode 250.
At the first external zones PA
1, first plate, 110 outstanding second plate 210 and the pseudo-colour filtering substrates 200 of surpassing of array base palte 100.Data driver 150 (see figure 5)s with sheet shape (chip-shape) place the first external zones PA corresponding to (interior)
1 First substrate 110 on.In data driver 150 and the viewing area DA first is to n bar data line DL
1To DL
nBe electrically connected.Comprise first to m data-signal from first drive signal of data driver 150 outputs, and first to m data-signal is added to first respectively to m bar data line DL
1To DL
mOn.
At the second external zones PA
2Be adjacent to the second external zones PA
2Potted line district SA in, form gate drivers 160 with thin film transistor (TFT) simultaneously with (plating) layer.On gate drivers 160 and the viewing area DA first is to n bar gate lines G L
1To GL
nBe electrically connected.Comprise first to n signal OUT from second drive signal of gate drivers 160 outputs
1To OUT
n(as shown in Figure 1), first to n signal is added to first respectively to n bar gate lines G L
1To GL
nOn.
Within potted line district SA, sealant 350 part cover gate drivers 160.So sealant 350 prevents to be short-circuited between public electrode 250 (it can form by conducting particles) and the gate drivers 160.
Equally, because sealant 350 has the specific inductive capacity littler than the liquid crystal layer between public electrode 250 and gate drivers 160 330, so the stray capacitance that produces between public electrode 250 and the gate drivers 160 has reduced.Therefore, can prevent the fault of gate drivers 160.
Fig. 7 is the sectional view of the amplification of array base palte 100 shown in Figure 6.
With reference to figure 7, in same metal cladding (for example, the first metal layer), form start signal line SL
1, the first clock line SL
2, second clock line SL
3, reset line SL
5With first grid polar curve GL
1Deposition forms start signal line SL on first plate 110
1, the first clock line SL
2, second clock line SL
3, reset line SL
5With first grid polar curve GL1.
The first metal layer for example can have single layer structure, comprises aluminium based metal, silver-base metal, copper base metal, molybdenum Base Metal, chromium, tantalum or titanium.
Optionally, the first metal layer can have the double-decker of being made up of sublayer, bottom and sublayer, top.The sublayer, top is on the sublayer, bottom, and the sublayer, top has different physical characteristicss with the sublayer, bottom.The sublayer, top comprises the metal with low-resistance coefficient, as, aluminium based metal, silver-base metal, copper base metal are to reduce the landing of signal delay or voltage.The sublayer, bottom can comprise the material that has good step level of coverage (good step coverage) with ITO and IZO, as, chromium, molybdenum, molybdenum alloy, tantalum or titanium, or the like.
In an one exemplary embodiment, have double-deck the first metal layer and can comprise sublayer of forming by the aluminium neodymium, top and the sublayer of forming by molybdenum tungsten, bottom.
On first plate 110 and at start signal line SL
1, the first clock line SL
2, second clock line SL
3, reset line SL
5With first grid polar curve GL
1On form gate insulating film 120.
Cut off () pressure-wire SL
4, first, second and the 3rd connecting line are with CL
1, CL
2And CL
3And the first data line DL
1In same metal cladding (for example, second metal film), form, and be formed on the gate insulating film 120.The single layer structure that second metal film (layer) can be made up of chromium, or three-decker by molybdenum tungsten, aluminium neodymium and molybdenum tungsten sublayer sequential lamination are formed.
First, second and the 3rd connecting line CL
1, CL
2And CL
3With start signal line SL
1, the first clock line SL
2, second clock line SL
3With reset line SL
5In different layers, and separate with gate insulating film 120.So, first, second and the 3rd connecting line CL
1, CL
2And CL
3With start signal line SL
1, the first clock line SL
2, second clock line SL
3With reset line SL
5Electrical isolation.
Cut off () pressure-wire SL
4With the first connecting line CL
1Be deposited on the gate insulating film 120.So, cut off () pressure-wire SL
4With the first connecting line CL
1Can form pattern simultaneously on gate insulating film 120 also forms as one each other.Consequently, provide in addition with cut-out () pressure-wire SL
4With the first connecting line CL
1The contact electrode that is electrically connected can omit.
Comprise cut-out () pressure-wire SL
4And first, second and the 3rd connecting line CL
1, CL
2And CL
3Layer on, and on gate insulating film 120, form passivating film 130.Passivating film 130 can comprise inorganic insulating membrane 131 and organic insulating film 132.
Each other at the first clock line SL of different metal claddings
2With the second connecting line CL
2By the first contact electrode CE
1Be electrically connected mutually.Each other at the second clock line SL of different metal claddings
3Pass through the second contact electrode CE with the 3rd connecting line CL3
2Be electrically connected mutually.Cut off () pressure-wire SL
4With the first connecting line CL
1Also forming as one mutually with one deck.
First, second and the 3rd connecting line CL
1, CL
2And CL
3With start signal line SL
1, the first clock line SL
2, second clock line SL
3With reset line SL
5At different layers, thereby, first, second and the 3rd connecting line CL
1, CL
2And CL
3In each can with part start signal line SL
1, the first clock line SL
2, second clock line SL
3With reset line SL
5Electrical isolation, these parts and first, second and the 3rd connecting line CL
1, CL
2And CL
3Be not electrically connected.
Cut off () pressure-wire SL
4Compared with beginning signal wire SL
1, the first clock line SL
2, second clock line SL
3With reset line SL
5More approach a side of first plate 110, thereby, cut off () pressure-wire SL
4Not with the second and the 3rd connecting line CL
2And CL
3Overlapping.So, cut off () pressure-wire SL
4Can be positioned at and first, second and the 3rd connecting line CL
1, CL
2And CL
3Identical layer.Consequently, the quantity of the electrode that forms in gate drivers 160 has reduced, thereby, because contact electrode and the line resistance that increases in addition can reduce.
In addition, when sealant 350 (as shown in Figure 6) and array base palte 100 misalignments, the cut-out of contiguous sealant 350 () pressure-wire SL
4Can partly expose, though the cut-out of contiguous sealant 350 () pressure-wire SL
4Part exposes, and still, because the corrosion ratio of the gate drivers that contact electrode causes can reduce, thereby has prevented the fault of gate drivers 160.
Fig. 8 is the sectional view of expression array base palte 100 of another one exemplary embodiment according to the present invention.
With reference to figure 8, on first plate 110 of array base palte 100, formed cut-out () pressure-wire SL
4, the first connecting line CL
1, the second connecting line CL
2, the 3rd connecting line CL
3With first grid polar curve GL
1Cut off () pressure-wire SL
4, the first connecting line CL
1, the second connecting line CL
2, the 3rd connecting line CL
3With first grid polar curve GL
1In each bar comprise (being formed on ... interior) the first metal layer.
On first plate 110 and comprise cut-out () pressure-wire SL
4, first, second and the 3rd connecting line CL
1, CL
2And CL
3And first grid polar curve GL
1The first metal layer on form gate insulating film 120.Start signal line SL
1, the first clock line SL
2, second clock line SL
3, reset line SL
5With first data line at DL
1Be deposited on (in second metal cladding) on the gate insulating film 120.
On gate insulating film 120 and comprising start signal line SL
1, the first and second clock line SL
2And SL
3, reset line SL
5With the first data line DL
1Second metal level on form passivating film 130.
Though the first clock line SL
2With the second connecting line CL
2Each other at different layers, but by the first contact electrode CE
1Be electrically connected mutually.Though second clock line SL
3With the 3rd connecting line CL
3Each other at different layers, but by the second contact electrode CE
2Be electrically connected mutually.
Cut off () pressure-wire SL
4With the first connecting line CL
1Being in identical layer also forms as one each other.So, provide in addition with cut-out () pressure-wire SL
4With the first connecting line CL
1The contact electrode that is electrically connected can omit, thereby the quantity of contact electrode has reduced in the gate drivers 160.So cut off () pressure-wire SL
4With the first connecting line CL
1Between line resistance can reduce, to prevent because the corrosion of the gate drivers 160 that causes of contact electrode.
In optional embodiment of the present invention, as the first clock line SL
2With second clock line SL
3In one of than cut off () pressure-wire SL
4When more approaching a side of array base palte, the first clock line SL then
2Or second clock line SL
3In one of can be formed on and first, second and the 3rd connecting line CL
1, CL
2And CL
3In identical (plating) layer.And, if the first clock line SL
2Or second clock line SL
3In one of with the corresponding second connecting line CL
2Or the 3rd connecting line CL
3In one of form as one the then corresponding first contact electrode CE
1Or the second contact electrode CE
2In one of can omit, to prevent because the first contact electrode CE
1Or the second contact electrode CE
2The corrosion of the gate drivers 160 that causes.
Fig. 9 is the sectional view of expression display device of another one exemplary embodiment according to the present invention.Figure 10 is the planimetric map of the array base palte in the presentation graphs 9.In Fig. 9 and Figure 10, identical numeral and Fig. 1 components identical in Fig. 8, and therefore, omit the explanation that further repeats of similar elements.
With reference to figure 9 and Figure 10, gate drivers 160 comprises start signal line SL
1, the first and second clock line SL
2And SL
3, cut off () pressure-wire SL
4, reset line SL
5With electrode layer EY.
By the first metal layer form cut-out () pressure-wire SL
4, and form start signal line SL by second metal level (being different from the first metal layer)
1, the first and second clock line SL
2And SL
3, reset line SL
5With electrode layer EY.
On first substrate 110, form and comprise start signal line SL
1, the first and second clock line SL
2And SL
3, reset line SL
5The first metal layer with electrode layer EY.On first substrate 110 and on the first metal layer, form gate insulator 120 to cover start signal line SL
1, the first and second clock line SL
2And SL
3, reset line SL
5With electrode layer EY.Formation cut-out on gate insulator 120 () pressure-wire SL
4So, cut off () pressure-wire SL
4Compared with beginning signal wire SL
1, the first and second clock line SL
2And SL
3, reset line SL
5The surface of more approaching second substrate 210 with electrode layer EY.
Forming passivation layer 130 on the gate insulator 120 and on second metal cladding, cut off to cover () pressure-wire SL
4Passivation layer 130 can comprise organic insulator and/or inorganic insulation layer.In embodiments of the present invention, though cut off () pressure-wire SL
4Cover by passivation layer 130, still, start signal line SL
1, the first and second clock line SL
2And SL
3, reset line SL
5Cover by gate insulator 120 and passivation layer 130 with electrode layer EY.
Pass second black matrix" 240 and form opening 241, this opening and cut-out () pressure-wire SL
4The position corresponding.Opening 241 ratio cut-outs () pressure-wire SL
4Wideer or with cut off () pressure-wire SL
4Width basic identical.Second black matrix" 240 comprises metal material, as chromium (Cr).
When on second black matrix" 240, forming public electrode 250 (with reference to figure 6), on second substrate 210 that exposes through opening 241, form and cut off () pressure-wire SL
4The corresponding public electrode 250 in position.
Thereby, can prevent to cut off () pressure-wire SL
4And second between the black matrix" 240 short circuit and the corrosion of second black matrix".Equally, when on second black matrix" 240, forming public electrode 250, can prevent the corrosion of second black matrix" because black matrix" 240 with cut off () pressure-wire SL
4What corresponding intra-zone divided is moved.
Though sealant 350 may be subjected to displacement between array base palte 100 and pseudo-colour filtering substrate 200,, opening 241 can prevent second black matrix" 240 and cut off () pressure-wire SL
4Between short circuit.
Therefore, at this driver element and having in the display device of this driver element array, cut off () pressure-wire (this line is separated by a distance with circuit part) and first to the 3rd connecting line be positioned at (being formed on) identical layer, and with first to the 3rd connecting line in one of form as one.So, be used for the contact electrode of first signal wire and the electrical connection of first connecting line can be omitted, with the quantity of contact electrode in the minimizing driver element, thereby prevent because the fault of the driver element that the corrosion of contact electrode causes.
Equally, with cut off () in the corresponding zone, position of pressure-wire, pass second black matrix" and form opening.So, can prevent to cut off () short circuit between pressure-wire and second black matrix" and the corrosion of second black matrix", thereby prevent the fault of display device.
Though described one exemplary embodiment of the present invention, but, be to be understood that the present invention should not be restricted to these one exemplary embodiment, and should be, in the desired the spirit and scope of the present invention as claims, those skilled in the art can make variations and modifications.
Claims (30)
1. driver element comprises:
Circuit part comprises a plurality of driving stages, is used for based on a plurality of control signal output driver signals; And
Circuit pack, comprise first signal wire, secondary signal line, described first signal wire is electrically connected to first connecting line of described driving stage and second connecting line that described secondary signal line is electrically connected to described driving stage, described first and second signal wires transmit described control signal, described first signal wire and described first and second connecting lines are set in the ground floor, and this ground floor is different from the second layer that comprises described secondary signal line.
2. driver element according to claim 1, wherein said secondary signal line is between described first signal wire and described a plurality of driving stage.
3. driver element according to claim 2, wherein said first signal wire and described first connecting line form as one.
4. driver element according to claim 1, wherein said secondary signal line comprise that at least one driving stage in described a plurality of driving stages transmits the start signal line of start signal, and this start signal begins the operation of described a plurality of driving stages;
Transmit first clock line of first clock signal to described a plurality of driving stages; And
To the second clock line of described a plurality of driving stages transmission second clock signals, wherein said second clock signal has and the different phase place of described first clock signal.
5. driver element according to claim 1, wherein said first signal wire is to transmit the cut-out ground voltage line of cutting off ground voltage to described a plurality of driving stages, and at least one in the start signal line and first and second clock lines are between described first signal wire and described a plurality of driving stage.
6. driver element according to claim 1, at least one driving stage in the wherein said driving stage comprises:
Input end is used for receiving start signal or drive signal from last driving stage;
First clock end is used for receiving first clock signal and second clock signal one;
The second clock end is used for receiving another of described first and second clock signals;
Cut off the ground voltage end, be used for receiving the cut-out ground voltage;
Control end is used for receiving carry signal from next driving stage;
The carry end is used for the output carry signal; And
Output terminal is used for output drive signal.
7. driver element according to claim 6, at least one driving stage of this in the wherein said driving stage also comprises: reset terminal is configured to receive the drive signal of last driving stage.
8. driver element according to claim 7, wherein said secondary signal line is a reset line, is used for applying to described a plurality of driving stages the drive signal of described last driving stage.
9. driver element according to claim 1, each layer in the wherein said ground floor and the described second layer all is the depositing metal layers of patterning.
10. driver element according to claim 1, wherein said driving stage each the level all with another driving stage cascade.
11. a display device comprises:
Display board is configured to utilize signal and data-signal to come display image; And
Gate drivers is configured to produce described signal, and described gate drivers comprises:
A plurality of driving stages, each driving stage all are configured to export signal based on a plurality of control signals, the cascade each other of described driving stage; And
First signal wire, secondary signal line, described first signal wire is electrically connected to first connecting line of described driving stage and described secondary signal line is electrically connected to second connecting line of described driving stage, described first signal wire and described first and second connecting lines are set at the layer different with described secondary signal line.
12. display device according to claim 11, wherein said gate drivers is formed on the described display board.
13. display device according to claim 11, wherein said display board comprises:
First substrate has the described gate drivers of the described signal of output, many gate lines that receive described signal and many data lines that receive described data-signal; And
Second substrate lumps together with described first substrate junction.
14. display device according to claim 13, wherein said gate line is at ground floor, and described data line is to be different from the second layer of described ground floor, and described data line and described gate line intersect, and described data line insulate mutually with described gate line.
15. display device according to claim 14, wherein said secondary signal line is at described ground floor, and described first signal wire and described first and second connecting lines are at the described second layer.
16. display device according to claim 15, each bar in wherein said first and second connecting lines all comprise have molybdenum tungsten sublayer, the three-decker of aluminium neodymium sublayer and molybdenum tungsten sublayer.
17. display device according to claim 15, wherein said first signal wire and described first connecting line form as one.
18. display device according to claim 14, wherein said first signal wire and described first and second connecting lines are at described ground floor, and described secondary signal line is at the described second layer.
19. display device according to claim 13, wherein said display board also comprises:
Liquid crystal layer is formed between described first and second substrates; And
Sealant, so that described first substrate and described second substrate combine, described sealant is overlapped with the described gate drivers that forms on described first substrate between described first and second substrates.
20. display device according to claim 11, wherein said secondary signal line comprise one of alignment down:
The start signal line is used for providing start signal to described gate drivers, and this start signal begins the operation of described gate drivers;
First clock line is used for providing first clock signal to described gate drivers; And
The second clock line is used for providing the second clock signal to described gate drivers, and described second clock signal has and the different phase place of described first clock signal.
21. display device according to claim 20, wherein said first signal wire is to transmit the cut-out ground voltage line of cutting off ground voltage to described gate drivers, and described start signal line and described first and second clock lines are between described first signal wire and described gate drivers.
22. a display device comprises:
Array base palte comprises:
First substrate is divided into viewing area and the external zones adjacent with described viewing area;
Driver, on first substrate, be positioned within the described external zones, described driver is configured to output drive signal; With
Pel array, on first substrate, be positioned within the described viewing area, described pel array is configured to receive the described drive signal from described driver, and
Second substrate and on described second substrate black matrix" that form, that be used for blocks light, described black matrix" has the opening that forms in described external zones,
Wherein said driver comprises:
Circuit part comprises a plurality of driving stages, and these a plurality of driving stages are configured for the output driver signal, each all cascade each other of level of described driving stage; And
Circuit pack comprises first signal wire and the secondary signal line that are used for transmitting to described driver control signal, and described first signal wire is set on the layer different with described secondary signal line.
23. display device according to claim 22, wherein said secondary signal line is formed on described first substrate, and described first signal wire is formed on the insulation course that is formed on described first substrate.
24. display device according to claim 22, wherein said opening is corresponding with the position of described first signal wire, and described opening has the width of being wider than the described first signal wire width or the width identical with the width of described first signal wire.
25. display device according to claim 22, wherein said black matrix" comprises metal material.
26. display device according to claim 22, wherein public electrode is formed on described black matrix" and described second substrate.
27. display device according to claim 22, wherein said driver and described pel array are formed on described first substrate by thin film deposition process technology.
28. display device according to claim 22 also comprises:
Liquid crystal layer is between described array base palte and described second substrate; With
Sealant lumps together described array base palte and described second substrate junction being used between described array base palte and described second substrate.
29. display device according to claim 28, at least a portion of the described driver that wherein said sealant will form on described first substrate partly covers.
30. display device according to claim 28, wherein said sealant is between described first signal wire and described opening.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR73127/04 | 2004-09-13 | ||
| KR1020040073127A KR101014172B1 (en) | 2004-09-13 | 2004-09-13 | Driving unit and display apparatus having the same |
| KR47859/05 | 2005-06-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1760946A CN1760946A (en) | 2006-04-19 |
| CN100517434C true CN100517434C (en) | 2009-07-22 |
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ID=36158516
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101283028A Active CN100517434C (en) | 2004-09-13 | 2005-09-13 | Driving unit and display apparatus having the same |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2006079041A (en) |
| KR (1) | KR101014172B1 (en) |
| CN (1) | CN100517434C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108051967A (en) * | 2017-12-29 | 2018-05-18 | 深圳市华星光电技术有限公司 | A kind of display panel |
Families Citing this family (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101056369B1 (en) * | 2004-09-18 | 2011-08-11 | 삼성전자주식회사 | Drive unit and display device having same |
| KR101404542B1 (en) * | 2006-05-25 | 2014-06-09 | 삼성디스플레이 주식회사 | Liquid crystal display |
| US8330492B2 (en) | 2006-06-02 | 2012-12-11 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and electronic device |
| KR101275248B1 (en) * | 2006-06-12 | 2013-06-14 | 삼성디스플레이 주식회사 | Gate driver circuit and display apparatus having the same |
| EP1895545B1 (en) | 2006-08-31 | 2014-04-23 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
| KR100814820B1 (en) | 2006-08-31 | 2008-03-20 | 삼성에스디아이 주식회사 | Organic light emitting display |
| JP4990034B2 (en) * | 2006-10-03 | 2012-08-01 | 三菱電機株式会社 | Shift register circuit and image display apparatus including the same |
| KR101294321B1 (en) * | 2006-11-28 | 2013-08-08 | 삼성디스플레이 주식회사 | Liquid crystal display |
| KR101493276B1 (en) * | 2007-05-09 | 2015-02-16 | 삼성디스플레이 주식회사 | Timing controller, liquid crystal display comprising the same and driving method of the liquid crystal display |
| KR101415562B1 (en) | 2007-08-06 | 2014-07-07 | 삼성디스플레이 주식회사 | Gate driving circuit and display apparatus having the same |
| KR101471553B1 (en) * | 2008-08-14 | 2014-12-10 | 삼성디스플레이 주식회사 | Gate driving circuit and display device having the same |
| CN101727859B (en) * | 2008-10-15 | 2012-12-26 | 北京京东方光电科技有限公司 | Grid electrode driving device of liquid display crystal |
| KR101785236B1 (en) | 2008-11-28 | 2017-10-12 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device, display device and electronic device including the same |
| EP2541533A1 (en) | 2010-02-25 | 2013-01-02 | Sharp Kabushiki Kaisha | Display device |
| CN102193237B (en) * | 2010-03-04 | 2012-10-03 | 胜华科技股份有限公司 | Display panel |
| KR101759985B1 (en) | 2010-10-20 | 2017-07-21 | 삼성디스플레이 주식회사 | Gate driver and Liquid crystal display comprising thereof |
| KR101697841B1 (en) | 2012-04-20 | 2017-01-18 | 샤프 가부시키가이샤 | Display device |
| JP5866439B2 (en) | 2012-05-16 | 2016-02-17 | シャープ株式会社 | Liquid crystal display |
| KR102334393B1 (en) * | 2014-11-26 | 2021-12-01 | 삼성디스플레이 주식회사 | Display device |
| KR102497761B1 (en) * | 2015-10-30 | 2023-02-07 | 엘지디스플레이 주식회사 | Array Substrate |
| KR102635916B1 (en) * | 2016-09-30 | 2024-02-08 | 엘지디스플레이 주식회사 | Display panel and borderless type display device including the same |
| KR102380764B1 (en) * | 2017-07-18 | 2022-03-31 | 엘지디스플레이 주식회사 | Gate shift register and organic light emitting display device including the same |
| KR102523978B1 (en) | 2018-03-19 | 2023-04-21 | 삼성디스플레이 주식회사 | Display device |
| CN110346990B (en) * | 2019-06-24 | 2021-06-25 | 苏州华星光电技术有限公司 | GOA circuit and display panel thereof |
| JP7078653B2 (en) * | 2020-01-21 | 2022-05-31 | 株式会社半導体エネルギー研究所 | Display device |
| CN111487825B (en) | 2020-04-23 | 2023-05-12 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
| CN115668353A (en) * | 2021-03-29 | 2023-01-31 | 京东方科技集团股份有限公司 | Display panel and display device |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2939043B2 (en) * | 1992-04-07 | 1999-08-25 | シャープ株式会社 | Active matrix substrate |
| JP3291069B2 (en) * | 1992-04-17 | 2002-06-10 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method thereof |
| JP3240681B2 (en) * | 1992-04-24 | 2001-12-17 | セイコーエプソン株式会社 | Active matrix panel drive circuit and active matrix panel |
| JP3122003B2 (en) * | 1994-08-24 | 2001-01-09 | シャープ株式会社 | Active matrix substrate |
| JP3897873B2 (en) * | 1997-09-11 | 2007-03-28 | 株式会社半導体エネルギー研究所 | Driving circuit for liquid crystal display device |
| JP2004118215A (en) * | 1997-10-13 | 2004-04-15 | Sanyo Electric Co Ltd | Display device |
| JP2001281679A (en) * | 2000-03-29 | 2001-10-10 | Matsushita Electric Ind Co Ltd | Active matrix type liquid crystal display device |
| KR100752602B1 (en) * | 2001-02-13 | 2007-08-29 | 삼성전자주식회사 | Shift resister and liquid crystal display using the same |
| JP2002299630A (en) * | 2001-03-30 | 2002-10-11 | Matsushita Electric Ind Co Ltd | Thin film transistor using integrated thin film of mow/al or al alloy/mow, thin film transistor array and manufacturing method therefor |
| KR100831280B1 (en) * | 2001-12-26 | 2008-05-22 | 엘지디스플레이 주식회사 | Liquid Crystal Display Device |
| US20030179542A1 (en) * | 2002-03-22 | 2003-09-25 | Compal Electronic, Inc | Means for externally connecting battery pack to portable computer |
| JP4480944B2 (en) * | 2002-03-25 | 2010-06-16 | シャープ株式会社 | Shift register and display device using the same |
| US7023410B2 (en) * | 2002-04-08 | 2006-04-04 | Samsung Electronics Co., Ltd. | Liquid crystal display device |
| JP3901127B2 (en) * | 2002-06-07 | 2007-04-04 | セイコーエプソン株式会社 | Electro-optical device and electronic apparatus |
| JP2004253511A (en) * | 2003-02-19 | 2004-09-09 | Hitachi Displays Ltd | Display apparatus |
| KR101010509B1 (en) * | 2004-05-31 | 2011-01-21 | 엘지디스플레이 주식회사 | Liquid Crystal Display Built-in Driving Circuit |
-
2004
- 2004-09-13 KR KR1020040073127A patent/KR101014172B1/en active IP Right Grant
- 2004-11-15 JP JP2004330063A patent/JP2006079041A/en active Pending
-
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- 2005-09-13 CN CNB2005101283028A patent/CN100517434C/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108051967A (en) * | 2017-12-29 | 2018-05-18 | 深圳市华星光电技术有限公司 | A kind of display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2006079041A (en) | 2006-03-23 |
| CN1760946A (en) | 2006-04-19 |
| KR20060024234A (en) | 2006-03-16 |
| KR101014172B1 (en) | 2011-02-14 |
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