JP3240681B2 - Active matrix panel drive circuit and active matrix panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix panel such as a liquid crystal display panel and, more particularly, to a structural technology on a driving circuit side thereof.

[0002]

2. Description of the Related Art Among flat display panels for displaying information by utilizing the alignment state of a liquid crystal, etc., in an active matrix type liquid crystal display panel, as shown in a block diagram of FIG. Matrix 2
2. Source line drive circuit 12 and gate line drive circuit 21
Are formed on the same transparent substrate 11 to reduce the size, increase the definition, and reduce the cost of the display device. Here, the source line driving circuit 12 has a shift register 13, sample and hold circuits 17, 18, and 19, and video signal lines 14, 15, and 16, while a gate line driving circuit 21
Has a shift register 20 and a buffer circuit 23 as necessary. The pixel matrix 22 includes a plurality of source lines 26 and 27 connected to the source line driving circuit 12,
, A plurality of gate lines 24, 25 connected to the gate line driving circuit 21, and a plurality of pixels 32, 33,... Formed at the intersections of these gate lines and source lines.
Each of the pixels 32, 33,... Has a thin film transistor (TFT) 29 and a liquid crystal cell 30. Further, a clock signal line 34 to which a clock signal is to be input to the shift register 13 is provided on the side of the source line driving circuit 12.
On the other hand, on the side of the gate line driving circuit 21, a clock signal line 37 for inputting a clock signal to the shift register 20 is disposed. In addition, 35,
38 is a source line drive circuit 12 and a gate line drive circuit 2
1 is a start signal line for inputting a start signal.

Here, the shift registers 13 and 20 are 1
As shown in FIG. 14A, the unit shift register 1a driven by the clock signal CLA of the clock signal CKA or the unit shift register driven by the clock signal CLA * having the opposite phase to the clock signal CLA, per bit. 1b, these unit shift registers 1a,
1b are alternately arranged in the shift direction. Among these unit shift registers 1a and 1b, the unit shift register 1a includes one inverter 2 and two clocked inverters 3a and 4a, and the unit shift register 1b includes one inverter 2 and two clocked inverters 3a.
b, 3a. Inverter 2
Is, as shown in FIG. 14B, a p-type TFT 201 and n
It has a CMOS structure including the type TFT 202.
Further, the clocked inverters 3a and 4a correspond to FIG.
As shown in FIG. 14C, the clocked inverters 3b and 4b are composed of p-type TFTs 301a and 302a and n-type TFTs 401a and 402a and can be driven by a clock signal CLA. As shown in d), the p-type TFTs 301b and 302b and the n-type TFT 40
1b, 402b and the opposite phase clock signal C
It can be driven by LA *.

For this reason, in the conventional active matrix panel, for example, as shown in FIG. 15, in the shift register 81 of the source line driving circuit 80, the p-type TFTs 301a and 301 of the clocked inverters 3a and 4a are provided.
2a and n-type TFTs 401a and 402a are respectively provided in two rows of thin film transistor forming regions 803a and 804a arranged from the outer peripheral side of the substrate (in the direction of arrow X) toward the pixel matrix forming region (in the direction of arrow Y). Is formed.

[0005]

In a liquid crystal display panel having such a structure, the purpose is to improve the display quality.
Although the pixel pitch is being narrowed to achieve finer pixels, the pixel pitch is in a state defined by the unit cell pitch P11 of the source line drive circuit 80. Here, the clocked inverters 3a and 4a of the shift register 81 are 4
Whereas the analog switch unit 85 includes n TFTs for each unit cell of the source line drive circuit 80.
Are composed only of the type TFTs 85a, 85b,.
The inverter circuits 87a and 87b of the buffer circuit 87
Since each is composed of complementary TFTs, the unit cell pitch P11 of the source line drive circuit 80 is defined as the unit shift register formation pitch P12 of the shift register 81 having a high TFT formation density.

However, in the conventional active matrix panel, there is a problem that the pitch P11 (pixel pitch) of the unit cell of the source line driving circuit 80 cannot be reduced due to the structural limitation of the shift register 81. That is, in the ion implantation step of the manufacturing process of the shift register 81, the p-type transistors having different conductivity types in the thin film transistor forming regions 803a and 804a.
TFTs 301a, 302a and n-type TFTs 401a, 4
Since it is necessary to introduce impurities of the opposite conductivity type into the region where the second TFT 02a is formed, the p-type TFTs 301a and 301
It is necessary to provide a predetermined interval between 2a and n-type TFTs 401a and 402a, for example, an interval of 10 μm or more. Therefore, any of the thin film transistor formation regions 803
a and 804a also have an increased length in the side direction of the substrate (the direction of arrow Z).

Further, in order to improve the operation speed of the source line driving circuit, as shown in a source line driving circuit 90 shown in FIG. Two series of clock signal lines 93,
94, and the clock signal C supplied from it.
The shift register 91 is composed of the A-series shift register 91a and the B-series shift register 91 so that the KA and CKB can drive the shift shift register 91 in two series.
b may be divided into two series. However, even in this case, the thin film transistor forming region 903a on the outer peripheral side of the substrate (in the direction of arrow X) and the thin film transistor forming region 903b on the side of the pixel matrix forming region (in the direction of arrow Y) are limited by the ion implantation process. Since it is necessary to provide an interval of more than 10 μm between the p-type TFT and the n-type TFT having different conductivity types, each of the thin film transistor formation regions 903a and 904a has a length in the side direction of the substrate (the direction of arrow Z). The length dimension becomes long. Therefore, the pitch P12 at which the unit shift register is formed in the shift register 91 cannot be reduced. In FIG. 16, the clock signal lines 93, 94
Are clock signal lines 931 and 9 for supplying clock signals CLA and CLB to the shift register 91, respectively.
41, and clock signal lines 923 and 942 for supplying clock signals CLA * and CLB * having phases opposite to those of the clock signals CLA and CLB to the shift register 91, and the clock signals CKA (CLA and CLA *) And the clock signals CKB (CLB, CLB *) are 9
It has a deviation of 0 °.

[0008] In view of the above problems, an object of the present invention is to provide:
An object of the present invention is to realize an active matrix panel in which unit cells on a driving circuit side can be narrowed in pitch by optimizing an arrangement structure of thin film transistors constituting a shift register.

[0009]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention is directed to a parallel arrangement in which the phases are shifted from each other.
First and second transfer of first and second clock signals
Clock signal line and video signal line for transferring video signals
And a first clock signal adjacent to the first clock signal line.
Signal coming in from the first line via the first clock signal input line.
Each unit shift register is synchronized with one clock signal.
Output n first bit output signals out of phase in parallel
A first clock-specific shift register to be activated, and a first clock
In parallel with the shift register
The second clock signal line and the second clock signal line.
A second clock signal coming in via the clock signal input line
Each unit shift register is out of phase with each other in synchronization with the
A second clock which outputs m second bit output signals in parallel.
Through a bit-specific shift register and a first bit output line
Converting the video signal into a pixel area based on a first bit output signal;
N first bit-specific switches for drawing in
Switch means and a second bit output via a second bit output line.
The video signal based on a different signal of the pixel area
M second bitwise switch means for pulling into a line
And the second clock signal line has a first clock signal
The first and second vias are located closer to the pixel area than the line.
The switch means for each bit comprises a second clock signal line and a first clock signal line.
It is closer to the pixel area than the clock-specific shift register.
Drive circuit for an active matrix panel
Thus, each unit of the first and second clock-specific shift registers is
Phase shift registers respectively have first and second clocked
It has an inverter circuit, and each clocked inverter circuit
The first conductive type in which thin film transistors of the same conductive type are paired
Transistor forming region and second conductivity type transistor forming
The area is built separately from the second clock.
First clocked inverter circuit in shift register
Of the first conductivity type transistor forming region and the second clock
Second clocked inverter circuit in shift register
The pixel region is different from the column of the first conductivity type transistor
Notch near one end of the switch width and the second
Clocked Inverter in Clock-Specific Shift Register
Region for forming the second conductivity type transistor of the
Second clocked inverter in shift register by clock
In column difference and the second conductivity type DOO transistor forming region of the capacitor circuit
It is unevenly distributed near the other end of the pixel pitch width and is separated by the second clock.
First clocked inverter circuit in shift register
Of second conductive type transistor forming region and second clock
Second clocked inverter circuit in shift register
Adjacent to the second conductivity type transistor forming region
And in the second clock-specific shift register
Transistor of the first conductivity type of the first clocked inverter circuit
In the star formation area and the second clock-specific shift register
Of the first conductivity type of the second clocked inverter circuit
Separated from the star formation area by an empty area between multiple rows
And a first bit of the first clock-specific shift register.
Output line is the first conductivity of the second clock-specific shift register.
Through the type transistor forming region and the space region.
1 bit-dependent switch means, and
The second bit output line of the second clock-specific shift register is
The second conductivity type transistor of the second clock-specific shift register itself.
Second bit-by-bit switch means via a transistor forming region
Characterized by being connected to

Here, the first and second clock-specific shifts
The register is sandwiched between the first and second clock lines
Can be adopted .

In the middle of the first and second bit output lines,
And a second clock line and first and second bit-by-bit switches
It is preferable to provide a buffer circuit between the means.

The buffer circuit and the first and second clocks
When video signal lines are placed in parallel with the shift register
good.

The first clock signal lines are out of phase with each other.
Clock signals for transferring the first clock signal
And the second clock signal lines are out of phase with each other.
A plurality of clock signal lines for transferring a second clock signal
It is good.

[0014]

According to this structure, the phases are shifted from each other.
The first and second clock signals are generated by the first and second clock signals.
Since the shift register for each lock is driven, the drive circuit
High-speed operation can be achieved, and per bit
The area occupied by the unit shift register is the same as before
Also, the first and second clock-specific shift registers are arranged in parallel.
Is used to reduce the pitch of unit cells in the drive circuit.
Accordingly, the pixel pitch can be narrowed, and high definition can be realized.
In particular, the first conductive element forming one clocked inverter
Transistor forming region and second conductivity type transistor forming
The pixel pitch is narrow because the area is staggered.
It is possible to reduce the size and to make the regions of the mutual conductivity type
Bent interconnects between their overlaps
Can be connected as vertical wiring without passing through,
You can secure room. However, with such a layout
Means that the second conductive type transistor forming regions are close to adjacent columns.
Although there is an advantage to be able to
The vertical wiring of each shift register itself becomes congested
Output the first bit of the first clock-specific shift register.
This impairs the margin for passing force lines. However, the first conductivity type transformer
The areas where the registers are formed have an empty area between two or more columns.
Because of the separation, the first clock-specific shift register
A first bit output line is connected to a second shift register for each clock.
Through the first conductivity type transistor formation region and the space region
Connected to the first bit-by-bit switch means, and
The second bit output line of the second clock-specific shift register
The second conductivity type transistor of the second clock-specific shift register itself.
Second bit-by-bit switch means via a transistor forming region
, The internal wiring and the first and second bits
The output pitch is guaranteed to pass, and the pixel pitch is reduced.
Can appear. Therefore, high-speed operation of the drive circuit and pixel pitch
, The display quality can be improved .

[0015] In the present invention, the first and the second arranged in parallel.
And the second clock-dependent shift registers are arranged in parallel.
Because it is sandwiched between the first and second clock lines,
Shortening and equalizing the length of the first and second clock signal input lines
In addition to preventing the malfunction of the high-speed shift operation,
Instead of increasing the length of the second bit output line, the first bit
To the relatively long wiring length of the output line.
The freedom of design for equalizing the wiring resistance increases, and the second via
The bit output line also has a second clock like the first bit output line.
2nd clock signal line
Parasitics at the intersection due to equalizing the number of intersections with the signal line
Capability equalization can be realized, and the first and second bit output signals
It is possible to suppress the mutual timing shift and improve the display quality.
You. Depending on the intersection with the second clock signal line,
There is a possibility that noise etc. may be superimposed on the bit output signal
In the middle of the first and second bit output lines and the second
Between the clock line and the first and second bit-by-bit switch means;
By providing a buffer circuit between them, noise and other
Etc., and the deterioration of display quality can be prevented .

[0016]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

Embodiment 1 FIG. 1 is a block diagram showing the arrangement of thin film transistors and wiring layers on the source line drive circuit side of an active matrix panel (liquid crystal display panel) according to Embodiment 1 of the present invention, and FIG. FIG. 3 and FIG. 3 are circuit diagrams thereof. Here, since the overall configuration of the active matrix panel of this example is substantially the same as the block diagram shown in FIG. 13, in the following description, only the configuration of the source line driving circuit will be described in detail.

[0018] In these figures, the source line driving circuit 40 of the active matrix panel of the present embodiment, like the conventional source line driver circuit illustrated in FIG. 16, the driving method of the shift register 40 are two series of . The source line driving circuit 40 is formed on the same transparent substrate together with a pixel matrix and a gate line driving circuit (both not shown), and drives a display operation of each pixel of the pixel matrix.
Here, the source line driving circuit 40 is formed between the outer peripheral edge of the substrate and the pixel matrix forming region. In this example, the shift register 41 is provided on the first outer peripheral side (in the direction of arrow X) of the substrate. Shift register forming area 42a
And the second shift register forming area 42b on the pixel matrix forming area side (in the direction of arrow Y), the A-series shift register 41a (the first shift register 41a) including unit shift registers A1, A2, A3,. Shift register)
, And a B-series shift register 41b (first shift register) composed of unit shift registers B1, B2, B3,.... Among the clock signal lines that supply the clock signals CKA and CKB to the A-series and B-series shift registers 41a and 41b, the A-series clock signal line 43 (the first clock signal line 43) that supplies the clock signal CKA to the A-series shift register 41a. One clock signal line) is arranged in parallel at a position adjacent to the first shift register formation region 41a, and supplies a B-series clock signal line 44 (second clock signal line 44) that supplies a clock signal CKB to the B-series shift register 41b. Clock signal lines) are arranged in parallel at positions adjacent to the second shift register formation region 42b. Here, the A-series clock signal line 43
Are formed on the outer peripheral side (in the direction of arrow X) of the substrate with respect to the first shift register formation region 42a, and the B-series clock signal lines 44 are formed with respect to the second shift register formation region 42b with respect to the pixel matrix formation region. (In the direction of arrow Y). Further, the clock signal line 43 of the A series
And the B-series clock signal lines 44 are located at substantially equal distances from the corresponding first or second shift register formation regions 42a and 42b. Therefore, a clock signal input line 49a connecting the A-series clock signal line 43 and the A-series shift register 41a, and a clock signal input line connecting the B-series clock signal line 44 and the B-series shift register 41b. The wiring length of 49b is almost the same size,
The clock signals CKA and CKA are designed to have the shortest dimensions.
Synchronization does not occur in the KB.

The second shift register forming area 42
A bit signal output line for transmitting the bit signal output from the shift register 41 toward the analog switch 45 of the sample and hold unit on the pixel matrix formation region side (in the direction of arrow Y) with respect to b. A buffer circuit 47 which amplifies the bit signal and also reduces the influence of noise from the B-series clock signal line 44 intersecting the bit signal output line 46 is formed in the middle of the buffer circuit 47. And two inverters 47a and 47b. Here, a buffer circuit 47 to reduce the influence of noise from the B-series clock signal line 44
A resistor R parasitic on a high-resistance bit signal output line 46 formed of a polycrystalline silicon layer, and an interlayer insulating film 48 interposed between the bit signal output line 46 and the clock signal line 44 as an aluminum wiring layer. It is also possible to configure a buffer circuit using the parasitic capacitance C constituted by.

Also, a clocked gate or the like can be employed.

In this embodiment, the A-series clock signal lines 43 are connected to clock signals CLA and CLA having phases opposite to each other.
* Are transmitted from two clock signal lines 431 and 432, and the B-series clock signal line 44 is also composed of two clock signal lines 441 and 442 that transmit clock signals CLB and CLB * having phases opposite to each other. Have been.

Among these clock signal lines 43 and 44, odd-numbered unit shift registers A1, A3,..., B1, B3,.
, And clock signals CLA * and CLB * are input from clock signal lines 432 and 442 to even-numbered unit shift registers A2, A4,..., B2, B4. Here, as shown in FIG. 3, each of the A-series and B-series shift registers 41a and 41b has one inverter 2 and two clocked inverters 3a and 4a (clocked inverters 3b and 4b). , B1, B2, B3,..., B1, B2, B3,..., Of which odd-numbered unit shift registers A1, A3,. Are the clock signals CLA and CL of the clock signals CKA and CKB.
B, while the even-numbered unit shift registers A2, A4,..., B2, B4.
It is driven by clock signals CLA * and CLB * having a phase opposite to that of B. Here, the inverter 2 is shown in FIGS.
As shown in (b), the p-type TFT 201 and the n-type TFT 2
02, which is a CMOS structure. In addition, clocked inverters 3a and 4a correspond to FIG. 1 and FIG.
As shown in (c), two p-type TFTs 301a, 301
2a and n-type TFTs 401a and 402a, and can be driven by clock signals CLA and CLB, whereas the clocked inverters 3b and 4b, as shown in FIGS. Two p-type TFTs 30
1b and 302b and n-type TFTs 401b and 402b, and can be driven by clock signals CLA * and CLB * having opposite phases.

The clock signal CKA (clock signals CLA, CLA *) from the A-series clock signal line 83
And the phase of the clock signal CKB (clock signals CLB, CLB *) from the B-series clock signal line 84 are shifted by 90 ° as shown in the timing chart of FIG. Therefore, after the start signal DX is input, the odd-numbered unit shift registers A1, A3,... Of the A-series shift register 41a correspond to the bit signal 252 corresponding to the falling edge of the pulse of the clock signal CLA.
, The even-numbered unit shift registers A2, A4,... Of the A-series shift register 41a output the bit signal 254 in response to the falling edge of the pulse of the clock signal CLA *. Also, the shift register 4 of the B series
1b odd-numbered unit shift registers B1, B3,.
Outputs the bit signal 253 in response to the falling edge of the pulse of the clock signal CLB, and outputs the even-numbered unit shift registers B2 and B4 of the B-series shift register 41b.
.. Output a bit signal 255 in response to the falling edge of the pulse of the clock signal CLB *. Then, based on the bit signals 252 to 255, the analog switch unit 4
The respective analog switches 5 operate to hold the respective video signals V from the video signal lines (video1, video2, video3) on the respective source lines. Therefore, the actual transmission timing of the bit signal is increased without increasing the operation of the thin film transistor of the shift register 41, so that the operation speed of the source line driving circuit 40 can be increased.

The arrangement structure of each TFT in the source line drive circuit 40 of the active matrix panel having such a configuration will be described with reference to FIGS. 5 (a), 5 (b) and 6.
explain.

FIG. 5A is a configuration diagram showing the arrangement of each TFT in the unit shift register A1 of the A-system shift register 41a in the source line driving circuit 40 of the active matrix panel of the present embodiment. 6B is a circuit diagram thereof, and FIG. 6 is a plan view showing an arrangement relationship between each TFT and a wiring layer in the unit shift register B1 of the shift register 41b of the B series in the source line driving circuit 40.

In FIG. 5A and FIG. 5B, the unit shift register A1 has one inverter 2 and two clocked inverters 3a and 4a. Also p-type TFT3
01a and 302a and n-type TFTs 401a and 402a. Here, the p-type TFTs 301a and 302
Each of the thin film transistor forming regions 300a, 300b, and 300 in which a and n-type TFTs 401a and 402a are formed.
c, 300d are arranged in four rows from the outer peripheral side of the substrate toward the pixel matrix formation region side, and the thin film transistor formation regions 300a, 300b, 300c, 30
0d, one end of the thin film transistor forming region 300a where the p-type TFTs 301a and 302a are formed on the side of the thin film transistor forming clocked inverter 3a and one end of the thin film transistor forming region 300b where the n-type TFTs 401a and 402a are formed. While they are close to each other, a predetermined distance is provided between them, while the other ends are located in opposite directions. Similarly, the p-type TFTs 301a and 301a on the side of the clocked inverter 4a
Thin-film formation region 300c in which 02a is formed
And one end of the thin film transistor forming region 300d in which the n-type TFTs 401a and 402a are formed are close to each other, and a predetermined distance is provided between them. Are located in opposite directions. Here, the reason why the thin film transistor forming regions in which TFTs of different conductivity types are formed are unevenly distributed in different regions is that, in the manufacturing process of the p-type TFTs 301a and 302a and the n-type TFTs 401a and 402a, the TFTs are batched halfway. When the n-type and p-type TFTs are sequentially formed by making only the impurities to be ion-implanted into the silicon film different from each other, a region where the p-type impurities are ion-implanted and an n-type impurity are formed. This is because if the region to be ion-implanted is too close, it is contaminated with impurities of the opposite conductivity type, and a TFT having stable characteristics cannot be formed. However, if the interval is excessively widened, the pitch P2 of the unit shift registers A1, A2,... Will eventually be expanded, and the pitch P1 of the unit cells of the source line driving circuit 40 will also be expanded. Therefore, in the source line driving circuit 40 of the active matrix panel of the present example, the thin film transistors arranged in four columns from the outer peripheral side of the substrate (in the direction of arrow X) toward the pixel matrix formation region side (in the direction of arrow Y). Forming regions 300a to 300d are provided, and, among these thin film transistor forming regions, one end sides of thin film transistor forming regions in which thin film transistors of different conductivity types are formed are brought close to each other, and the other end sides are made opposite directions. , The length of the unit shift register A1 in the side direction (in the direction of arrow Z) of the substrate is reduced while unevenly distributing the thin film transistor forming regions in which TFTs of different conductivity types are formed in different regions. It is. The other unit shift registers A2, A3,..., B2, B3,. For example, as shown in FIG. 6, the unit shift register B1, and the connecting hole for the drain of the p-type TFT 302 a, and the connection hole with respect to the n-type TFT 401a, toward the outer peripheral edge of the substrate in the formation region of the pixel matrix identical The distance between the thin film transistor forming region 300a and the thin film transistor forming region 300b in the side direction of the substrate and the distance between the thin film transistor forming region 300d and the thin film transistor forming region 300c in the side direction of the substrate are reduced until the unit shift register A1, , B1, B2,..., The forming pitch P2 is narrowed. The formation position of the p-type TFT 201 constituting the inverter 2 is changed to the p-type TFT 301.
a, thin film formation region 3 on which 302a is formed
00a, 300c and n-type TFT
The formation position of the thin film transistor 202 is changed to the thin film transistor formation regions 300b and 300d where the n-type TFTs 401a and 402a are formed.
Accordingly, thin film transistor forming regions in which TFTs of different conductivity types are formed are unevenly distributed in different regions. Then, as shown in FIG. 1 and FIG.
The bits of the stars A1 and A2 are SP1 and SP3 are the shift registers.
Regions for forming p-type transistors of the transistors B1 and B2;
Connects to the corresponding analog switch via the space
And the bits of the shift registers B1 and B2.
Output lines SP0 and SP2 are connected to the shift registers B1 and B2 respectively.
Corresponding via the n-type transistor forming region.
Connected to a analog switch.

Further, in the source line driving circuit 40 of the active matrix panel of the present embodiment, as shown in FIG. 7, a sectional view taken along line VV of FIG. 6 is formed on the surface of the insulating transparent substrate 11. P for the silicon layer 103
Type impurity by ion implantation of clocked inverter 4a
P-type TFTs 301a and 302a are formed, of which the source 101a of the n-type TFT 301a and the n-type TFT
The drain 102a of the FT 302a is shared with the silicon region 103a into which a common high-concentration impurity is introduced,
The formation interval in the side direction of the substrate is further reduced. In other TFTs, the same region is shared by the source and drain of the TFT.
In FIG. 7, 104a and 105a are n-type TFTs.
Gate electrodes 301a and 302a made of polycrystalline silicon, of which a gate electrode 104a extends therefrom to form a clock signal input line 49b. On the other hand, 106a and 107a are aluminum wiring layers, and constitute source / drain wiring layers for supplying a drain potential and a source potential to the n-type TFTs 401a and 402a. FIG. 8 shows an arrangement structure of each TFT and a wiring layer in the buffer circuit 47 and the analog switch unit 45. As shown in the figure, the formation pitch P of the unit shift registers A1, A2,.
In response to the narrowing of the number 2, the pitch of the bit signal output line 46 therefrom is also narrowed, and the pitch P1 of the unit cell of the source line driving circuit 40 is also narrowed.

As described above, in the source line drive circuit 40 of the active matrix panel of this embodiment, the unit shift registers A1, A2,..., B1, B2,. Are formed in two shift register forming regions 42a and 42b arranged between the pixel region and the pixel matrix forming region side (in the direction of arrow Y), so that the unit cell pitch P1 of the source line driving circuit 40 is Is small. In the source line driving circuit 40, the unit shift register A having a high formation density of circuit elements is used.
, B2,..., B1, B2,..., P-type TFTs 301a, 302a, 3 constituting the clocked shift registers 3a, 3b, 4a, 4b.
01b, 302b and n-type TFTs 401a, 402
The formation regions of a, 401b, and 402b are arranged in four rows from the outer peripheral side of the substrate (in the direction of arrow X) toward the formation region of the pixel matrix (in the direction of arrow Y). While one end side of the formed thin film transistor forming region is brought close to each other,
Since the other end sides thereof are located in opposite directions, the unit shift registers A1, A2,..., B1, The length dimension of the substrate in the side direction (direction of arrow Z) of B2.
/ 3. Therefore, the formation pitch P of the unit shift registers A1, A2,.
2, the pitch of the unit cells of the source line drive circuit 40 is narrowed. For this reason, the pixels of the pixel matrix defined by the unit cell pitch P1 of the source line driving circuit 40 can be miniaturized to improve the display quality.

The shift register 41 supplies clock signals CKA (CLA, CLA *) and CKB (CLB, CLB).
*) A-series and B-series clock signal lines 4 for supplying
3 and 44, the A-series clock signal line 43 is arranged in parallel at a position adjacent to the first shift register formation area 42a, and the B-series clock signal line 44 is arranged in the second shift register formation area 42b. The clock signal input lines 49a, 4a from the clock signal lines 43, 44 to the shift register 41 are arranged in parallel at adjacent positions.
The wiring length of 9b is designed to be substantially the same dimension and the shortest dimension. Therefore, there is no problem that the clock signals CKA and CKB are out of synchronization due to a difference in wiring resistance or a difference in parasitic capacitance, so that the shift register 41 does not malfunction and the reliability of the active matrix panel is high.
The A-series clock signal line 43 is formed on the outer peripheral side of the substrate with respect to the first shift register formation region 42a, and the B-series clock signal line 44 is formed with a pixel matrix with respect to the second shift register formation region 42b. Since the clock signal input lines 49a and 49b do not pass through the first and second shift register forming regions 42a and 42b, the unit shift register A1 , B1, A2, B2,... Can be formed closer to each other.

[Embodiment 2] FIG. 9 is a block diagram of a source line driving circuit side of an active matrix panel (liquid crystal display panel) according to Embodiment 2 of the present invention. FIG. 9 shows the shift register and clock signal lines. Are shown. Here, since the entire configuration of the active matrix panel of this example is the same as the block diagram shown in FIG.
The description of the entire configuration is omitted. Further, among the shift register, the buffer circuit, and the analog switch section constituting the source line driving circuit, the configurations of the buffer circuit and the analog switch section are the same as those of the active matrix panel of the first embodiment. Since the circuit and the circuit elements constituting the analog switch section are the same as those of the active matrix panel of the first embodiment, the active matrix panel of this example will be described based only on the block diagram of FIG.

In FIG. 9, the source line driving circuit 50 of the active matrix panel of this embodiment is divided into four lines, and the source line driving circuit 50 is a pixel matrix and gate line driving circuit (neither is shown). And on the same transparent substrate to drive the display operation of each pixel of the pixel matrix. The source line driving circuit 50 is formed between the outer periphery of the substrate and the region where the pixel matrix is formed. The shift register 51 is formed of a first shift register on the outer periphery of the substrate (in the direction of arrow X). It is formed divided into a formation region 52a and a second shift register formation region 52b on the pixel matrix formation region side (in the direction of arrow Y). Of these first and second shift register formation areas 52a and 52b, the first shift register formation area 52a has unit shift registers A1,
A-series shift registers 51a composed of A2... And C-series shift registers 51c (first shift registers) composed of the unit shift registers C1, C2. In the register forming area 52b, a B-series shift register 51b including unit shift registers B1, B2,... And a D-series shift register 51d (second shift register) including unit shift registers D1, D2,. They are formed alternately.

Here, the A-series clock signal line 5 for supplying the clock signals CKA and CKC to the A-series shift register 51a and the C-series shift register 51c.
The 3rd and C series clock signal lines 54 (first clock signal lines) are arranged in parallel at positions adjacent to the first shift register formation region 51a, and the B series shift register 51b and the D series shift register A B-series clock signal line 55 and a D-series clock signal line 56 (second clock signal line) for supplying clock signals CKB and CKD to 51d are adjacent to the second shift register formation region 51b. Are arranged side by side.
The A-series clock signal line 53 and the C-series clock signal line 54 are connected to the first shift register formation region 52a.
Are formed on the outer peripheral side of the substrate (in the direction of arrow X), while the B-series clock signal lines 55 and D
The series clock signal line 56 is formed on the pixel matrix formation region side (the direction of arrow Y) with respect to the second shift register formation region 52b. Therefore, a clock signal input line 59a from the A-series clock signal line 53 (first clock signal line) to the A-series shift register 51a.
And the wiring length of the clock signal input line 59b from the B-series clock signal line 55 (second clock signal line) to the B-series shift register 51b are designed to have substantially the same and shortest dimensions. Has become easier. Similarly, the wiring length of the clock signal input line 59c from the C-series clock signal line 54 (first clock signal line) to the C-series shift register 51c and the D-series clock signal line 56 (second clock signal line) The line length of the clock signal input line 59d from the line D) to the D-series shift register 51d is also designed to be substantially the same dimension and the shortest dimension. Also,
The A-series clock signal line 53 and the C-series clock signal line 54 are close to and parallel to each other, and the B-series clock signal line 55 and the D-series clock signal line 56 are close to and parallel to each other. Therefore, the wiring lengths of all the clock signal input lines 59a, 59b, 59c, 59d have substantially the same dimensions.

The second shift register formation area 52
A bit for transmitting a bit signal from each unit shift register of the shift register 51 toward the analog switch section 65 of the sample hold section is located on the pixel matrix formation area side (in the direction of arrow Y) with respect to b. Signal line 6
6 are formed, and the bit signal is delayed at an intermediate position to reduce the influence of noise from the B-series clock signal line 55 and the D-series clock signal line 56 on the side where the bit signal output line 66 intersects. A buffer circuit 67 that also performs a function of performing the same is configured by two inverters and the like as in the first embodiment.

In this embodiment, each of the clock signal lines 53, 54, 55, and 56 is composed of two clock signal lines for supplying clock signals having phases opposite to each other. Of the shift registers 51a to 51d, odd-numbered unit shift registers A1, C1, B1,
D1,... And even-numbered unit shift registers A2, C
, B2, D2,... Are driven by clock signals having phases opposite to each other. Also, the clock signal line 5 of the A series
3, the phase of the clock signal CKB from the B-series clock signal line 55, the phase of the clock signal CKC from the C-series clock signal line 54, and the clock signal from the D-series clock signal line 56. C
The KD phase is shifted by 45 ° with respect to each other, so that driving in four series is possible. Therefore, the operation speed of the source line driving circuit 50 can be increased without increasing the frequency of the operation of the thin film transistor included in the shift register 51.

Also, in the source line driving circuit 50 of the active matrix panel of this embodiment, the unit shift register per bit shown in FIG. 5B, for example, the unit shift register A1 shown in FIG. It has one inverter 2 and two clocked inverters 3a and 4a, of which the clocked inverter 3a is shown in FIG.
As shown in (a), the outer peripheral side of the substrate (in the direction of arrow X)
, Four rows of thin film transistor forming regions 30 arranged in the direction from the pixel matrix forming region side (in the direction of arrow Y)
0a, 300b, 300c, and 300d. Here, the thin film transistor forming region 300a in which the p-type TFTs 301a and 302a are formed, and the n-type TFT
The thin film transistor forming region 300b in which 401a and 402a are formed, and the n-type T on the side of the clocked inverter 4a.
The thin film transistor forming region 300d where the FTs 401a and 402a are formed, and the p-type TFTs 301a and 302a
Are formed in the order of the thin film transistor forming regions 300c in which the thin film forming regions are formed.
0d, the thin film transistor forming region 300a in which TFTs of different conductivity types are formed is separated from the thin film transistor forming region 300b at a position close to the side direction of the substrate.
Od and the thin film transistor forming region 300c are also separated at a position close to the side direction of the substrate. .., B1, B2,...
・ It has the same structure.

For this reason, in the active matrix panel of this embodiment, similarly to the first embodiment, the thin film transistor formation region 300a and the thin film transistor formation region 300b
Between the thin film transistor forming region 300d and the thin film transistor forming region 300c.
, B1, B2 in the unit shift register A1, A2,..., B1, B2.
... The formation pitch P2 is narrowed. The shift register 71 further includes A-series and C-series shift registers 51a and 51c in a first shift register formation area 52a on the outer peripheral side of the substrate and a second shift register formation area 52b on the pixel matrix formation area side. And the B-series and D-series shift registers 51b, 51c are formed in parallel so that the source line driving circuit 50
The pitch P1 of the unit cell is narrowed. Therefore, the pixel pitch of the pixel matrix can be reduced, and the display quality can be improved. Here, the clock signal lines 53 to 56 of the A-series to D-series are arranged in parallel at positions adjacent to the corresponding shift register formation regions, and therefore, from the respective clock signal lines 53 to 56 to the shift register 41. Clock signal input lines 59a to 59d
Can be designed to have the same length and the shortest dimension between the series. Therefore, the clock signals CKA, CKB, CK caused by the difference in the wiring resistance or the difference in the parasitic capacitance are generated.
There is no occurrence of synchronization deviation between C and CKD. Therefore, no malfunction occurs in the shift register 51, and the reliability of the active matrix panel is high. Moreover, since the shift register 41 is driven in four lines, the operation speed of the source line driving circuit 50 can be further increased.

Third Embodiment FIG. 10 is a block diagram showing the arrangement of thin film transistors and wiring layers on the source line drive circuit side of an active matrix panel (liquid crystal display panel) according to a third embodiment of the present invention, and FIG. FIG. 12 is a circuit diagram thereof. The overall configuration of the active matrix panel of this example is also the same as that shown in the block diagram of FIG. 13, and a description of the overall configuration will be omitted. Further, among the shift register, the buffer circuit, and the analog switch section constituting the source line driving circuit, the configuration of the buffer circuit and the analog switch section is the same as that of the active matrix panel of the first embodiment.
Since the circuit elements constituting the buffer circuit and the analog switch section are the same as those of the active matrix panel of the first embodiment, FIG. 10 shows only the structure on the shift register side.

In these figures, the source line driving circuit 70 of this example is a one-line driving system, and the source line driving circuit 70 is provided together with a pixel matrix and a gate line driving circuit (both are not shown). It is formed on the same transparent substrate and drives the display operation of each pixel of the pixel matrix.
Further, the source line driving circuit 70 is formed between the outer peripheral edge of the substrate and the region where the pixel matrix is formed. In this example, the shift register 71 is formed of the first shift register on the outer peripheral side of the substrate. The region 72a and the second shift register formation region 72 on the pixel matrix formation region side
and b. That is, of the first and second shift register formation regions 72a and 72b, the first shift register formation region 72a has a unit shift register A driven by the clock signal CKA.
A first shift register 7 composed of 1, A4, A5,.
1a, a second shift register 71b including unit shift registers A2, A3, A6,... Driven by the same clock signal CKA is formed in the second shift register formation area 72b. I have.

Here, a first clock signal line 73 for supplying a clock signal CKA to the first shift register 51a.
Are arranged in parallel at positions adjacent to the first shift register formation area 71a, while the second clock signal line 74 for supplying the clock signal CKA to the second shift register 71b is connected to the second shift register formation area 71a. It is arranged in parallel at a position adjacent to the region 71b. Also, the first
Clock signal line 73 is formed on the outer peripheral edge side (in the direction of arrow X) of the substrate with respect to first shift register formation region 72a, and second clock signal line 74 is formed with respect to second shift register formation region 72b. It is formed on the formation area side of the pixel matrix (the direction of arrow Y). Further, the wiring length of the clock signal input line 79a from the first clock signal line 73 to the first shift register 71a, and the wiring length of the clock signal input line 79b from the second clock signal line 74 to the second shift register 71b. The wiring length is designed to have the same size and the shortest size. Further, the bit signal from the shift register 71 is directed toward the analog switch unit 75 (the pixel matrix side) on the pixel matrix formation region side (the direction of arrow Y) with respect to the second shift register formation region 72b. Signal line 7 for transmission
6 is formed, and a buffer circuit 77 which also delays the bit signal to reduce the influence of noise from the second clock signal line 74 where the bit signal output line 76 intersects is provided at an intermediate position thereof. As in the first embodiment, it is configured by two inverters and the like. Note that also in this example, the first and second shift registers 71a and 71b
Are composed of the same circuit elements as those of the first embodiment, while both of the clock signal lines 73 and 74 are provided with two clock signal lines 731 and 721 for supplying clock signals CLA and CLA * having phases opposite to each other. 732, 741, and 742, the first shift register 71a and the second shift register 71a are connected to clock signals CLA,
It can be driven by CLA *. Here, the first
And both the second clock signal lines 73 and 74
The first and second clock signal lines 73 and 74 can be configured by two clock signal lines corresponding to clock signals CLA and CLA * having opposite phases. , Clock signal line 73,
The parasitic capacitance and the like between 74 are made equivalent to prevent the clock signal on one side from being delayed as compared with the clock signal on the other side.

Also, in the source line driving circuit 50 of this embodiment, as shown in FIGS. 5A and 5B, a unit shift register per bit, for example, a clocked inverter of the unit shift register A1 3a, four rows of thin film transistor forming regions 300a, 300b, 300c, arranged from the outer peripheral side of the substrate (in the direction of arrow X) toward the pixel matrix forming region (in the direction of arrow Y).
It is formed at 300d. These thin film transistor forming regions 300a to 300d are
The thin film transistor forming region 300a where the p-type TFTs 301a and 302a on the side a are formed, and the n-type TFT 40
Thin film transistor forming region 300b in which 1a and 402a are formed, n-type TFT on the side of clocked inverter 4a
The thin film transistor forming region 300d in which 401a and 402a are formed and the thin film transistor forming region 300c in which p-type TFTs 301a and 302a are formed are arranged in this order, and one of the thin film transistor forming regions in which thin film transistors of different conductivity types are formed. The end sides are close to each other, while their other end sides are located in opposite directions. That is, the thin film transistor forming region 300 in which TFTs of different conductivity types are formed
a and the thin film transistor formation region 300b are separated at a position close to the side direction of the substrate, and similarly, the thin film transistor formation region 300d and the thin film transistor formation region 300c are separated at a position close to the side direction of the substrate. It is. Further, the other unit shift registers A2,
A3... Have the same structure.

Therefore, in the active matrix panel of this embodiment, as in the first embodiment, the thin film transistor formation region 300a and the thin film transistor formation region 300b
Between the thin film transistor forming region 300d and the thin film transistor forming region 300c.
Are narrowed, the pitch P2 of the unit shift registers A1, A2,... Is narrowed, and the pitch P1 of the unit cells of the source line driving circuit 70 is narrowed. The shift register 71 includes a first shift register formation area 72a on the outer peripheral side of the substrate and a second shift register formation area 72a on the pixel matrix formation area side.
b, the pitch P1 of the unit cells of the source line drive circuit 70 is further narrowed. Therefore, the pixel pitch of the pixel matrix can be reduced, and the display quality can be improved. Here, the first clock signal line 73 is arranged in parallel at a position adjacent to the first shift register formation region 72a,
Since the second clock signal line 74 is arranged in parallel at a position adjacent to the second shift register forming region 72b, the shift register 4 is connected to each of the clock signal lines 73 and 74.
The wiring lengths of the clock signal input lines 79a and 79b up to 1 are designed to have the same size and the shortest size between the series. For this reason, the clock signal CKA does not lose synchronization due to a difference in wiring resistance or a difference in parasitic capacitance. Therefore, no malfunction occurs in the shift register 71, and the reliability of the active matrix panel is high.

The arrangement structure of the thin film transistor having the above structure can be adopted also on the gate line driving circuit side.

[0043]

As described above, in the active matrix panel according to the present invention, the first matrix having the phases shifted from each other.
The first and second clock signals are generated by the first and second clock signals.
The shift register is driven by the
High-speed operation, and a single bit per bit.
Even if the occupied area of the shift register is the same as
The first and second clock-specific shift registers are arranged in parallel.
The unit pitch of the drive circuit
Pixel pitch can be narrowed, and high definition can be realized. Special
The first conductivity type forming one clocked inverter
Transistor formation region and second conductivity type transistor formation region
The pixel pitch is narrow because the area is staggered.
Between the conductive type regions.
Now, bend the interconnect at the overlap
Can be connected as vertical wiring without any
You can secure a margin. However, with such a layout
Means that the second conductive type transistor forming regions are close to adjacent columns.
Although there is an advantage to be able to
The vertical wiring of each shift register itself becomes congested
Output the first bit of the first clock-specific shift register.
This impairs the margin for passing force lines. However, the first conductivity type transformer
The areas where the registers are formed have an empty area between two or more columns.
Because of the separation, the first clock-specific shift register
A first bit output line is connected to a second shift register for each clock.
Through the first conductivity type transistor formation region and the space region
Connected to the first bit-by-bit switch means, and
The second bit output line of the second clock-specific shift register
The second conductivity type transistor of the second clock-specific shift register itself.
Second bit-by-bit switch means via a transistor forming region
, The internal wiring and the first and second bits
The output pitch is guaranteed to pass, and the pixel pitch is reduced.
Can appear. Therefore, high-speed operation of the drive circuit and pixel pitch
, The display quality can be improved .

In the present invention, the first and the second
And the second clock-dependent shift registers are arranged in parallel.
Because it is sandwiched between the first and second clock lines,
Shortening and equalizing the length of the first and second clock signal input lines
In addition to preventing the malfunction of the high-speed shift operation,
Instead of increasing the length of the second bit output line, the first bit
To the relatively long wiring length of the output line.
The freedom of design for equalizing the wiring resistance increases, and the second via
The bit output line also has a second clock like the first bit output line.
2nd clock signal line
Parasitics at the intersection due to equalizing the number of intersections with the signal line
Capability equalization can be realized, and the first and second bit output signals
It is possible to suppress the mutual timing shift and improve the display quality.
You. Depending on the intersection with the second clock signal line,
There is a possibility that noise etc. may be superimposed on the bit output signal
In the middle of the first and second bit output lines and the second
Between the clock line and the first and second bit-by-bit switch means;
By providing a buffer circuit between them, noise and other
Etc., and the deterioration of display quality can be prevented .

[0045]

[0046]

[0047]

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an arrangement of components of a two-system source line driving circuit in an active matrix panel according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a source line driving circuit shown in FIG.

FIG. 3 is a circuit diagram of the source line driving circuit shown in FIG.

FIG. 4 is a timing chart of signals input to and output from each unit of the source line driving circuit shown in FIG. 1;

5A is a configuration diagram showing an arrangement of each component in a unit shift register of the shift registers of the source line driving circuit shown in FIG. 1, and FIG. 5B is a circuit diagram thereof.

6 is a plan view showing an arrangement of each component in a shift register of the source line driving circuit shown in FIG.

FIG. 7 is a sectional view taken along line VV in FIG. 6;

8 is a plan view showing an arrangement of each component in an analog switch section of the source line driving circuit shown in FIG. 1;

FIG. 9 is a block diagram of four lines of source line driving circuits in the active matrix panel according to the second embodiment of the present invention.

FIG. 10 is a configuration diagram illustrating an arrangement of components of a series of source line driving circuits in an active matrix panel according to a third embodiment of the present invention.

11 is a block diagram of the source line driving circuit shown in FIG.

12 is a circuit diagram of the source line driving circuit shown in FIG.

FIG. 13 is a block diagram illustrating an overall configuration of an active matrix panel.

14A is a circuit diagram of a shift register, FIG. 14B is a configuration diagram of the inverter, and FIGS. 14C and 14D are configuration diagrams of the clocked inverter.

FIG. 15 is a configuration diagram showing an arrangement of components of a series of source line driving circuits in a conventional active matrix panel.

FIG. 16 is a configuration diagram showing an arrangement of respective components of two lines of source line driving circuits in a conventional active matrix panel.

[Explanation of symbols]

11 Transparent substrate 12, 40, 50, 70, 80, 90 Source line driving circuit 13, 20, 41, 51, 71, 81, 91 Shift register 17, 18, 19 Sample hold circuit 21 gate line drive circuit 22 pixel matrix 24, 25 gate line 26, 27, 28 source line 29 thin film transistor 30 liquid crystal cell 34, 37, 83, 84, 93, 94... Clock signal lines 41a, 51a... A series shift register (first shift register) 41b, 51b... B series shift register (second shift register) 42a , 52a, 72a... Second shift register forming area 42b, 52b, 72b... Second shift register forming area 43, 53. Lines (first clock signal lines) 44, 55 ... B-series clock signal lines (second clock signal lines) 45, 65, 75, 85 ... analog switch units 46, 66, 66a, 66b, 76, 86 ... bit signal output lines 47, 67, 77 ... buffer circuits 49a, 49b, 59a to 59d, 79a, 79b, 8
9a, 89b... Clock signal input line 51c... C series shift register (first shift register) 51d... D series shift register (second shift register) 54... C series clock Signal line (first clock signal line) 56... D-series clock signal line (second clock signal line) 73... First clock signal line 74. 300b, 300c, 300d: Thin film transistor formation region

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/133 550 G09F 9/30 338 G09G 3/36

Claims (6)

(57) [Claims] 1. A parallel arrangement wherein the phases are shifted from each other.
First and second transfer of first and second clock signals
Clock signal line and video signal line for transferring video signals
And a first clock signal adjacent to the first clock signal line.
Signal coming in from the first line via the first clock signal input line.
Each unit shift register is synchronized with one clock signal.
Output n first bit output signals out of phase in parallel
A first clock-specific shift register to be activated, and a first clock
In parallel with the shift register
The second clock signal line and the second clock signal line.
A second clock signal coming in via the clock signal input line
Each unit shift register is out of phase with each other in synchronization with the
A second clock which outputs m second bit output signals in parallel.
Through a bit-specific shift register and a first bit output line
Converting the video signal into a pixel area based on a first bit output signal;
N first bit-specific switches for drawing in
Switch means and a second bit output via a second bit output line.
The video signal based on a different signal of the pixel area
M second bitwise switch means for pulling into a line
And the second clock signal line has a first clock signal
The pixel than the line and the first clock-specific shift register
A first and second bit-by-bit switch located near the region;
The stage is closer to the pixel area than the second clock signal line.
Drive circuit for an active matrix panel
Therefore, each unit shift of the first and second clock-specific shift registers is performed.
Registers are respectively the first and second clocked inverters.
And each clocked inverter circuit has the same conductivity.
Conductivity type transistors that combine thin film transistors of different types
Transistor formation region and second conductivity type transistor formation region
And the first clock in the second clock-specific shift register.
Region for forming the first conductivity type transistor of the inverter circuit
Second clock in second clock-specific shift register
Region for forming the first conductivity type transistor of the inverter circuit
Is unevenly distributed near one end of the pixel pitch width
In both cases, the first clock in the second clock-specific shift register is used.
Formation of second conductivity type transistor of locked inverter circuit
Region and the second clock in the second clock-specific shift register.
Formation of second conductivity type transistor of locked inverter circuit
It is unevenly distributed near the other end of the pixel pitch width in a row different from the area,
First clock in second clock-specific shift register
Region for forming the second conductivity type transistor of the inverter circuit and
Second clock in second clock-specific shift register
Region for forming the second conductivity type transistor of the inverter circuit and
Are adjacent to each other in different columns, and are shifted by the second clock.
Of the first clocked inverter circuit in the register
One-conductivity-type transistor formation region and second clock-specific shift
Of the second clocked inverter circuit in the
Space between two or more columns different from the one conductivity type transistor formation region
A first clock-specific shift register
The first bit output line of the second shifter
A first conductivity type transistor forming region of the transistor and the space
Connected to the first bit-by-bit switch means via the
And the second clock-dependent shift register
Is the second clock-specific shift register itself
Of the second bit through the second conductive type transistor formation region of
A switch connected to switch means
Driver circuit for the active matrix panel . 2. The active matrix according to claim 1,
In the panel driving circuit, the first and second clocks
A shift register is sandwiched between the first and second clock lines.
A drive circuit for an active matrix panel, which is characterized by being provided. 3. The active matrix according to claim 2,
In the panel driving circuit, the first and second bits
In the middle of an output line, the second clock line and the first
And a buffer circuit between the second bit-dependent switch means and
A driving circuit for an active matrix panel, wherein a driving circuit is interposed . 4. The acty according to claim 2 or claim 3.
In the driving circuit of the sub-matrix panel, the buffer
Circuit and the first and second clock-dependent shift registers;
Wherein the video signal lines are arranged in parallel . 5. The method according to claim 1, wherein:
In the drive circuit of the active matrix panel described
The first clock signal lines are connected to the first
Multiple clock signal lines for transferring
And the second clock signal lines are shifted in phase from each other by the second clock signal line.
A plurality of clock signal lines der for transferring the clock signal
Driving the active matrix panel, characterized in that that
Circuit . 6. The method according to claim 1, wherein:
Using the drive circuit of the specified active matrix panel
The active matrix panel characterized by comprising Te.