JP5208277B2 - Scanning signal line driving circuit and display device including the same - Google Patents

Description

  The present invention relates to a scanning signal line driving circuit of an active matrix display device, and more particularly to a shift register included in the scanning signal line driving circuit.

  Conventionally, a plurality of gate bus lines (scanning signal lines) and a plurality of source bus lines (video signal lines) are arranged in a lattice pattern, and a plurality of pixel forming portions are arranged in a matrix corresponding to the intersections of these signal lines. An active matrix type display device is known. Each pixel forming unit includes a thin film transistor (TFT) that is a switching element, a pixel capacitor for holding a pixel value, and the like. The gate terminal of the thin film transistor is connected to the gate bus line passing through the corresponding intersection, and the source terminal is connected to the source bus line passing through the intersection. The active matrix display device is further provided with a gate driver (scanning signal line driving circuit) for driving the gate bus line and a source driver (video signal line driving circuit) for driving the source bus line.

  The video signal indicating the pixel value is transmitted by the source bus line, but one source bus line cannot transmit the video signal indicating the pixel value for a plurality of rows at a time (simultaneously). For this reason, the writing of the video signal to the pixel capacitance included in the pixel formation portion is sequentially performed row by row. Therefore, in order to sequentially select a plurality of gate bus lines for a predetermined period, a gate driver including a plurality of stages of shift registers is used.

  The shift register operates based on the clock signal. This clock signal is given to each stage of the shift register from a clock signal trunk line disposed at the outer edge of the panel. The clock signal is usually supplied to a plurality of thin film transistors included in the shift register. For this reason, a layout area for the shift register is required between the arrangement area of the clock signal trunk wiring and the arrangement area of the pixel formation portion. This is one of the factors that increase the layout area of the shift register. In particular, in a display device including a shift register that operates based on a large number of clock signals, an increase in the frame area of the panel becomes a problem. In addition, when a plurality of panels are cut out from the mother glass, a shift register is formed in the frame area if the panel can be used as a frame area in a relatively narrow range (for example, a small-sized panel). Becomes difficult. For this reason, the panel is wasted, and the yield is significantly reduced.

  The following prior art documents are known in relation to the present invention. Patent Documents 1 to 7 disclose the configuration of a gate driver including a shift register. In these documents, a clock signal necessary for the operation of the shift register is applied to each stage of the shift register from the clock signal trunk line as shown in FIG. For example, in Patent Document 1, when connecting the trunk wiring and each stage of the gate driving unit, as shown in FIG. 27, a gate driving unit is provided by providing a contact (rectangular rectangle) and a zigzag lead-out line. It is disclosed that the interval between the signal lines is reduced. Further, Patent Document 7 discloses that a clock lead-out wiring from a clock signal trunk wiring is connected to two adjacent stages in one shift register and the clock signal is shared by these two stages. (See FIG. 4 and FIG. 6 of Patent Document 7). The same contents are described in Patent Document 6 (see FIGS. 3 and 5 of Patent Document 6). In Patent Documents 6 and 7, there are two types (CK1, CK2) of clock signals necessary for the operation of the shift register, and the number of clock lead-out lines is one per shift register.

Japanese Unexamined Patent Publication No. 2008-26865 Japanese Unexamined Patent Publication No. 2004-157508 International Publication No. 2003/87921 Pamphlet Japanese Unexamined Patent Publication No. 2008-146079 Japanese Unexamined Patent Publication No. 2007-200452 Japanese Unexamined Patent Publication No. 2006-39524 Japanese Unexamined Patent Publication No. 2007-316642

  By the way, in recent years, the demand for downsizing of the panel is increasing, and the reduction of the frame area is required. However, as described above, since the layout area of the shift register increases in the conventional configuration, there is a limit in reducing the frame area of the panel. In this regard, Patent Document 1 discloses a configuration in which the interval between the signal lines of the gate driving unit is narrowed. In order to sufficiently protect the gate driver (gate driver), it is preferable to cover (cover) the gate driver with a liquid crystal panel sealing material. However, in the configuration disclosed in Patent Document 1, when the number of wirings of the gate driving unit increases, the range in which the sealing material is applied becomes small, and the gate driving unit is not sufficiently protected.

  Patent Documents 6 and 7 disclose a configuration in which the number of clock lead-out lines is less than the number of clocks necessary for the operation of the shift register. These documents disclose a gate driving unit including one shift register. However, since a large liquid crystal panel has a heavy load, it is difficult to drive with a single shift register, and two or more shift registers are required.

  Therefore, an object of the present invention is to reduce the frame area of a panel in a display device (for example, a display device having a large panel) including a scanning signal line driver circuit including a plurality of shift registers.

A first aspect of the present invention is a scanning signal line driving circuit for driving a plurality of scanning signal lines arranged in a display unit of a display device,
Each is composed of a plurality of stages, a plurality of shift registers that sequentially shift pulses applied to the first stage based on a plurality of clock signals applied to each stage, and drive the scanning signal lines;
A plurality of signal lines for transmitting the clock signal, and a clock signal trunk line disposed on the opposite side of the display unit with respect to the shift register;
The plurality of shift registers are disposed on one side of the display unit,
The plurality of shift registers include an odd-numbered stage shift register composed of only odd-numbered stages, and an even-numbered stage shift register composed of only even-numbered stages,
Each stage of the shift register receives a part of the clock signal from the clock signal trunk and receives the remaining clock signal from another shift register.

According to a second aspect of the present invention, in the first aspect of the present invention,
Each stage of the shift register operates based on four clock signals.

According to a third aspect of the present invention, in the first aspect of the present invention,
Each stage of the shift register receives the remaining clock signal from a stage adjacent to another shift register.

According to a fourth aspect of the present invention, in the first aspect of the present invention,
Each stage of the shift register includes a charge control switching element that charges a corresponding scanning signal line based on a clock signal received from the clock signal trunk line,
The phase of the remaining clock signal is shifted by 90 degrees from the phase of the clock signal applied to the charge control switching element.

According to a fifth aspect of the present invention, in the first aspect of the present invention,
Each stage of the shift register includes a contact for supplying the partial clock signal to both a front stage and a rear stage of another shift register.

According to a sixth aspect of the present invention, in the first aspect of the present invention,
Each stage of the shift register has a contact for supplying the partial clock signal to the front stage of the other shift register, and a contact for supplying the partial clock signal to the rear stage of the other shift register. The two contacts are arranged at positions where they are in contact with each other.

According to a seventh aspect of the present invention, in the first aspect of the present invention,
The shift register has a dummy stage that gives the clock signal received from the clock signal trunk wiring to the first stage as it is, and a dummy stage that gives the clock signal received from the clock signal trunk wiring to the last stage as it is It has what is possessed.

According to an eighth aspect of the present invention, in the seventh aspect of the present invention,
The dummy stage includes only components necessary for transmitting a clock signal received from the clock signal trunk line among the components of each stage of the shift register.

According to a ninth aspect of the present invention, in the fourth aspect of the present invention,
Each stage of the shift register further includes a thin film transistor in which a drain electrode or a source electrode is connected to a gate terminal of the charge control switching element,
The thin film transistor is a multi-channel thin film transistor and is formed of an oxide semiconductor.
A tenth aspect of the present invention is a display device including a display unit including a plurality of scanning signal lines and a scanning signal line driving circuit according to any one of the first to ninth aspects.

An eleventh aspect of the present invention is a scanning signal line driving circuit for driving a plurality of scanning signal lines arranged in a display unit of a display device,
Each is composed of a plurality of stages, a plurality of shift registers that sequentially shift pulses applied to the first stage based on a plurality of clock signals applied to each stage, and drive the scanning signal lines;
A plurality of signal lines for transmitting the clock signal, and a clock signal trunk line disposed on the opposite side of the display unit with respect to the shift register;
The plurality of shift registers are disposed on one side of the display unit,
The plurality of shift registers include an odd-numbered stage shift register composed of only odd-numbered stages, and an even-numbered stage shift register composed of only even-numbered stages,
Each stage of the shift register receives a part of the clock signal from the clock signal trunk, receives another part of the clock signal from the other shift register, and receives the remaining clock signal from the other stage of the same shift register. It is characterized by receiving.

The first and second aspect of the present invention, in the first one aspect of the present invention,
Each stage of the shift register operates based on four clock signals.

The first third aspect of the present invention, in the first one aspect of the present invention,
Each stage of the shift register receives the other part of the clock signal from an adjacently arranged stage of the other shift register, and receives the remaining clock signal from the previous stage or the next stage of the same shift register. To do.

The first fourth aspect of the present invention, in the first one aspect of the present invention,
Each stage of the shift register includes a charge control switching element that charges a corresponding scanning signal line based on a clock signal received from the clock signal trunk line,
The phase of the other part of the clock signal is shifted by 90 degrees from the phase of the clock signal applied to the charge control switching element, and the phase of the remaining clock signal is shifted by 180 degrees.

First fifth aspect of the present invention, in the first one aspect of the present invention,
Each stage of the shift register is a contact for supplying the part of the clock signal to at least two of the front stage of another shift register, the rear stage of the other shift register, and the other stage of the same shift register. It is characterized by including.

Aspect of the first 6 of the present invention, in the first one aspect of the present invention,
Each stage of the shift register has a contact for supplying the partial clock signal to a front stage of another shift register, and a contact for supplying the partial clock signal to a rear stage of the other shift register; A contact for supplying the part of the clock signal to the other stage of the same shift register, and at least two of the three contacts are arranged in contact with each other.

Aspect of the first 7 of the present invention, in the first one aspect of the present invention,
The shift register has a dummy stage that gives the clock signal received from the clock signal trunk wiring to the first stage as it is, and a dummy stage that gives the clock signal received from the clock signal trunk wiring to the last stage as it is It has what is possessed.

Aspect of the first 8 of the present invention, in the first 7 of the aspect of the present invention,
The dummy stage includes only components necessary for transmitting a clock signal received from the clock signal trunk line among the components of each stage of the shift register.

A nineteenth aspect of the present invention is the fourteenth aspect of the present invention,
Each stage of the shift register further includes a thin film transistor in which a drain electrode or a source electrode is connected to a gate terminal of the charge control switching element,
The thin film transistor is a multi-channel thin film transistor and is formed of an oxide semiconductor.
A twentieth aspect of the present invention is a display device including a display unit including a plurality of scanning signal lines and a scanning signal line driving circuit according to any one of the first to first nineteenth aspects.

According to the first or the first one aspect of the present invention, the number of wires connecting the respective stages of the clock signal main lines and the shift register is less than before. This reduces the wiring area for the clock signal at each stage of the shift register. In addition, since the load capacity per clock signal trunk line is smaller than the conventional one, the mutual interference due to the clock signal can be suppressed, and the waveform dullness of the clock signal can be reduced. Therefore, the size of a switching element (for example, a thin film transistor) included in the shift register can be made smaller than before. Furthermore, it is not necessary to newly provide components other than signal lines for transmitting a clock signal between each stage of the shift register and another shift register (or another stage of the same shift register). . From the above, the layout area for the shift register on the panel of the display device can be reduced, and the frame area of the panel can be reduced.

According to the second or first and second aspect of the present invention, in the scanning signal line drive circuit having a shift register that operates based on four clock signals, the same effect as the first or the first 1 aspect is obtained .

According to the third or the first third aspect of the present invention, using a relatively short signal line, it is possible to provide a clock signal from the other clock signal main lines to each stage of the shift register. For this reason, it is possible to realize a scanning signal line drive circuit having the same effects as those of the first or first aspect with a relatively simple configuration.

According to the fourth or first fourth aspect of the present invention, in the scanning signal line drive circuit having a shift register that operates based on a plurality of clock signals whose phases are shifted 90 degrees from each other, the first or the first 1 aspect The same effect can be obtained.

According to the fifth or first fifth aspect of the present invention, by realizing all or part of the necessary contacts in one contact, and reduce the occupied area of the contact at each stage of the shift register, the panel The frame area can be effectively reduced.

According to the sixth or aspects of the first 6 of the present invention, than when located away a plurality of contacts, it is possible to reduce the contact resistance.

Seventh present invention, the eighth, according to the aspect of the first 7 or the first 8, the circuit configuration of each stage of the shift register is the same, since the parasitic capacitance is almost equal, the waveform of the clock signal dampened substantially is Be the same. Accordingly, the shift register can be stably operated.

According to the ninth or nineteenth aspect of the present invention, it is possible to prevent the leakage current from flowing through the thin film transistor and the potential of the gate terminal of the charge control switching element from fluctuating.
According to the tenth or twentieth aspect of the present invention, a display device including a scanning signal line drive circuit that achieves the same effects as any one of the first to ninth or first to ninth aspects is realized. can do.

1 is a block diagram illustrating a configuration of a liquid crystal display device according to a first embodiment of the present invention. FIG. 2 is a block diagram illustrating a schematic configuration of a gate driver included in the liquid crystal display device illustrated in FIG. 1. It is a block diagram which shows the detail of the gate driver which concerns on 1st Embodiment. FIG. 4 is a circuit diagram of a bistable circuit included in the gate driver shown in FIG. 3. 4 is a timing chart of a gate clock signal input to the gate driver shown in FIG. 3. 4 is a timing chart showing a change in potential of a bistable circuit included in the gate driver shown in FIG. 3. 4 is a timing chart of scanning signals output from the gate driver shown in FIG. 3. It is a schematic diagram which shows the layout of the gate driver shown in FIG. It is a schematic diagram which shows the layout of the conventional gate driver. It is a schematic diagram which shows the layout of the conventional bistable circuit. It is a schematic diagram which shows the layout of the bistable circuit after moving an element. It is a schematic diagram which shows the layout of the bistable circuit which concerns on 1st Embodiment. It is a figure for demonstrating the effect of the gate driver which concerns on 1st Embodiment. It is a schematic diagram which shows the load capacity | capacitance in the gate driver which concerns on 1st Embodiment. It is a schematic diagram which shows the load capacity | capacitance in the conventional gate driver. It is a block diagram which shows the structure of the liquid crystal display device which concerns on the modification of 1st Embodiment. FIG. 10 is a circuit diagram of a bistable circuit included in a gate driver according to another modification of the first embodiment. It is a top view of multichannel TFT. It is sectional drawing of a multi-channel TFT. It is an equivalent circuit diagram of a multi-channel TFT. It is a block diagram which shows the detail of the gate driver which concerns on the 2nd Embodiment of this invention. It is a schematic diagram which shows the layout of the gate driver shown in FIG. It is a block diagram which shows the detail of the gate driver which concerns on the 3rd Embodiment of this invention. FIG. 20 is a circuit diagram of a bistable circuit included in the gate driver shown in FIG. 19. It is a block diagram which shows the detail of the gate driver which concerns on a reference example. FIG. 22 is a circuit diagram of a bistable circuit included in the gate driver shown in FIG. 21. It is a figure which shows arrangement | positioning of the contact in the gate driver which concerns on the modification of 1st-3rd embodiment. It is a block diagram which shows the detail of the gate driver which concerns on the 4th Embodiment of this invention. FIG. 25 is a schematic diagram showing a layout of the gate driver shown in FIG. 24. It is a figure which shows the supply form of the clock signal in a gate driver. FIG. 10 is a layout diagram of a gate driving unit disclosed in Patent Document 1.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the liquid crystal display device according to the first embodiment of the present invention. A liquid crystal display device shown in FIG. 1 includes a power source 1, a DC / DC converter 2, a display control circuit 3, a gate driver (scanning signal line driving circuit) 4, a source driver (video signal line driving circuit) 5, and a common electrode driving circuit 6. , And an active matrix display device including the display unit 7. Typically, the gate driver 4 and the display unit 7 are formed monolithically on the same substrate. The liquid crystal display device according to this embodiment is characterized by the configuration of the shift register included in the gate driver 4. Hereinafter, m is an even number, n is an integer of 2 or more, and m = 2a.

  The display unit 7 is provided corresponding to m gate bus lines (scanning signal lines) GL1 to GLm, n source bus lines (video signal lines) SL1 to SLn, and intersections of these signal lines ( m × n) pixel forming portions are included. The (m × n) pixel forming portions are arranged in a matrix to form a pixel array. Each pixel forming portion includes a thin film transistor 8 which is a switching element, a pixel electrode, a common electrode Ec, and a liquid crystal layer. The thin film transistor 8 has a gate terminal connected to a gate bus line passing through the corresponding intersection, a source terminal connected to a source bus line passing through the intersection, and a drain terminal connected to the pixel electrode. The common electrode Ec is a counter electrode provided in common to (m × n) pixel formation portions. The liquid crystal layer is sandwiched between the pixel electrode and the common electrode Ec. A pixel capacitor Cp is constituted by a liquid crystal capacitor formed by the pixel electrode and the common electrode Ec. In many liquid crystal display devices, an auxiliary capacitor is provided in parallel with the liquid crystal capacitor in order to reliably hold the voltage in the pixel capacitor Cp. Since the auxiliary capacity is not directly related to the present invention, its description and illustration are omitted.

  The power supply 1 supplies a predetermined power supply voltage to the DC / DC converter 2, the display control circuit 3, and the common electrode drive circuit 6. The DC / DC converter 2 generates a predetermined DC voltage based on the power supply voltage supplied from the power supply 1 and supplies it to the gate driver 4 and the source driver 5. The common electrode drive circuit 6 gives a predetermined potential Vcom to the common electrode Ec.

  The display control circuit 3 receives an image signal DAT and a timing signal group TG (including a horizontal synchronization signal and a vertical synchronization signal) given from the outside, and controls the digital video signal DV and image display on the display unit 7. Control signal for output. The control signals output from the display control circuit 3 include a source start pulse signal SSP, a source clock signal SCK, a latch strobe signal LS, a first gate start pulse signal GSP_O, a second gate start pulse signal GSP_E, a first A gate end pulse signal GEP_O, a second gate end pulse signal GEP_E, and a gate clock signal GCK are included. The gate clock signal GCK includes four-phase clock signals CK1, CK1B, CK2, and CK2B (hereinafter referred to as first to fourth gate clock signals).

  The gate driver 4 includes a first gate start pulse signal GSP_O, a second gate start pulse signal GSP_E, a first gate end pulse signal GEP_O, a second gate end pulse signal GEP_E output from the display control circuit 3, and The gate clock signal GCK is received. Based on these signals, the gate driver 4 repeatedly performs the operation of sequentially applying the active scanning signals Gout (1) to Gout (m) to the gate bus lines GL1 to GLm with one vertical scanning period as a cycle.

  The source driver 5 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 3. Based on these signals, the source driver 5 applies driving video signals S (1) to S (n) to the source bus lines SL1 to SLn.

  The active scanning signals Gout (1) to Gout (m) are sequentially applied to the gate bus lines GL1 to GLm, and the driving video signals S (1) to S (n) are applied to the source bus lines SL1 to SLn. As a result, an image based on the image signal DAT given from the outside is displayed on the display unit 7.

  FIG. 2 is a block diagram showing a schematic configuration of the gate driver 4. As shown in FIG. 2, the gate driver 4 includes a plurality of stages of shift registers 10. A pixel matrix of m rows × n columns is formed on the display unit 7, and each stage of the shift register 10 is provided so as to correspond to each row of the pixel matrix on a one-to-one basis. Each stage of the shift register 10 is a bistable circuit 11. The bistable circuit 11 has two states and is in one of the states at an arbitrary time, and outputs a signal indicating the state (hereinafter referred to as a state signal). As described above, the shift register 10 includes m (= 2a) bistable circuits 11.

  FIG. 3 is a block diagram showing details of the gate driver 4. As shown in FIG. 3, the gate driver 4 includes a shift register 10 including m bistable circuits 11 and a trunk wiring including a clock signal trunk wiring. In FIG. 3, the shift register 10 is configured by arranging m bistable circuits 11 side by side in the vertical direction. The shift register 10 is disposed on the left side of the display unit 7. On the left side of the shift register 10, the main wiring for the first to fourth gate clock signals CK 1, CK 1 B, CK 2, CK 2 B, and the low potential DC voltage VSS are used. A trunk wiring and a trunk wiring for the clear signal CLR are arranged.

  The bistable circuit 11 includes four-phase clock signals CKA, CKB, CKC, CKD (hereinafter referred to as first to fourth clocks), a set signal S, a reset signal R, a clear signal CLR, and a low potential DC voltage VSS. Is input, and the state signal Q is output from the bistable circuit 11. In addition, the input second clock CKB is output from the bistable circuit 11 to the neighboring stage (including the adjacent stage) as a clock signal of the neighboring stage (including the neighboring stage) of the shift register.

  The following signals are given to each stage (bistable circuit 11) of the shift register 10. The low potential DC voltage VSS and the clear signal CLR are commonly applied to all stages. When k is an integer greater than or equal to 1 and less than or equal to a predetermined value, the (4k-3) stage bistable circuit is supplied with the first gate clock signal CK1 as the first clock CKA and the second gate clock as the second clock CKB. Signal CK1B is provided. The (4k-2) -th stage bistable circuit is supplied with the third gate clock signal CK2 as the first clock CKA and the fourth gate clock signal CK2B as the second clock CKB. The second gate clock signal CK1B is supplied as the first clock CKA and the first gate clock signal CK1 is supplied as the second clock CKB to the (4k-1) -th stage bistable circuit. The 4k stage bistable circuit is supplied with the fourth gate clock signal CK2B as the first clock CKA and with the third gate clock signal CK2 as the second clock CKB. Each stage of the shift register 10 receives the low potential DC voltage VSS, the clear signal CLR, the first clock CKA, and the second clock CKB from the main wiring.

  In the bistable circuit at the m-th stage (final stage), the first gate clock signal CK1 (when a is an odd number) or the second gate clock signal CK1B (when a is an even number) is used as the third clock CKC. Given by. FIG. 3 shows a case where a is an odd number. The bistable circuits other than the m-th stage are given the second clock CKB output from the next stage as the third clock CKC. The first gate (first stage) bistable circuit is supplied with the third gate clock signal CK2 from the main wiring as the fourth clock CKD. The bistable circuit other than the first stage is supplied with the second clock CKB output from the previous stage as the fourth clock CKD.

  The first gate start pulse signal GSP_O is supplied as the set signal S to the first stage bistable circuit. The second gate start pulse signal GSP_E is supplied as the set signal S to the second stage bistable circuit. The bistable circuit other than the first stage and the second stage is supplied with the state signal Q output from the previous stage as the set signal S. A second gate end pulse signal GEP_E is supplied as the reset signal R to the m-th stage bistable circuit. The first gate end pulse signal GEP_O is supplied as the reset signal R to the (m−1) -th stage bistable circuit. The bistable circuits other than the (m−1) -th stage and the m-th stage are supplied with the state signal Q output from the second stage as the reset signal R.

  FIG. 4 is a circuit diagram of the bistable circuit 11. As shown in FIG. 4, the bistable circuit 11 includes ten thin film transistors MA, MB, MI, MF, MJ, MK, ME, ML, MN, MD, and a capacitor CAP1. The source terminal of the thin film transistor MB, the drain terminals of the thin film transistors MA, ME, and ML, the gate terminals of the thin film transistors MJ and MI, and one end of the capacitor CAP1 are connected to the same node (hereinafter referred to as the first node N1). The drain terminals of the thin film transistors MJ and MK, the source terminal of the thin film transistor MF, and the gate terminal of the thin film transistor ME are connected to the same node (hereinafter referred to as a second node N2).

  Each component included in the bistable circuit 11 has the following functions. The thin film transistor MA sets the potential of the first node N1 to a low level while the clear signal CLR is at a high level. The thin film transistor MB sets the potential of the first node N1 to a high level while the set signal S is at a high level. The thin film transistor MI applies the potential of the first clock CKA to the output terminal Q while the potential of the first node N1 is at a high level. The output terminal Q of the bistable circuit 11 is connected to the corresponding gate bus line, and the first clock CKA is given from the main wiring. The thin film transistor MI functions as a charge control switching element that charges the corresponding gate bus line based on the clock signal received from the clock signal trunk line.

  The thin film transistor MF sets the potential of the second node N2 to a high level while the third clock CKC is at a high level. The thin film transistor MJ sets the potential of the second node N2 to low level while the potential of the first node N1 is high level. When the potential of the second node N2 becomes high level during the corresponding gate bus line selection period, the thin film transistor ME is turned on, the potential of the first node N1 is lowered, and the thin film transistor MI is turned off. The thin film transistor MJ is provided to prevent this phenomenon.

  The thin film transistor MK sets the potential of the second node N2 to a low level while the fourth clock CKD is at a high level. If the thin film transistor MK is not provided, the potential of the second node N2 is always at a high level except during the selection period of the corresponding gate bus line, and a bias voltage is continuously applied to the thin film transistor ME. If this state continues, the threshold voltage of the thin film transistor ME rises, and the thin film transistor ME does not sufficiently function as a switch. The thin film transistor MK is provided to prevent this phenomenon.

  The thin film transistor ME sets the potential of the first node N1 to low level while the potential of the second node N2 is high level. The thin film transistor ML sets the potential of the first node N1 to a low level while the reset signal R is at a high level. The thin film transistor MN makes the potential of the output terminal Q low level while the reset signal R is high level. The thin film transistor MD sets the potential of the output terminal Q to a low level while the second clock CKB is at a high level. The capacitor CAP1 functions as a compensation capacitor that maintains the potential of the first node N1 at a high level during the selection period of the corresponding gate bus line.

  FIG. 5 is a timing chart of the gate clock signal input to the gate driver 4. FIG. 6 is a timing chart showing changes in the potential of the bistable circuit 11. FIG. 7 is a timing chart of the scanning signal output from the gate driver 4. The operation of the bistable circuit 11 and the shift register 10 including the same will be described below with reference to FIGS.

  As shown in FIG. 5, the potentials of the first to fourth gate clock signals CK1, CK1B, CK2, and CK2B all become high level every other horizontal scanning period. The phase of the first gate clock signal CK1 and the phase of the second gate clock signal CK1B are shifted from each other by 180 degrees (a period corresponding to one horizontal scanning period), and the phase of the third gate clock signal CK2 and the fourth gate clock signal CK2B Are also 180 degrees out of phase with each other. The phase of the third gate clock signal CK2 is 90 degrees behind the phase of the first gate clock signal CK1.

  During the operation of the liquid crystal display device, the first to fourth clocks CKA, CKB, CKC, and CKD supplied to the bistable circuit 11 change as shown in FIG. At time t0, the set signal S changes to high level. Since the thin film transistor MB is diode-connected, when the set signal S becomes high level, the first node N1 is precharged to high level. At this time, since the thin film transistor MJ is turned on, the potential of the second node N2 becomes low level. At this time, the reset signal R is at a low level. Therefore, the thin film transistors ME and ML are in an off state. Therefore, the precharged potential of the first node N1 is kept at a high level until time t2, which will be described later.

  At time t1, the first clock CKA changes from the low level to the high level. A first clock CKA is applied to the source terminal of the thin film transistor MI, and a parasitic capacitance (not shown) exists between the gate and source of the thin film transistor MI. For this reason, when the source potential of the thin film transistor MI rises, the gate potential of the thin film transistor MI also rises (that is, the first node N1 is bootstrapped). As a result, the thin film transistor MI is in a state (on state) in which a sufficiently high voltage is applied to the gate terminal. Since the first clock CKA is at a high level from time t1 to time t2, the status signal Q is also at a high level in the same period. As a result, the gate bus line connected to the output terminal Q enters a selected state, and video signals are written to the pixel capacitors Cp in the plurality of pixel formation portions connected to the gate bus line.

  At time t2, the first clock CKA changes from the high level to the low level, and the second clock CKB and the reset signal R change from the low level to the high level. As a result, the thin film transistors MD, ML, and MN are turned on. When the thin film transistors MD and MN are turned on, the state signal Q becomes low level. When the thin film transistor ML is turned on, the potential of the first node N1 becomes low level. As a result, the status signal Q becomes a high level when the first clock CKA is at a high level between the time when the set signal S becomes a high level and the time when the reset signal R becomes a high level.

  As shown in FIG. 3, m bistable circuits 11 are connected, the first to fourth gate clock signals CK1, CK1B, CK2, and CK2B are changed as shown in FIG. 5, and the first gate start pulse is further changed. The signal GSP_O, the second gate start pulse signal GSP_E, the first gate end pulse signal GEP_O, and the second gate end pulse signal GEP_E are controlled to a high level only for one horizontal scanning period at a predetermined timing. Accordingly, the odd-stage bistable circuit sequentially transfers the pulses included in the first gate start pulse signal GSP_O from the first stage to the (m−1) th stage. Similarly, the even-stage bistable circuit sequentially transfers pulses included in the second gate start pulse signal GSP_E from the second stage to the m-th stage. Therefore, the status signal Q output from each stage of the shift register 10 sequentially becomes a high level. The state signal Q is applied to the gate bus lines GL1 to GLm as scanning signals Gout (1) to Gout (m), respectively. As a result, as shown in FIG. 7, scanning signals Gout (1) to Gout (m) that sequentially become high level for each horizontal scanning period are given to the gate bus lines GL1 to GLm arranged in the display unit 7. It is done.

  FIG. 8 is a schematic diagram showing a layout of the gate driver 4. Hereinafter, in the schematic diagram showing the layout, a wide straight line and a broken line represent wiring, and a small rectangle provided at a location where the wiring intersects represents a contact. The three bistable circuits shown in FIG. 8 include a first clock CKA applied to the thin film transistor MI, a second clock CKB for controlling the thin film transistor MD (not shown), and a third clock CKC for controlling the thin film transistor MF. And a fourth clock CKD for controlling the thin film transistor MK needs to be provided.

  The three bistable circuits shown in FIG. 8 are provided with contacts 115, 125, and 135, respectively. The (4k-2) -th stage bistable circuit includes a wiring 121 for the first clock CKA, a wiring 122 for the second clock CKB, a wiring 123 for the third clock CCK, and a wiring for the fourth clock CKD. 124 is provided. The wiring 121 for the first clock CKA is connected to the trunk wiring for the third gate clock signal CK2 through the contact 126. The wiring 122 for the second clock CKB is connected to the trunk wiring for the fourth gate clock signal CK2B through the contact 127. The wiring 123 for the third clock CKC is connected to the wiring 132 for the second clock CKB of the bistable circuit in the (4k-1) stage via the contact 135 in the (4k-1) stage bistable circuit. Connected. The wiring 132 is connected to the trunk wiring for the first gate clock signal CK1 through the contact 137. The wiring 124 for the fourth clock CKD is connected to the wiring 112 for the second clock CKB of the bistable circuit of the (4k-3) stage via the contact 115 in the bistable circuit of the (4k-3) stage. Connected. The wiring 112 is connected to the trunk wiring for the second gate clock signal CK1B through the contact 117.

Further, the wiring 122 for the second clock CKB is connected to the wiring 113 for the third clock CKC of the bistable circuit at the (4k-3) stage via the contact 125 in the bistable circuit at the (4k-2) stage. , And the wiring 134 for the fourth clock CKD of the bistable circuit at the (4k−1) stage. Other bistable circuits included in the shift register 10 are also laid out in the same form as in FIG. Each stage of such shift register 10 receives a portion of the clock signal of the four clock signals from the clock signal main lines, the remaining part of the clock signal (clock signal is not received from the clock signal main lines) before or Receive from the next stage.

  Referring now to FIG. 3, in the shift register 10, the set signal S, the reset signal R, and the status signal Q are exchanged between odd stages or even stages. Therefore, it can be said that the shift register 10 includes an odd-numbered stage shift register composed of only odd-numbered stages and an even-numbered stage shift register composed of only even-numbered stages. The odd-numbered previous stage and the next stage are even-numbered stages, and the even-numbered previous stage and the next stage are odd-numbered stages. Therefore, each stage of the odd stage shift register receives the remaining clock signal from the adjacent stage of the even stage shift register, and each stage of the even stage shift register receives the residual clock signal of the odd stage shift register. It can be said that it is received from adjacently arranged steps. In this way, each stage of the shift register 10 receives the remaining clock signal from the other shift register (more specifically, from a stage adjacent to the other shift register).

  The wiring 121 for the first clock CKA intersects the wiring 113 for the third clock CKC and the wiring 124 for the fourth clock CKD in the (4k-3) -th stage bistable circuit. The second clock CKB wiring 122 intersects with the third clock CKC wiring 123. In this way, the lead-out wiring from the clock signal trunk wiring intersects with the clock wiring for receiving the remaining clock signal from the stage arranged adjacent to another shift register.

  As described above, the gate driver 4 according to this embodiment includes a plurality of shift registers (odd-stage shift register and even-stage shift register) and a clock signal trunk line. The clock signal trunk line is composed of four signal lines for transmitting four clock signals, and is arranged on the opposite side of the display unit 7 with respect to the shift register 10. The odd-numbered stage shift register is composed of a plurality of stages, and sequentially shifts the pulses given to the first stage based on the four clock signals given to the respective stages, so that the odd-numbered gate bus lines GL1, GL3,. Drive -1. The even stage shift register has the same configuration as the odd stage shift register, and drives the even-numbered gate bus lines GL2, GL4,.

  Each stage of the shift register 10 receives a part of the clock signal from the clock signal trunk line and receives the remaining clock signal from the stage arranged adjacent to the other shift register. The phases of the remaining clock signals (the third clock CCK and the fourth clock CKD) are shifted by 90 degrees from the phase of the clock signal (first clock CKA) provided from the clock signal trunk line to the charge control switching element (thin film transistor MI). ing. Each stage of the shift register 10 includes a contact (for example, the contact 125) for supplying the clock signal received from the clock signal trunk line to both the front stage and the rear stage of the other shift register.

  Hereinafter, effects of the gate driver 4 according to the present embodiment and a liquid crystal display device including the same will be described. FIG. 9 is a schematic diagram showing a layout of a conventional gate driver. In the conventional gate driver, each stage of the shift register receives all four clock signals necessary for operation from the main wiring (see FIG. 9). On the other hand, in the gate driver 4 according to the present embodiment, each stage of the shift register 10 receives a part of the four clock signals necessary for the operation from the clock signal main wiring and receives the remaining clocks. A signal is received from another shift register included in the gate driver 4 (see FIGS. 3 and 8). For this reason, in the present embodiment, the number of wirings connecting the trunk wiring and the bistable circuit is reduced as compared with the prior art, and the wiring area for clock signals in the bistable circuit is reduced. Therefore, according to the gate driver 4 and the liquid crystal display device including the gate driver 4 according to the present embodiment, in the display device including the gate driver including a plurality of shift registers, the area of the bistable circuit is reduced, and the panel The frame area can be reduced.

  For example, in the bistable circuit 140 shown in FIG. 10A, a lead-out wiring 141 for supplying a clock signal from the main wiring is provided, and the element 143 is arranged at the position P1. In the bistable circuit 140, a structure in which a wiring 142 is provided between adjacent stages of another shift register and a clock signal is received using the wiring 142 is employed (see FIG. 10B). As a result, the lead-out wiring 141 becomes unnecessary, and the element 143 can be arranged at the position P2. As a result, as shown in FIG. 10C, the layout area of the bistable circuit 140 can be reduced. Therefore, as shown in FIG. 11, the frame region can be narrowed by the length L in the extending direction of the gate bus line. Therefore, a gate driver can be easily formed even with a panel (for example, a small-sized panel) that has a relatively small area that can be used as a frame area. Further, it becomes possible to form a gate driver having a function equivalent to that of a conventional panel in a panel having a narrower frame region than the conventional one.

  In FIG. 8, the wiring 122 for the second clock CKB of the (4k-2) stage bistable circuit and the wiring 113 for the third clock CKC of the (4k-3) stage bistable circuit are connected. And a contact for connecting the wiring 122 and the wiring 134 for the fourth clock CKD of the (4k−1) -th stage bistable circuit is realized by one contact 125. In this way, by providing contacts at each stage of the shift register 10 for supplying the clock signal received from the clock signal trunk wiring to both the front stage and the rear stage of the other shift registers, the frame area of the panel is further increased. Can be small.

  In the present embodiment, the load capacity associated with the clock signal trunk line is, for example, about one-half that of the prior art. This point will be described with reference to FIGS. FIG. 12 is a schematic diagram showing the load capacitance associated with one trunk wiring per two bistable circuits for the gate driver 4 according to the present embodiment. FIG. 13 is a schematic diagram showing the same contents as FIG. 12 for a conventional gate driver. When the capacitance value C1 is obtained based on the area of the intersection between the trunk wiring and the lead wiring, the capacitance value C1 is, for example, 90 fF. Further, when the capacitance value C2 is obtained based on the area of the intersection between the clock wirings in the shift register region, the capacitance value C2 is, for example, 5 fF. In general, the width of the trunk wiring is 10 times or more the width of the clock wiring in the shift register area. In this example, the load capacity according to this embodiment is about one-half that of the prior art. Therefore, mutual interference due to the clock signal can be suppressed, and the waveform dullness of the clock signal can be reduced. Therefore, the size of the thin film transistor constituting the shift register can be made smaller than before, and the frame area of the panel can be made smaller than before.

(Modification of the first embodiment)
About this embodiment, the following modifications can be constituted. In the above description, each stage of the shift register 10 receives the clock signal not received from the clock signal trunk line from the previous stage or the next stage, but the present invention is not limited to this. Each stage of the shift register may receive a clock signal that is not received from the trunk line for the clock signal from a stage other than the previous stage and the next stage of the shift register. Further, each stage of the shift register may receive the first clock CKA given to the previous stage as the fourth clock CKD, and may receive the first clock CKA given to the next stage as the third clock CKC. Further, the bistable circuit 11 shown in FIG. 4 may include a capacitor between the input terminal for the third clock CKC and the second node N2 instead of the thin film transistor MF.

  In the above description, the gate driver 4 is arranged on one side of the display unit 7, but gate drivers may be arranged on both sides of the display unit 7 as shown in FIG. 14. According to this configuration, one gate bus line can be charged from both sides of the display unit 7, and insufficient charging in the large panel can be solved.

  In the bistable circuit 11 shown in FIG. 4, while the first node N1 is bootstrapped, a high voltage is applied between the source and drain of the thin film transistors ML and ME (or thin film transistors ML, ME, and MB), Leakage currents flow through these thin film transistors, and the potential at the first node N1 may vary. Therefore, in order to solve this problem, a thin film transistor in which a drain electrode or a source electrode is connected to the first node N1 may be formed of a multi-channel TFT. For example, when the thin film transistors ML and ME are formed of multi-channel TFTs (ML2 and ME2), the bistable circuit 12 shown in FIG. 15 is obtained. According to the bistable circuit 12, it is possible to prevent a leakage current from flowing through the thin film transistors ML and ME, thereby reducing the potential of the first node N1. The use of a multi-channel TFT is effective in a circuit using microcrystalline silicon having a relatively large off-state current.

  Hereinafter, the multi-channel TFT will be described with reference to FIGS. 16A to 16C. 16A is a plan view of the multi-channel TFT, FIG. 16B is a cross-sectional view taken along line A-A ′ of FIG. 16A, and FIG. 16C is an equivalent circuit diagram of the multi-channel TFT. A multi-channel TFT 150 shown in FIGS. 16A and 16B has a dual gate structure (double gate structure) and is electrically equivalent to two TFTs connected in series (FIG. 16C).

  The multi-channel TFT 150 has an active layer 154 supported on a substrate (for example, a glass substrate) 151. The active layer 154 is a semiconductor layer and includes a microcrystalline silicon (μc-Si) film. The active layer 154 includes channel regions 154c1, 154c2 (hereinafter referred to as two channel regions), a source region 154s, a drain region 154d, and an intermediate region 154m formed between the two channel regions. The multi-channel TFT 150 further includes a contact layer 156, an electrode layer 158, a gate electrode 152, and a protective film 159 covering these. The contact layer 156 includes a source contact region 156s in contact with the source region 154s, a drain contact region 156d in contact with the drain region 154d, and an intermediate contact region 156m in contact with the intermediate region 154m. The electrode layer 158 includes a source electrode 158s in contact with the source contact region 156s, a drain electrode 158d in contact with the drain contact region 156d, and an intermediate electrode 158m in contact with the intermediate contact region 156m. The gate electrode 152 faces the two channel regions and the intermediate region 154m with the gate insulating film 153 interposed therebetween. The intermediate electrode 158m is in a floating state.

  The channel region 154c1 is formed between the source region 154s and the intermediate region 154m, and the channel region 154c2 is formed between the drain region 154d and the intermediate region 154m. The two channel regions, the source region 154s, the drain region 154d, and the intermediate region 154m are formed in one continuous active layer 154. Further, the entire portion of the intermediate electrode 158m existing between the two channel regions overlaps with the gate electrode 152 with the intermediate region 154m and the gate insulating film 153 interposed therebetween.

  The active layer 154 of the multi-channel TFT 150 is formed of a microcrystalline silicon film or a laminated film of a microcrystalline silicon film and an amorphous silicon film, and can be manufactured using a conventional amorphous silicon TFT manufacturing process. . The microcrystalline silicon film can be formed, for example, using a plasma CVD (Chemical Vapor Deposition) method similar to the method for forming an amorphous silicon film, using a silane gas diluted with hydrogen gas as a source gas. Note that the present invention is not limited to a circuit using microcrystalline silicon, and a multi-channel TFT can be applied to a circuit using amorphous silicon or an oxide semiconductor.

  The liquid crystal display devices according to the second to fourth embodiments of the present invention are different from the liquid crystal display device according to the first embodiment in the configuration of the shift register included in the gate driver. Hereinafter, in the second to fourth embodiments, differences from the first embodiment will be described.

(Second Embodiment)
FIG. 17 is a block diagram showing details of the gate driver according to the second embodiment of the present invention. The gate driver according to this embodiment includes a shift register 20 including an odd-numbered stage shift register and an even-numbered stage shift register, and a trunk line including a clock signal trunk line. The shift register 20 includes m (= 2a) bistable circuits 11 and dummy bistable circuits 21 and 22 that function as dummy stages. The dummy bistable circuits 21 and 22 do not include a thin film transistor that is a switching element. The dummy bistable circuits 21 and 22 include only the components necessary for transmitting the clock signal received from the clock signal trunk line among the components of each stage of the shift register 20.

  The dummy bistable circuit 21 is provided on the first stage side of the shift register 20. The dummy bistable circuit 21 is supplied with the third gate clock signal CK2 from the trunk line as the second clock CKB. The dummy bistable circuit 21 outputs the supplied second clock CKB as it is. The second clock CKB output from the dummy bistable circuit 21 is supplied to the first stage bistable circuit as the fourth clock CKD.

  The dummy bistable circuit 22 is provided on the final stage side of the shift register 20. The dummy bistable circuit 22 is supplied with the first gate clock signal CK1 (when a is an odd number) or the second gate clock signal CK1B (when a is an even number) from the trunk wiring as the second clock CKB. FIG. 17 shows a case where a is an odd number. The dummy bistable circuit 22 outputs the supplied second clock CKB as it is. The m-th bistable circuit is supplied with the second clock CKB output from the dummy bistable circuit 22 as the third clock CKC.

  Here, one dummy bistable circuit is provided on the first stage side and the last stage side of the shift register 20, but depending on the number of clock signals necessary for the operation of the shift register, the first stage side and the last stage side are provided. Each may be provided with a plurality of dummy bistable circuits.

  FIG. 18 is a schematic diagram showing a layout of the gate driver according to the present embodiment. The dummy bistable circuits 21 and 22 include only the components necessary for transmitting the second clock CKB received from the clock signal trunk line among the components of each stage (bistable circuit 11) of the shift register 20. The dummy bistable circuit 21 is provided with a wiring 212 and a contact 215 for the second clock CKB. The wiring 212 is connected to the trunk wiring for the third gate clock signal CK2 through the contact 217, and the fourth clock CKD of the first stage bistable circuit through the contact 215 in the dummy bistable circuit 21. The wiring 234 is connected. The dummy bistable circuit 22 is provided with a wiring 222 for the second clock CKB and a contact 225. The wiring 222 is connected to the trunk wiring for the first gate clock signal CK1 through the contact 227, and is connected to the third clock CKC of the m-th stage bistable circuit through the contact 225 in the dummy bistable circuit 22. And a wiring 243 for use. Except for the above points, the layout of the gate driver according to this embodiment is the same as that of the first embodiment. Also in this embodiment, the lead-out wiring from the clock signal trunk wiring intersects with the clock wiring for receiving the remaining clock signal from the stage arranged adjacent to another shift register.

  As described above, the gate driver according to the present embodiment includes a plurality of shift registers (odd-stage shift register and even-stage shift register) and a clock signal trunk line. Among the plurality of shift registers, one having a dummy bistable circuit 21 that supplies the second clock CKB received from the clock signal trunk line as it is to the first stage (odd stage shift register) and the clock signal trunk line And a dummy bistable circuit 22 that supplies the second clock CKB to the final stage as it is (an even stage shift register).

  Therefore, according to the present embodiment, the circuit configuration is the same for all the bistable circuits from the first stage to the last stage, and the parasitic capacitances are substantially equal, so that the waveform blunting of the clock signal is substantially the same. Accordingly, the shift register can be stably operated.

(Third embodiment)
FIG. 19 is a block diagram showing details of the gate driver according to the third embodiment of the present invention. The gate driver according to the present embodiment includes a shift register 30 including an odd-numbered stage shift register and an even-numbered stage shift register, and a trunk line including a clock signal trunk line. The shift register 30 includes m (= 2a) bistable circuits 31 and dummy bistable circuits 21 and 22. The bistable circuit 31 is obtained by adding a function of outputting a signal Z that changes in the same manner as the state signal Q to the bistable circuit 11 according to the first embodiment.

  FIG. 20 is a circuit diagram of the bistable circuit 31. The bistable circuit 31 is obtained by adding a thin film transistor MG to the bistable circuit 11. The thin film transistor MG outputs the first clock CKA as the signal Z while the potential of the first node N1 is at a high level. In the first and second embodiments, the state signal Q output from the bistable circuit 11 is used as the set signal S and the reset signal R. On the other hand, in the present embodiment, the signal Z generated by the thin film transistor MG is used as the set signal S and the reset signal R.

  In a large panel, the waveform of the state signal Q tends to be blunt because the load on the pixel formation portion is large. If the state signal Q in which the waveform is blunted is used as the set signal S and the reset signal R, the shift register may malfunction. According to the present embodiment, by using the signal Z generated separately from the state signal Q as the set signal S and the reset signal R, it is possible to prevent the shift register from malfunctioning due to the waveform blunting of the state signal Q. it can.

  FIG. 21 is a block diagram illustrating details of a gate driver according to a reference example. The gate driver shown in FIG. 21 includes a shift register 40 including an odd-numbered stage shift register and an even-numbered stage shift register, and a trunk line including a clock signal trunk line. The shift register 40 includes m (= 2a) bistable circuits 41 and two dummy bistable circuits (not shown). FIG. 22 is a circuit diagram of the bistable circuit 41. The bistable circuit 41 operates based on two clock signals (first clock CKA and second clock CKB). In a large panel, signal delay tends to occur while signals are transmitted from the first stage to the last stage of the shift register. Therefore, as shown in FIG. 21, it is only necessary to configure shift registers having different odd-numbered stages and even-numbered stages. Accordingly, when attention is paid to one shift register, the number of stages of the shift register becomes one-half that of the conventional one.

In the gate driver shown in FIG. 21, as in the first to third embodiments, the number of clock signals necessary for the operation of one bistable circuit (here, “2”) is more bistable from the main wiring. The number of clock signals given to the circuit (here, “1”) is smaller. In this way, the number of lead wires from the trunk wire can be reduced as compared to the conventional case, and the intersection between the lead wire and the trunk wire can be reduced as compared with the conventional case. Thereby, signal delay can be effectively prevented. In the gate driver shown in FIG. 21, as in the third embodiment, the waveform of the state signal Q is provided by providing a thin film transistor for generating the signal Z used as the set signal S and the reset signal R in the bistable circuit. It is possible to prevent malfunction of the shift register due to blunting.

  In the first to third embodiments, the wiring for the second clock CKB of the bistable circuit at a certain stage (connected to the main wiring) and the wiring for the third clock CKC of the bistable circuit at the previous stage. And a contact for connecting the wiring for the second clock CKB of the bistable circuit of the stage and the wiring for the fourth clock CKD of the bistable circuit of the subsequent stage This is realized by contact (see FIG. 8). However, the present invention is not limited to this. As shown in FIG. 23, the contact 165 for connecting the wiring 162 for the second clock CKB of the bistable circuit in a certain stage and the wiring 163 for the third clock CKC of the previous bistable circuit, and the wiring 162 And a contact 166 for connecting the wiring 164 for the fourth clock CKD of the subsequent stage bistable circuit may be provided separately, and the two contacts 165 and 166 may be arranged at positions where they are in contact with each other to be electrically connected. . Thereby, contact resistance can be made smaller than arrange | positioning two contacts in the position distant.

(Fourth embodiment)
FIG. 24 is a block diagram showing details of the gate driver according to the fourth embodiment of the present invention. The gate driver according to the present embodiment includes a shift register 50 including an odd-numbered stage shift register and an even-numbered stage shift register, and a trunk line including a clock signal trunk line. The shift register 50 includes m (= 2a) bistable circuits 51 and dummy bistable circuits 52 to 54 that function as dummy stages.

  The bistable circuit 51 has the same circuit configuration as the bistable circuit 11 according to the first embodiment (see FIG. 4). However, the bistable circuit 51 outputs the inputted first clock CKA to the neighboring stage (including the adjacent stage) as the clock signal of the neighboring stage (including the neighboring stage) of the shift register. This is different from the bistable circuit 11 that outputs the clock CKB to the neighboring stage (including the adjacent stage) as a clock signal of the neighboring stage (including the neighboring stage) of the shift register. Like the dummy bistable circuits 21 and 22 according to the second embodiment, the dummy bistable circuits 52 to 54 do not include a thin film transistor that is a switching element, and each stage of the shift register 50 (bistable circuit 51) is configured. Among the elements, only the components necessary for transmission of the clock signal received from the clock signal trunk line are included.

The dummy bistable circuit 52 is provided on the first stage side of the shift register 20. The dummy bistable circuit 52 is supplied with the fourth gate clock signal CK2B from the trunk line as the first clock CKA. The dummy bistable circuits 53 and 54 are provided in the final stage of the shift register 5 0. The dummy bistable circuit 53 is supplied with the second gate clock signal CK1B (when a is an odd number) or the first gate clock signal CK1 (when a is an even number) from the trunk wiring as the first clock CKA. The dummy bistable circuit 54 is supplied with the fourth gate clock signal CK2B (when a is an odd number) or the third gate clock signal CK2 (when a is an even number) from the trunk line as the first clock CKA. FIG. 24 shows a case where a is an odd number. The dummy bistable circuits 52 to 54 output the given first clock CKA as it is.

The following signals are given to the stage of the shift register 50 (bistable circuit 51). The low potential DC voltage VSS and the clear signal CLR are commonly applied to all stages. When k is an integer greater than or equal to 1 and less than or equal to a predetermined value, the first gate clock signal CK1 is supplied to the (4k-3) stage bistable circuit as the first clock CKA. The third gate clock signal CK2 is supplied as the first clock CKA to the (4k-2) stage bistable circuit. The second gate clock signal CK1B is supplied as the first clock CKA to the (4k-1) -th bistable circuit. The fourth gate clock signal CK2B is supplied to the 4k stage bistable circuit as the first clock CKA. Each stage of the shift register 5 0, the DC voltage VSS of low potential, the clear signal CLR, and receives a first clock CKA from the main lines.

  The first clock CKA output from the dummy bistable circuit 52 is supplied to the first (first) bistable circuit as the third clock CKC. The bistable circuit other than the first stage is supplied with the first clock CKA output from the previous stage as the third clock CKC. The first clock CKA output from the dummy bistable circuit 53 is supplied as the fourth clock CKD to the m-th (final) bistable circuit. The bistable circuit other than the m-th stage is supplied with the first clock CKA output from the next stage as the fourth clock CKD.

  The m-th bistable circuit is supplied with the first clock CKA output from the dummy bistable circuit 54 as the second clock CKB. The first clock CKA output from the dummy bistable circuit 53 is supplied to the (m−1) -th bistable circuit as the second clock CKB. The bistable circuit other than the (m−1) -th stage and the m-th stage is supplied with the first clock CKA output from the second stage as the second clock CKB.

  FIG. 25 is a schematic diagram showing a layout of the gate driver according to the present embodiment. 25 includes a first clock CKA given to the thin film transistor MI, a second clock CKB for controlling the thin film transistor MD, a third clock CKC for controlling the thin film transistor MF, and a thin film transistor MK. It is necessary to provide the fourth clock CKD for controlling the above.

  The (4k-2) stage bistable circuit shown in FIG. 25 includes a first clock CKA wiring 521, a second clock CKB wiring 522, a third clock CKC wiring 523, and a fourth clock. CKD wiring 524 and contacts 525 and 526 are provided. The wiring 521 for the first clock CKA is connected to the trunk wiring for the third gate clock signal CK2 via the contact 527. The second clock CKB wiring 522 is connected to the first clock CKA wiring 541 of the 4k stage bistable circuit via a contact 546 provided in the 4k stage bistable circuit. The wiring 541 is connected to the trunk wiring for the fourth gate clock signal CK2B through the contact 547. The wiring 523 for the third clock CKC is connected to the first clock CKA for the bistable circuit in the (4k-3) stage via the contact 515 provided in the bistable circuit in the (4k-3) stage. 511 is connected. The wiring 511 is connected to the trunk wiring for the first gate clock signal CK1 through the contact 517. The wiring 524 for the fourth clock CKD is a wiring for the first clock CKA of the (4k-1) -th stage bistable circuit via a contact 535 provided in the (4k-1) -th stage bistable circuit. 531 is connected. The wiring 531 is connected to the trunk wiring for the second gate clock signal CK1B through the contact 537.

  Further, the wiring 521 for the first clock CKA is connected to the wiring 533 for the third clock CKC of the bistable circuit in the (4k-1) stage via the contact 525 in the bistable circuit in the (4k-2) stage. , And the wiring 514 for the fourth clock CKD of the (4k-3) stage bistable circuit. The wiring 521 is connected to a wiring (not shown) for the second clock CKB of the (4k-4) stage bistable circuit via the contact 526 in the (4k-2) stage bistable circuit. Connected. Other bistable circuits included in the shift register 50 are also laid out in the same form as in FIG. In this way, each stage of the shift register 50 receives a part of the four clock signals from the clock signal trunk line, receives another part of the clock signal from the previous stage or the next stage, and receives the remaining clock signals. Is received from the second stage.

  As in the first embodiment, the shift register 50 includes an odd-numbered stage shift register and an even-numbered stage shift register, the odd-numbered stage before and the next stage are even-numbered stages, and the even-numbered stage preceding and next stages. Becomes an odd numbered stage. Further, the second stage after the odd-numbered stage is the odd-numbered stage, and the second stage after the even-numbered stage is the even-numbered stage. Accordingly, each stage of the shift register 50 receives a part of the four clock signals from the clock signal trunk line and receives another part of the clock signal from the other shift register (more specifically, the other part). It can be said that the remaining clock signal is received from the same shift register (more specifically, from the next stage of the same shift register).

  In addition, the wiring 531 for the first clock CKA of the (4k−1) stage bistable circuit includes the wiring 533 for the third clock CKC of the (4k−1) stage bistable circuit, and (4k−) 2) Crosses the wiring 522 for the second clock CKB at the stage. In this way, the lead wiring from the clock signal trunk wiring is the clock wiring for receiving another part of the clock signal from the stage arranged adjacent to the other shift register, and the remaining clock signal of the same shift register. Crosses the clock wiring for receiving from the next stage.

As described above, in the gate driver according to the present embodiment, each stage of the shift register 50 receives a part of the clock signal from the clock signal trunk line and receives another part of the clock signal from the other shift register. Receive from the adjacent stage and receive the remaining clock signal from the next stage of the same shift register. From the phase of the clock signal (first clock CKA) given from the clock signal trunk to the charge control switching element (thin film transistor MI), the phases of the other part of the clock signals (third clock CKC and fourth clock CKD) are The phase of the remaining clock signal (second clock CK B ) is shifted by 180 degrees. Each stage of the shift register 50 includes a contact (for example, a contact 525) for supplying the clock signal received from the clock signal trunk line to both the front stage of the other shift register and the rear stage of the other shift register. .

  According to the gate driver and the liquid crystal display device including the gate driver according to the present embodiment, the same effects as those of the first embodiment can be obtained. Also in the present embodiment, a modification similar to that in the first embodiment can be configured. Further, in this embodiment, each stage of the shift register 50 is configured so that the clock signal received from the clock signal trunk line is the front stage of another shift register, the rear stage of the other shift register, and the other stage of the same shift register. A contact (for example, contact 525) for giving to at least two of them may be included. Alternatively, each stage of the shift register 50 has a contact for giving the clock signal received from the clock signal trunk wiring to the front stage of the other shift register, and for giving the clock signal to the rear stage of the other shift register. A contact and a contact for supplying the clock signal to the other stage of the same shift register may be separately included, and at least two of the three contacts may be disposed and electrically connected to each other. . In this embodiment, each stage of the shift register 50 receives the remaining clock signal from the next stage of the same shift register. However, the remaining clock signal may be received from the previous stage of the same shift register.

  Note that although a liquid crystal display device has been described as an example of a display device to which the present invention is applied, the present invention is not limited to this. The present invention can also be applied to display devices other than liquid crystal display devices, such as organic EL (Electro Luminescence) display devices.

  Since the scanning signal line driving circuit of the present invention has an effect of reducing the layout area for the shift register and the frame area of the panel, various display devices such as a liquid crystal display device and an organic EL display device can be obtained. Can be used.

DESCRIPTION OF SYMBOLS 1 ... Power supply 2 ... DC / DC converter 3 ... Display control circuit 4 ... Gate driver (scanning signal line drive circuit)
5 ... Source driver (video signal line drive circuit)
DESCRIPTION OF SYMBOLS 6 ... Common electrode drive circuit 7 ... Display part 8 ... Thin-film transistor 10, 20, 30, 40, 50 ... Shift register 11, 12, 31, 41, 51 ... Bistable circuit 21, 22, 52-54 ... Dummy bistable circuit GL1 to GLm: Gate bus line ( scanning signal line)
SL1 to SLn: Source bus line ( video signal line)
MA, MB, MD, ME, MF, MG, MI, MJ, MK, ML, MN ... Thin film transistor GEP_O ... First gate end pulse signal GEP_E ... Second gate end pulse signal GSP_O ... First gate start pulse Signal GSP_E ... Second gate start pulse signal GCK ... Gate clock signal CK1 ... First gate clock signal CK1B ... Second gate clock signal CK2 ... Third gate clock signal CK2B ... Fourth gate clock signal CKA ... First clock CKB ... Second clock CKC ... Third clock CKD ... Fourth clock S ... Set signal R ... Reset signal Q ... Status signal

Claims (20)

A scanning signal line driving circuit for driving a plurality of scanning signal lines arranged in a display unit of a display device,
Each is composed of a plurality of stages, a plurality of shift registers that sequentially shift pulses applied to the first stage based on a plurality of clock signals applied to each stage, and drive the scanning signal lines;
A plurality of signal lines for transmitting the clock signal, and a clock signal trunk line disposed on the opposite side of the display unit with respect to the shift register;
The plurality of shift registers are disposed on one side of the display unit,
The plurality of shift registers include an odd-numbered stage shift register composed of only odd-numbered stages, and an even-numbered stage shift register composed of only even-numbered stages,
Each stage of the shift register receives a part of the clock signal from the clock signal trunk line and receives the remaining clock signal from another shift register.   2. The scanning signal line driving circuit according to claim 1, wherein each stage of the shift register operates based on four clock signals.   2. The scanning signal line drive circuit according to claim 1, wherein each stage of the shift register receives the remaining clock signal from a stage adjacent to another shift register. Each stage of the shift register includes a charge control switching element that charges a corresponding scanning signal line based on a clock signal received from the clock signal trunk line,
2. The scanning signal line drive circuit according to claim 1, wherein the phase of the remaining clock signal is shifted by 90 degrees from the phase of the clock signal applied to the charge control switching element. 3.   2. The scanning signal line drive according to claim 1, wherein each stage of the shift register includes a contact for supplying the part of the clock signal to both a front stage and a rear stage of another shift register. circuit.   Each stage of the shift register has a contact for supplying the partial clock signal to the front stage of the other shift register, and a contact for supplying the partial clock signal to the rear stage of the other shift register. 2. The scanning signal line drive circuit according to claim 1, wherein the two contacts are arranged at positions in contact with each other.   The shift register has a dummy stage that gives the clock signal received from the clock signal trunk wiring to the first stage as it is, and a dummy stage that gives the clock signal received from the clock signal trunk wiring to the last stage as it is The scanning signal line driving circuit according to claim 1, wherein the scanning signal line driving circuit according to claim 1 is included.   8. The dummy stage according to claim 7, wherein the dummy stage includes only components necessary for transmitting the clock signal received from the clock signal trunk line among the components of each stage of the shift register. Scanning signal line driving circuit. Each stage of the shift register further includes a thin film transistor in which a drain electrode or a source electrode is connected to a gate terminal of the charge control switching element,
5. The scanning signal line drive circuit according to claim 4, wherein the thin film transistor is a multi-channel thin film transistor and is formed of an oxide semiconductor. A display unit including a plurality of scanning signal lines, and a scanning signal line drive circuit according to any one of claims 1 to 9 display. A scanning signal line driving circuit for driving a plurality of scanning signal lines arranged in a display unit of a display device,
Each is composed of a plurality of stages, a plurality of shift registers that sequentially shift pulses applied to the first stage based on a plurality of clock signals applied to each stage, and drive the scanning signal lines;
A plurality of signal lines for transmitting the clock signal, and a clock signal trunk line disposed on the opposite side of the display unit with respect to the shift register;
The plurality of shift registers are disposed on one side of the display unit,
The plurality of shift registers include an odd-numbered stage shift register composed of only odd-numbered stages, and an even-numbered stage shift register composed of only even-numbered stages,
Each stage of the shift register receives a part of the clock signal from the clock signal trunk, receives another part of the clock signal from the other shift register, and receives the remaining clock signal from the other stage of the same shift register. A scanning signal line driver circuit receiving the scanning signal line driver circuit.

Wherein each stage of the shift register, characterized in that it operates based on four clock signals, the scanning signal line drive circuit according to claim 1 1. Each stage of the shift register receives the other part of the clock signal from an adjacently arranged stage of the other shift register, and receives the remaining clock signal from the previous stage or the next stage of the same shift register. to, the scanning signal line driving circuit according to claim 1 1. Each stage of the shift register includes a charge control switching element that charges a corresponding scanning signal line based on a clock signal received from the clock signal trunk line,
The phase of the other clock signal is shifted by 90 degrees from the phase of the clock signal applied to the charge control switching element, and the phase of the remaining clock signal is shifted by 180 degrees, scanning signal line drive circuit according to claim 1 1. Each stage of the shift register is a contact for supplying the part of the clock signal to at least two of the front stage of another shift register, the rear stage of the other shift register, and the other stage of the same shift register. characterized in that it comprises a scanning signal line drive circuit according to claim 1 1. Each stage of the shift register has a contact for supplying the partial clock signal to a front stage of another shift register, and a contact for supplying the partial clock signal to a rear stage of the other shift register; and a contact for supplying the part of the clock signals to other stages of the same shift register, characterized in that at least two are arranged at positions in contact with each other among the three contact claim 1 1 2. A scanning signal line driving circuit according to 1. The shift register has a dummy stage that gives the clock signal received from the clock signal trunk wiring to the first stage as it is, and a dummy stage that gives the clock signal received from the clock signal trunk wiring to the last stage as it is characterized in that it contains as having, a scanning signal line drive circuit according to claim 1 1. The dummy stage, among the components of each stage of said shift register, characterized in that it comprises only components required for transmission of a clock signal received from the clock signal main line, according to claim 1 7 Scanning signal line driving circuit. Each stage of the shift register further includes a thin film transistor in which a drain electrode or a source electrode is connected to a gate terminal of the charge control switching element,
The scanning signal line driving circuit according to claim 14, wherein the thin film transistor is a multi-channel thin film transistor and is formed of an oxide semiconductor. A display device comprising: a display unit including a plurality of scanning signal lines; and the scanning signal line driving circuit according to any one of claims 1 to 19 .

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