JP3496948B2 - Active matrix panel drive circuit and active matrix panel - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix panel such as a liquid crystal display panel, and more particularly to a structure technology for its drive circuit side.

[0002]

2. Description of the Related Art Among flat type display panels which display information by utilizing the alignment state of liquid crystal, etc., an active matrix type liquid crystal display panel has a pixel structure as shown in a block diagram of FIG. Matrix 22,
The source line drive circuit 12 and the gate line drive circuit 21 are formed on the same transparent substrate 11 to achieve downsizing, high definition, and cost reduction of the display device. Here, the source line drive circuit 12 has a shift register 13, sample hold circuits 17, 18, 19 and video signal lines 14, 15, 16 while a gate line drive circuit 21.
Has a shift register 20 and, if necessary, a buffer circuit 23. Further, the pixel matrix 22 includes a plurality of source lines 26, 27 connected to the source line drive circuit 12,
28, a plurality of gate lines 24, 25 connected to the gate line drive circuit 21, and a plurality of pixels 32, 33 formed at the intersections of these gate lines and source lines.
, And each pixel 32, 33 ... Has a thin film transistor 29 and a liquid crystal cell 30. Here, a clock signal line 34 for inputting a clock signal to the shift register 13 is arranged on the source line drive circuit 12 side, while a gate signal drive circuit 21 is connected to the shift register 20 on the gate line drive circuit 21 side. A clock signal line 37 to which a clock signal should be input is arranged. Reference numerals 35 and 38 denote start signal lines for inputting start signals to the source line drive circuit 12 and the gate line drive circuit 21.

[0003]

Here, in the liquid crystal display panel, in order to improve the display quality of the liquid crystal display panel, the pixel pitch is narrowed to make the pixels finer. However, in the conventional active matrix panel, In the structure of the drive circuit, there is a problem in that there is a limit in narrowing the pixel pitch due to the restriction of the structure on the drive circuit side. That is, the pitch of the pixels 32, 33, ... Inevitably becomes the same pitch as the unit cell of the drive circuit, but the shift register 13 of the source line drive circuit 12 is composed of, for example, 10 thin film transistors per bit. However, there is a limit to the narrowing of the formation area.

In order to improve the display quality of the liquid crystal display panel, it is also required to increase the operating speed of the drive circuit. However, due to the operating characteristics of the thin film transistors forming the shift register 12, the operating frequency of the thin film transistors should be increased. Since there is a limit to increase the operation speed of the source line drive circuit 12 while ensuring a certain margin, a method of driving the shift register 12 in multiple series has been devised. Here, in making the shift register 12 multi-series, the above-mentioned problem, that is, the source line drive circuit 12
In order to solve the problem that there is a limit to the narrowing of the pitch of the unit cell in FIG.
And, as shown in FIG. 11, it is proposed to divide the formation region of the shift register 81. That is, in the first shift register formation area 82a, the unit shift registers A1,
The A-series shift register 81a including A2 ... Is formed, while the B-series shift register 81b including the unit shift registers B1, B2 ... Is formed in the second shift register formation region 82b. Here, the function symbols of the unit shift registers A1, B1, A2, B2, ... Are as shown in FIG. 10B, in the unit shift register A1, a shift signal input Ain and a shift signal output Aout.
And that bit signal output is performed.

Here, the unit shift registers A1, B1,
As shown in FIG. 11, each of A2, B2 ... Is composed of one inverter 2 and two clocked inverters 3 and 4, and these are formed by n bits to form an A series shift register 81a and a B series shift register 81a. The shift register 81b is configured. In the shift register 81 having such a configuration,
For the shift register 81a of the A-series, while supplying a clock signal CKA from the clock signal line 83 of the A series, for the shift register 81 b of the B series, the clock signal from the clock signal line 84 of the B-series CKB To supply. Further, by shifting the phase of the clock signal CKA from the A-series clock signal line 83 and the phase of the clock signal CKB from the B-series clock signal line 84 by 90 °, the sample-hold circuit from the shift register 81 side. The high-frequency bit signal can be transmitted to the analog switch 85.

The A-system clock signal lines 83 are mutually connected.
Inverse phase clock signals CLA, CLA * (*
Shows reverse phase. ) Supplying two clock signal lines 83
1, 832, and a B-series clock signal line 84
Is also composed of two clock signal lines 841 and 842 for supplying clock signals CLB and CLB * having mutually opposite phases. Of the clock signal lines 831 and 841, odd-numbered unit shift registers A1, A3, ..., B
Clock signals CLA and CLB are input to 1, B3, ... On the other hand, even-numbered unit shift registers A2, A4 ..., B2, B4 are input from the clock signal lines 832, 842.
Clock signals CLA * and CLB * are input to. Further, a buffer circuit 87 for adjusting the synchronization of bit signals is composed of two inverters 5 and 6 between the shift registers 81a and 81b and the analog switch 86. According to the source line drive circuit 80 having two lines in this manner, the operation speed of the source line drive circuit 80 can be increased without increasing the frequency of driving the thin film transistor itself of the shift register 81, and the unit Shift registers A1, B1, A2, B2 ...
However, since the pitch of the source line driving circuit 80 is formed in two stages, the pitch per unit cell of the source line driving circuit 80 is effectively reduced to 1/2.
The pixel pitch can be narrowed. Further, as shown in FIG. 12, the shift register 91 is set to the A to D series shift registers 91a, 91b, 91c, and 91d, while the A to D series clock signals CKA, CKB,
It is also possible to further increase the operation speed of the source line drive circuit 90 by arranging the four series of A to D series clock signal lines 92, 93, 94 and 95 for supplying CKC and CKD.

However, in the source line drive circuits 80, 90 shown in FIGS. 10 to 12, the clock signal lines 83, 84, 92-on one side of the formation regions of the shift registers 81, 91, that is, on the outer peripheral side of the substrate. Since 95 are collectively arranged, each clock signal line 83, 84,
Since the wiring lengths of the clock signal input lines from 92 to 95 to the shift registers 81 and 91 greatly differ for each series,
There is a new problem that the shift registers 81 and 91 are likely to malfunction due to the difference in wiring resistance or the difference in parasitic capacitance of the clock signal input lines. That is, in the two-series source line drive circuit 80 shown in FIGS. 10 and 11, the wiring length is greatly different between the A-series clock signal input line 89a and the B-series clock signal input line 89b. In the four-series source line driving circuit 90 shown in FIG. 1, between the A-series clock signal input line 99a, the B-series clock signal input line 99b, the C-series clock signal input line 99c, and the D-series clock signal input line 99d. The wiring length is long. In addition, 2 shown in FIG. 10 and FIG.
In the series source line drive circuit 80, the unit shift registers A1, A2 and A3 of the A series shift register 81 are included.
Since the B-series clock signal input line 99b passes through the space between ..., The A-series shift register 81
The pitch of the unit shift registers A1, A2, A3, ... Is forced to be expanded, and there is a limit to narrowing the pitch of the unit cells of the source line drive circuit 80. Such problems are
In the four-series source line driving circuit 90 shown in FIG. 12, the problem becomes more prominent.

In view of the above problems, the object of the present invention is to:
While optimizing the layout structure of the shift register and the clock signal line to prevent malfunction of the shift register,
It is to realize an active matrix panel capable of narrowing the pitch of unit cells on the drive circuit side.

[0009]

In order to solve the above problems, the present invention provides first and second clocks which are arranged in parallel and which transfer first and second clock signals which are out of phase with each other. A signal line, a video signal line for transferring a video signal, and a first clock signal which is adjacent to the first clock signal line and which comes from the first clock signal line through the first clock signal input line. The unit shift register outputs the shift signals serially in synchronization with each other, and the first clock-by-clock shift register and the first clock-by-clock shift register which sequentially output n first bit output signals whose phases are sequentially shifted in parallel. The unit shift register shifts in synchronism with each other and adjacent to the second clock signal line, in synchronization with the second clock signal coming from the second clock signal line through the second clock signal input line. While serial output No., second to parallel outputs of the m second bit output signal sequence of the phase shift
A clock-by-clock shift register, n first signal line-by-line switch means for pulling a video signal to a signal line in the pixel region based on the first bit output signal through the first bit output line, and a second M second signal line-specific switch means for pulling a video signal to another signal line in the pixel region based on the second bit output signal via the bit output line, and the second clock signal line is The first and second signal line switch means are located closer to the pixel region than the first clock signal line, and the first and second signal line-specific switch means are located closer to the pixel region than the second clock signal line and with respect to the second clock signal line. A driving circuit for active matrix panels formed in parallel,
The first and second clock-specific shift registers are sandwiched inside the first and second clock lines, and the first clock signal input line does not intersect with the second clock-specific shift register. The second clock signal input line is connected to the clock-based shift register, and the second clock signal input line is connected to the second clock-based shift register without intersecting with the first clock-based shift register . Two clocks
One of the power lines that supplies power to another shift register
Of the first clock signal line and the first clock signal line.
It is located between each shift register and
Of the other power source line is the second clock signal line and the second clock signal line.
It is arranged between the shift register for each clock .

Here, a buffer circuit may be provided in the middle of the first and second bit output lines and between the second clock line and the first and second bit-by-bit switch means.
Further, it is desirable that the first bit output line is drawn from the first clock-wise shift register to the second clock-wise shift register side and connected to the first bit-wise switch means.

The first clock signal and the second clock signal are not limited to one each, and the first clock signal and the second clock signal are clock signals that are out of phase with each other by 90 °, and The first clock signal line is a pair of clock signal lines for transferring a positive phase signal and a reverse phase signal of the first clock signal, and the second clock signal line is the second clock signal line.
Positive phase signal of the clock signal and yet good as a pair of clock signal lines for transferring the reverse-phase signal.

[0012]

[0013]

According to this structure, the first and second clock shift registers are driven by the first and second clock signals whose phases are shifted from each other, so that the driving circuit can be operated at high speed. In addition, even if the occupied area of the unit shift register per bit is the same as the conventional one , the adjacent unit shift registers in each shift register
Since they can be packed and arranged , the pixel pitch can be narrowed and high definition can be realized. In particular, the first and second clock shift registers arranged in parallel are sandwiched between the first and second clock lines arranged in parallel .
The first clock signal input line is
First clock-based shift register without crossing register
The second clock signal input line
The second clock without crossing the first clock-wise shift register.
Since it is connected to the shift register for each lock ,
Also, the second clock signal input line can be minimized and made to have the same length to prevent malfunction of the high-speed shift operation, and the lead wire length of the second bit output line is increased. relatively long lead wiring that can be close to the length of, the it is possible to first equivalent of the wiring resistance of the second bit output lines together, the second bit output line also with the first bit output line Similarly, since it always crosses the second clock signal line, the first and second bit outputs
By equalizing the number of crossings of the line with the second clock signal line, equalization of the parasitic capacitance at the crossing portion can be realized.
It is possible to suppress the timing shift between the bit output signals of, and improve the display quality. On the contrary, since no clock signal line is sandwiched between the first and second shift registers for each clock, the shift signal output from the unit shift register is provided between the first and second shift registers for each clock. Is not limited to the shift signal line for inputting to the unit shift register of the subsequent stage in the clock-by-clock shift register to which the unit shift register belongs, and the shift signal output from the unit shift register does not belong to the other unit shift register. Since the shift signal line for inputting to the unit shift register of the same stage in the clock shift register can also be formed between the first and second clock shift registers, it is possible to mix shift signals. The first and second shift registers for each clock are mutually dependent, and the first and second shift registers are out of phase with each other. Despite driven by a clock signal, also a result be apparent, a single shift register having excellent synchrony,
Helps improve display quality.

[0014]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

[Embodiment 1] FIG. 1 is a block diagram of a source line drive circuit side of an active matrix panel (liquid crystal display panel) according to Embodiment 1 of the present invention, and FIG. 2 is a thin film transistor constituting the source line drive circuit. It is explanatory drawing which shows arrangement | positioning of a wiring layer. Here, the overall configuration of the active matrix panel of this example is similar to that of the block diagram shown in FIG. 9, and in this example, the main feature is in the arrangement of the shift register and the clock signal line on the source line driver circuit side. In the following description, the description of the overall configuration will be omitted and the configuration of the source line drive circuit will be described in detail.

In these figures, the source line drive circuit 40 of the active matrix panel of the present example has a two-system drive system, like the source line drive circuits shown in FIGS. 10 and 11. The source line drive circuit 40 is
It is formed on the same transparent substrate together with the pixel matrix and the gate line drive circuit (both not shown), and drives the display operation of each pixel of the pixel matrix. In addition, the source line drive circuit 40 is formed between the outer peripheral edge of the substrate and the pixel matrix formation region.
The shift register 41 of the source line drive circuit 40 includes a first shift register forming region 42a on the outer peripheral edge side (direction of arrow X) of the substrate and a second shift register forming side of the pixel matrix (direction of arrow Y). In the formation area 42b, the A-series shift register 41a (first shift register) including unit shift registers A1, A2, A3, ... And unit shift registers B1, B2, B3 ...
And a B series shift register 41b (first shift register). Also, these A-series and B-series shift registers 41a, 41
Among the clock signal lines that supply the clock signals CKA and CKB to b, the A-series clock signal line 43 (first clock signal line) that supplies the clock signal CKA to the A-series shift register 41a is the first shift line. The B-series clock signal line 44 (second clock signal line), which is arranged in parallel at a position adjacent to the register formation region 41a and supplies the clock signal CKB to the B-series shift register 41b, is the second shift register. It is arranged in parallel at a position adjacent to the formation region 42b. Here, the A-system clock signal line 43 is connected to the first shift register formation region 4
2a is formed on the outer peripheral edge side (direction of arrow X) of the substrate, and the B-series clock signal line 44 is formed on the pixel matrix formation region side (direction of arrow Y) with respect to the second shift register formation region 42b. Has been formed. Further, the A-series clock signal line 43 and the B-series clock signal line 44 are located at positions substantially equidistant from the corresponding first or second shift register forming regions 42a and 42b.
The A-series clock signal line 43 and the A-series shift register 41a are connected by a clock signal input line 49a, and the B-series clock signal line 44 and the B-series shift register 41b are connected by a clock signal input line 49b. Has been done. Here, A-system clock signal line 4
3 are arranged in parallel at a position adjacent to the first shift register formation region 42a, and the B-series clock signal line 44 is provided.
Are arranged in parallel at positions adjacent to the second shift register formation region 42b, the clock signal lines 4
The wiring lengths of the clock signal input lines 49a and 49b from 3,44 to the shift register 41 are designed to have the same dimension and the shortest dimension between the A series and the B series.

Further, the second shift register forming region 42
On the pixel matrix formation region side (direction of arrow Y) with respect to b, the bit signal output from the shift register 41 is directed to the sample hold unit, that is, the analog switch unit 45 side (pixel matrix side). A bit signal output line 46 for transmitting the signal is formed, and a bit signal output to the side of the analog switch section 45 via the bit signal output line 46 is delayed in the middle thereof to output the bit signal. The buffer circuit 47, which should mitigate the influence of noise from the B-series clock signal line 44 where the line 46 intersects, has two inverters 47 as shown in FIG.
a, 47b. Here, in the middle position of the bit signal line 46, the buffer circuit 47 that should mitigate the influence of noise from the B-series clock signal line 44.
As shown in FIGS. 3 (a), 3 (b) and 3 (c), the resistance R parasitic on the high resistance bit signal output line 46 formed of the polycrystalline silicon layer and the bit signal Output line 46 and clock signal line 44 that is an aluminum wiring layer
It is also possible to form a buffer circuit by using the parasitic capacitance C formed by the interlayer insulating film 48 interposed between the buffer circuit and the. Also, clocked gates can be used.

In this example, as shown in FIG.
The A-series clock signal line 43 is composed of two clock signal lines 431 and 432 through which the clock signals CLA and CLA * having opposite phases are transmitted, and the B-series clock signal line 44 also has the opposite phase clock signals. CLB, CLB *
Of two clock signal lines 441 and 442 for transmitting. Of these clock signal lines 43, 44, odd-numbered unit shift registers A1, A3 ..., B1, B3, ...
The clock signals CLA, CLB are input to the clock signals CLA *, CLB * from the opposite phase clock signal lines 432, 442 to the even-numbered unit shift registers A2, A4 ..., B2, B4. Is entered. Where A
Series and B series shift registers 41a and 41b are
In each case, as shown in FIG. 4A, one inverter 2 and two clocked inverters 3a and 4a (clocked inverters 3b and 4b) are used to shift the unit shift register 1 (A1, A2, A3) for one bit. ..., B1, B
2, B3 ...), of which odd-numbered unit shift registers 1a (A1, A3 ..., B)
, B3 ...) are driven by the clock signals CLA, CLB of the clock signals CKA, CKB, while the even-numbered unit shift registers 1b (A2, A4.
.., B2, B4 ...) are clock signals CKA, C
It is driven by clock signals CLA *, CLB * having a phase opposite to that of the clock signals CLA, CLB of the KB. That is, the inverter 2 includes a p-channel type TFT 201 and an n-channel type TFT 201 as shown in FIGS. 2 and 4B.
However, the clocked inverters 3a and 4a have two p-channel type TFTs 301a and 30a, as shown in FIGS. 2 and 4C.
2a and n-channel type TFTs 401a and 402a, and can be driven by clock signals CLA and CLB. The clocked inverters 3b and 4b are two p-types as shown in FIGS. 2 and 4D. Channel type TFT
301b and 302b and n-channel TFTs 401b and 4
02b and a clock signal CLA * of opposite phase,
It can be driven by CLB *.

Further, the clock signal CKA (clock signals CLA, CLA *) from the A-system clock signal line 43.
And the phase of the clock signal CKB from the B-series clock signal line 44 (clock signals CLB, CLB *) are shifted by 90 ° as in the timing chart shown in FIG. Therefore, after the start signal DX is input, the odd-numbered unit shift registers (A1, A3, ...) Of the A-series shift register 41a correspond to the bit signal 2 corresponding to the pulse falling of the clock signal CLA.
While outputting 52, unit shift registers (A2, A4, ...) Of even-numbered shift registers 41a of A series
Outputs the bit signal 254 in response to the pulse falling of the clock signal CLA *. In addition, odd-numbered unit shift registers (B
, B3 ...) outputs the bit signal 253 in response to the pulse falling of the clock signal CLB, while B
The even-numbered unit shift registers (B2, B4 ...) Of the series shift registers 41b are clock signals CLB *.
The bit signal 255 is output in response to the falling edge of the pulse. Then, based on the bit signals 252 to 255, each analog switch of the analog switch unit 45 operates to hold each video signal V supplied via video1, video2, and video3 in each source line. Therefore, the operation speed of the source line drive circuit 40 can be increased because the substantial transmission timing of the bit signal is increased in frequency without increasing the operation frequency of the thin film transistor of the shift register 41.

As described above, the source line drive circuit 4 of this example
At 0, the shift register 41 of the source line drive circuit 40 shifts the A series to the first shift register formation region 42a on the outer peripheral edge side of the substrate and the second shift register formation region 42b on the pixel matrix formation region side. Register 4
1a and a B-series shift register 41b are formed separately, and the first shift register formation region 42a is formed.
And the second shift register formation region 42b are formed in parallel, the area occupied by the unit shift registers A1, B1, A2, B2, ... Per bit is the same as that of the conventional source drive circuit. However, the pitch of the unit cells of the source line drive circuit 40 is narrowed.
Therefore, the pixel pitch of the pixel matrix can be narrowed to improve the display quality. Here, the clock signals CKA (CLA, CLA *), C
Of the A-series and B-series clock signal lines 43 and 44 that supply KB (CLB, CLB *), the A-series clock signal line 43 is arranged in parallel at a position adjacent to the first shift register formation region 42a. Since the B-series clock signal line 44 is arranged in parallel at a position adjacent to the second shift register formation region 42b, the clock signal input line 49a from each clock signal line 43, 44 to the shift register 41 is formed. , 49b have the same wiring length and the shortest wiring length between the A series and the B series. Therefore, the problem that the clock signals CKA and CKB are not synchronized due to the difference in wiring resistance or the difference in parasitic capacitance does not occur, so that the shift register 41 does not malfunction and the reliability of the active matrix panel is high. The A-series clock signal line 43 is formed on the outer peripheral edge side of the substrate with respect to the first shift register formation region 42a.
Since the B-series clock signal line 44 is formed on the pixel matrix formation region side (direction of arrow Y) with respect to the second shift register formation region 42b, the first and second shift register formation regions 42a, Since the clock signal input lines 49a and 49b do not pass through 42b, the unit shift registers A1, B1, A2, B2, ... Can be formed in close proximity to each other.

[Embodiment 2] FIG. 6 is a block diagram of a source line driving circuit side of an active matrix panel (liquid crystal display panel) according to Embodiment 2 of the present invention. FIG. 6 shows the shift register and clock signal line thereof. The arrangement relationship of is shown. Here, the overall configuration of the active matrix panel of the present example is similar to that of the block diagram shown in FIG. 9, and thus the description of the overall configuration is omitted. Further, among the shift register, the buffer circuit, and the analog switch section which form the source line drive circuit, the configurations of the buffer circuit and the analog switch section are the same as those of the active matrix panel of the first embodiment, and moreover, the shift register and the buffer are also provided. Since the circuit elements constituting the circuit and the analog switch section are the same as those of the active matrix panel of the first embodiment,
The active matrix panel of this example will be described based on only the block diagram of FIG.

In FIG. 6, the source line drive circuit 50 of the active matrix panel of this example is made into four series, and the source line drive circuit 50 is a pixel matrix and gate line drive circuit (neither is shown). It is also formed on the same transparent substrate and drives the display operation of each pixel of the pixel matrix. Further, the source line driving circuit 50 is formed between the outer peripheral edge of the substrate and the pixel matrix formation region, and the shift register 51 thereof is the first shift register on the outer peripheral edge side (direction of arrow X) of the substrate. It is formed by being divided into a formation region 52a and a second shift register formation region 52b on the pixel matrix formation region side (direction of arrow Y). Of these first and second shift register formation regions 52a and 52b, the unit shift register A1,
The A-series shift register 51a composed of A2 ... and the C-series shift register 51c (first shift register) composed of the unit shift registers C1, C2 ... In the register formation area 52b, a B series shift register 51b including unit shift registers B1, B2 ... And a D series shift register 51d (second shift register) including unit shift registers D1, D2. They are formed alternately. Here, the clock signal C is supplied to the A-series shift register 51a and the C-series shift register 51c.
The A-series clock signal line 53 and the C-series clock signal line 54 (first clock signal line) for supplying KA and CKC are arranged in parallel at positions adjacent to the first shift register formation region 51a. The B series clock signal line 55 and the D series clock signal line 56 (second clock signal line) for supplying the clock signals CKB and CKD to the B series shift register 51b and the D series shift register 51d are 2 shift register formation region 5
It is arranged in parallel at a position adjacent to 1b. The A-series clock signal line 53 and the C-series clock signal line 54 are formed on the outer peripheral edge side (in the direction of arrow X) of the substrate with respect to the first shift register formation region 52a. The clock signal line 55 of the series and the clock signal line 56 of the D series are on the pixel matrix formation region side (arrow Y) with respect to the second shift register formation region 52b.
Direction). Here, the wiring length of the clock signal input line 59a from the A-series clock signal line 53 (first clock signal line) to the A-series shift register 51a and the B-series clock signal line 55 (second clock signal). The wiring length of the clock signal input line 59b from the line) to the B-series shift register 51b is designed to have the same size and the shortest size. Similarly, from the C-series clock signal line 54 (first clock signal line) to C
The wiring length of the clock signal input line 59c to the series shift register 51c, and the D series clock signal line 56 (second clock signal line) to the D series shift register 51c.
The wiring lengths of the clock signal input lines 59d up to d are designed to have the same size and the shortest size. Also, A
Series clock signal line 53 and C series clock signal line 5
4 is close to and parallel to each other, and the B-series clock signal line 55 and the D-series clock signal line 56 are close to and parallel to each other. Therefore, any of the clock signal input lines 59a, 59b, The wiring lengths of 59c and 59d are also approximately the same size.

The second shift register forming region 52
On the pixel matrix formation region side (direction of arrow Y) with respect to b, the bit signal from each unit shift register of the shift register 51 is sample-holded, that is, the analog switch unit 65 side (pixel matrix side). A bit signal line 66 for sending the signal to the analog switch unit 65 is formed in the middle of the bit signal line 66 by delaying the bit signal sent to the analog switch section 65 side. B-series clock signal lines 55 and D-series clock signal lines 56 on the side where the output lines 66 intersect.
The buffer circuit 67 that should mitigate the effect of noise from
Similar to the first embodiment, it is composed of two inverters. Here, by delaying the bit signal, the B-series clock signal line 55 on the side where the bit signal output line 66 intersects.
As the buffer circuit 67 for mitigating the influence of noise from the D-series clock signal line 56, a resistance parasitic on the high resistance bit signal output line 66 formed of a polycrystalline silicon wiring layer and a bit signal output line 66 and B series and D series clock signal lines 55, which are aluminum wiring layers,
It is also possible to use a circuit utilizing a parasitic capacitance formed by an interlayer insulating film interposed between the circuit 56 and 56, or a clocked gate.

Also in the present example, each of the clock signal lines 53, 54, 55 and 56 is composed of two clock signal lines for supplying clock signals of mutually opposite phases, and the clock signals of the A to D series are provided. Of the shift registers 51a to 51d, odd-numbered unit shift registers A1, C1, B1,
D1 ... and even-numbered unit shift registers A2 and C
2, B2, D2, ... Are driven by clock signals having opposite phases. In addition, the clock signal line 5 of A series
3, the phase of the clock signal CKA from the B series, the phase of the clock signal CKB from the B series clock signal line 55, the phase of the clock signal CKC from the C series clock signal line 54, and the clock signal from the D series clock signal line 56. C
The phases of KD can be shifted by 45 ° from each other and can be driven in four series. Therefore, the operation speed of the source line driving circuit 50 can be increased without increasing the frequency of the operation of the thin film transistor forming the shift register 51.

As described above, the source line drive circuit 5 of this example
Also in 0, as in the first embodiment, the shift register 41
Is the first shift register formation region 52 on the outer peripheral edge side of the substrate.
a and a second shift register forming area 52b on the side of the pixel matrix forming area are divided and formed as A series and C series shift registers 51a and 51c and B series and D series shift registers 51b and 51c. Moreover, since the first shift register formation region 52a and the second shift register formation region 52b are formed in parallel, the unit shift register A per bit is formed.
The area occupied by 1, B1, C1, D1, A2, B2 ... Is equivalent to that of the conventional source drive circuit, but the pitch of the unit cells of the source line drive circuit 50 is narrowed. Therefore, the pixel pitch of the pixel matrix can be narrowed to improve the display quality. Here, among the A-series to D-series clock signal lines 53 to 56, the A-series and C-series clock signal lines 53 and 54 are arranged in parallel at positions adjacent to the first shift register formation region 52a. , B series and D series clock signal lines 5
Since the wirings 5 and 56 are arranged in parallel at positions adjacent to the second shift register formation region 52b, the wiring lengths of the clock signal input lines 59a to 59d from the respective clock signal lines 53 to 56 to the shift register 41. Can be designed to have the same size and the shortest size for each series. Therefore, the synchronization deviation of the clock signals CKA, CKB, CKC, and CKD due to the difference in wiring resistance or the difference in parasitic capacitance does not occur. Therefore, no malfunction occurs in the shift register 51, and the reliability of the active matrix panel is high.

As shown in FIG. 7, B series and D series
The bit signal output line 66a from the series shift registers 51b and 51d to the analog switch 65 side is once extended from the second shift register formation region 42b toward the outer peripheral edge side (direction of arrow X) of the substrate. , And from there, by extending toward the analog switch 65 side, B series and D series shift registers 51b, 51
The wiring length of the bit signal output line 66a from d to the analog switch 65 side is substantially the same as the wiring length of the bit signal output line 66b from the A series and C series shift registers 51a and 51c to the analog switch 65 side. By adjusting the dimensions, it is possible to suppress the deviation of the synchronization of the bit signals.

[Embodiment 3] FIG. 8 is a block diagram of a source line drive circuit side of an active matrix panel (liquid crystal display panel) according to an embodiment of the present invention. FIG. 8 shows the shift register and clock signal lines. The arrangement relationship is shown. Here, the overall configuration of the active matrix panel of the present example is also similar to that of the block diagram shown in FIG. 9, so description of the overall configuration will be omitted. Further, among the shift register, the buffer circuit, and the analog switch section which form the source line drive circuit, the configurations of the buffer circuit and the analog switch section are the same as those of the active matrix panel of the first embodiment, and moreover, the shift register and the buffer are also provided. Since the circuit elements constituting the circuit and the analog switch section are the same as those of the active matrix panel of the first embodiment, the active matrix panel of the present example will be described based only on the block diagram of FIG.

In FIG. 8, the source line drive circuit 7 of this example.
0 is a 1-series driving method, and the source line driving circuit 70
Are formed on the same transparent substrate together with the pixel matrix and the gate line drive circuit (both not shown), and drive the display operation of each pixel of the pixel matrix. Further, the source line drive circuit 70 is formed between the outer peripheral edge of the substrate and the pixel matrix formation region. In this example, the shift register 71 is formed as a first shift register on the outer peripheral edge side of the substrate. Region 72a and second shift register formation region 72b on the pixel matrix formation region side
It is formed by being divided into and. That is, of the first and second shift register formation regions 72a and 72b,
In the first shift register forming area 72a, the unit shift registers A1 driven by the clock signal CKA
A first shift register 71a including A4, A5 ...
On the other hand, a second shift register 71b including unit shift registers A2, A3, A6 ... Driven by the same clock signal CKA is formed in the second shift register formation region 72b. . Here, the clock signal CKA is supplied from the first clock signal line 73 to the first shift register 51a,
The clock signal lines 73 are arranged in parallel at positions adjacent to the first shift register formation region 71a. On the other hand, the clock signal CKA is supplied from the second clock signal line 74 to the second shift register 71b.
The clock signal line 74 is arranged in parallel at a position adjacent to the second shift register formation region 71b. Further, the first clock signal line 73 is formed on the outer peripheral edge side (in the direction of arrow X) of the substrate with respect to the first shift register formation region 72a, and the second clock signal line 74 is formed in the second shift register formation region. 72b is formed on the pixel matrix formation region side (direction of arrow Y). Furthermore, the wiring length of the clock signal input line 79a from the first clock signal line 73 to the first shift register 71a and the clock signal input line 79b from the second clock signal line 74 to the second shift register 71b. The wiring length is designed to have the same dimension and the shortest dimension. Further, the bit signal from the shift register 71 is supplied to the analog switch unit 7 on the pixel matrix formation region side (direction of arrow Y) with respect to the second shift register formation region 72b.
5, a bit signal line 76 for sending out to the side of 5 (pixel matrix side) is formed, and in the middle position, it is sent out to the side of the analog switch section 75 via the bit signal output line 76. A buffer circuit 77 for delaying a bit signal to mitigate the influence of noise from the second clock signal line 74 where the bit signal output line 76 intersects is configured by two inverters or the like as in the first embodiment. ing.

In the present example as well, the first and second shift registers 71a and 71b are both composed of the same circuit elements as in the first embodiment, while the clock signal lines 73 and 74 are The first shift register 71a and the second shift register 71a are configured by two clock signal lines that supply clock signals having opposite phases to each other, and can drive the first shift register 71a and the second shift register 71a with clock signals having opposite phases. Here, although both the first and second clock signal lines 73 and 74 can be configured by a single clock signal line, the first and second clock signal lines 73 and 74 are opposite in phase to each other. By configuring with two clock signal lines corresponding to the clock signal, the parasitic capacitance between the clock signal lines becomes equivalent and the clock signal on one side is delayed compared to the clock signal on the other side. Is prevented.

As described above, the source line drive circuit 7 of this example
Even in 0, the shift register 71 includes the first shift register formation region 72a on the outer peripheral edge side of the substrate and the second shift register formation region 72 on the pixel matrix formation region side.
Since the first shift register forming area 72a and the second shift register forming area 72b are formed in parallel with each other, the unit shift registers A1, A2 per bit are divided. The area occupied by A3 ... Is equal to that of the conventional source drive circuit, but the pitch of the unit cells of the source line drive circuit 70 is narrowed. Therefore, the pixel pitch of the pixel matrix can be narrowed to improve the display quality. Here, the first clock signal line 73 is arranged in parallel at a position adjacent to the first shift register formation region 72a, and the second clock signal line 74 is arranged in the second shift register formation region 7a.
Since it is arranged in parallel at a position adjacent to 2b,
The wiring lengths of the clock signal input lines 79a and 79b from the clock signal lines 73 and 74 to the shift register 41 are
It is designed to have the same size and the shortest size between each series.
Therefore, the clock signal CKA does not deviate in synchronization due to the difference in wiring resistance or the difference in parasitic capacitance. Therefore, since the shift register 71 does not malfunction, the reliability of the active matrix panel is high.

[0031]

As described above, according to the present invention, the first and second clock signal lines for transferring the first and second clock signals, which are arranged in parallel and are out of phase with each other, and the video signal are transferred. The video signal line adjacent to the first clock signal line, and the unit shift register shifts in synchronization with the first clock signal coming from the first clock signal line through the first clock signal input line. A first clock shift register for outputting signals serially and outputting n first bit output signals whose phases are sequentially shifted in parallel; and a second clock shift register parallel to the first clock shift register Adjacent to the signal line, the unit shift register serially outputs the shift signal in synchronization with the second clock signal coming from the second clock signal line through the second clock signal input line, and A second clock-based shift register that outputs in parallel m second bit output signals that are out of phase with each other, and a video signal to a signal line in the pixel region based on the first bit output signal that passes through the first bit output line. N first signal line-specific switch means for pulling in, and m second second signal lines for pulling in a video signal to another signal line in the pixel region based on the second bit output signal via the second bit output line. And the second clock signal line is located closer to the pixel area than the first clock signal line,
The first and second switch means for each signal line is a drive circuit of an active matrix panel which is located closer to the pixel region than the second clock signal line and is parallel to the second clock signal line, The first and second clock-specific shift registers are sandwiched inside the first and second clock lines, and the first clock signal input line does not intersect with the second clock-specific shift register. The second clock signal input line is connected to the second clock shift register without intersecting with the first clock shift register .
Supply power to the first and second shift registers for each clock
One of the power supply lines to be used is the first clock signal
Placed between the line and the first clock-wise shift register
And the other power supply line is the second clock signal line
Between the second shift register for each clock and
Since it is characterized by the fact that it has the following effects.

Since the first and second shift registers for each clock are driven by the first and second clock signals whose phases are shifted from each other, the driving circuit can be operated at high speed and per bit. Even if the unit shift register occupies the same area as the conventional one, adjacent unit shift registers in each shift register can be packed and arranged, so that the pixel pitch can be narrowed and high definition can be realized. In particular, the first and second clock-specific shift registers arranged in parallel are sandwiched inside the first and second clock lines arranged in parallel, and the first clock signal input line is divided into second clock signals. The second clock signal input line is connected to the first clock-specific shift register without intersecting with the shift register, and the second clock signal input line is connected to the second clock-specific shift register without intersecting with the first clock-specific shift register. Tei order, aims to minimize and the length of the first and second clock signal input lines, not only can prevent a malfunction of the high-speed shift operation, amount that lead wiring length of the second bit output line increases and, On the contrary, it is possible to approach the relatively long lead-out wiring length of the first bit output line.
The wiring resistance of the bit output line can be equalized, and the second bit output line must cross the second clock signal line in the same manner as the first bit output line. By equalizing the number of crossings between the second bit output line and the second clock signal line, it is possible to equalize the parasitic capacitance at the crossing portions and suppress the timing shift between the first and second bit output signals. The display quality can be improved. On the contrary, since no clock signal line is sandwiched between the first and second shift registers for each clock, the shift signal output from the unit shift register is provided between the first and second shift registers for each clock. Is not limited to the shift signal line for inputting to the unit shift register of the subsequent stage in the clock-by-clock shift register to which the unit shift register belongs, and the shift signal output from the unit shift register does not belong to the other unit shift register. Since the shift signal line for inputting to the unit shift register of the same stage in the clock shift register can also be formed between the first and second clock shift registers, it is possible to mix shift signals. The first and second shift registers for each clock are mutually dependent, and the first and second shift registers are out of phase with each other. Despite driven by a clock signal, apparently, it becomes possible to better single shift register in synchrony, it contributes to improvement of display quality.

[0033]

[0034]

[0035]

[Brief description of drawings]

FIG. 1 is a block diagram showing an arrangement of respective constituent parts of a source line drive circuit in an active matrix panel according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an arrangement relationship between a thin film transistor and a wiring layer included in the source line driving circuit shown in FIG.

3A and 3B are explanatory views showing a modified example of the buffer circuit used in the source line driving circuit shown in FIG. 1, in which FIG. 3A is a plan view of an intersection of a bit signal output line and a clock signal line, and FIG. )
Is a cross-sectional view thereof, and (c) is a configuration diagram of a buffer circuit configured by a resistance and a capacitance parasitic thereto.

4A is a block diagram showing a configuration of a shift register of the source line driving circuit shown in FIG. 1, FIG. 4B is a configuration diagram of an inverter used in the shift register, and FIGS. It is a block diagram of the clocked inverter used for the shift register.

5 is a timing chart of signals input to and output from various parts of the source line drive circuit shown in FIG.

FIG. 6 is a block diagram showing an arrangement of each component of a source line drive circuit in an active matrix panel according to Example 2 of the present invention.

FIG. 7 is a block diagram showing an arrangement of each component of a source line drive circuit in an active matrix panel according to a modification of the second embodiment of the present invention.

FIG. 8 is a block diagram showing an arrangement of each component of a source line drive circuit in an active matrix panel according to Example 3 of the present invention.

FIG. 9 is a block diagram showing the overall configuration of an active matrix panel.

FIG. 10A is a block diagram of a two-line source line drive circuit of an active matrix panel according to a reference example, and FIG. 10B is an explanatory diagram showing a function of a shift register which constitutes the source line drive circuit.

11 is a block diagram showing the function of each component of the source line drive circuit having two lines in the active matrix panel shown in FIG.

FIG. 12 is a block diagram on the side of a source line drive circuit in which the active matrix panel according to the reference example is made into four series.

[Explanation of symbols]

11 ... Transparent substrate 12, 40, 50, 70, 80, 90 ... Source line drive circuit 13, 20, 41, 51, 71, 81, 91 ... Shift register 17, 18, 19 ... Sample-hold circuit 21 ... Gate line drive circuit 22 ... Pixel matrix 24, 25 ... Gate lines 26, 27, 28 ... Source line 29 ... Thin film transistor 30 ... Liquid crystal cells 34, 37, 83, 84, 92 to 95 ... Clock signal lines 41a, 51a ... A series shift register (first shift register) 41b, 51b ... B series shift register (second shift register) 42a , 52a, 72a ... Second shift register formation regions 42b, 52b, 72b ... Second shift register formation regions 43, 53 ... A series clock signal lines (second 44,55 ... B series clock signal lines (second clock signal lines) 45, 65, 75, 85 ... Analog switch portions 46, 66, 66a, 66b, 76, 86. ..Bit signal output lines 47, 67, 77 ... Buffer circuits 49a, 49b, 59a to 59d, 79a, 79b, 8
9a, 89b ... Clock signal input line 51c ... C series shift register (first shift register) 51d ... D series shift register (second shift register) 54 ... C series clock Signal line (first clock signal line) 56 ... D series clock signal line (second clock signal line) 83, 84, 92 to 95 ... Clock signal line

Claims (5)

(57) [Claims] 1. A parallel arrangement of first and second clock signal lines for transferring first and second clock signals, which are out of phase with each other, a video signal line for transferring a video signal, and a first Adjacent to the first clock signal line, the unit shift register serially outputs the shift signal in synchronization with the first clock signal coming from the first clock signal line through the first clock signal input line, and sequentially. A first clock-by-clock shift register that outputs n first-bit output signals out of phase in parallel; a second clock signal line that is parallel to the first clock-by-clock shift register and adjacent to a second clock signal line; The unit shift register serially outputs the shift signal in synchronization with the second clock signal coming from the second clock signal input line through the second clock signal input line, and the m second phase shift registers are sequentially shifted in phase. Second to output bit output signals in parallel
A clock-by-clock shift register, n first signal line-by-line switch means for pulling the video signal into a signal line in the pixel region based on the first bit output signal through the first bit output line, and a second Second signal output switch means for pulling the video signal to another signal line in the pixel region based on the second bit output signal via the bit output line of the second clock signal. The line is located closer to the pixel region than the first clock signal line, and the first and second signal line-specific switch means is located closer to the pixel region than the second clock signal line and is the second clock. A drive circuit for an active matrix panel formed in parallel with a signal line, wherein first and second clock-by-clock shift registers are sandwiched inside the first and second clock lines. A clock signal input line is connected to the first clock-specific shift register without intersecting the second clock-specific shift register, and the second clock signal input line is the first clock-specific shift register. Connected to the second clock-wise shift register without crossing the
Supply power to the 1st and 2nd clock shift registers
One of the power supply lines is the first clock signal.
Between the signal line and the first shift register for each clock.
Is installed and the other power line is connected to the second black line.
Between the clock signal line and the second shift register for each clock
A drive circuit for an active matrix panel, characterized in that it is arranged between them . 2. The drive circuit for an active matrix panel according to claim 1, wherein the second clock line and the first clock line are in the middle of the first and second bit output lines.
And a driving circuit for the active matrix panel, wherein a buffer circuit is interposed between the switching means and the second bit-by-bit switch means. 3. A drive circuit for an active matrix panel according to claim 2, wherein the first bit output line is drawn from the first clock by the shift register to the second clock by the shift register side the A drive circuit for an active matrix panel, characterized in that the drive circuit is connected to a switch means for each first bit. 4. The driving circuit for an active matrix panel according to any one of claims 1 to 3, wherein the first clock signal and the second clock signal and phase to each other are shifted 90 ° A clock signal,
The first clock signal line is a pair of clock signal lines for transferring a positive-phase signal of the first clock signal and an opposite-phase signal thereof, and the second clock signal line is a positive-phase signal of the second clock signal. A drive circuit for an active matrix panel, which is a pair of clock signal lines for transferring a signal and its opposite phase signal. 5. An active matrix panel characterized by comprising the active matrix panel drive circuit defined in any one of claims 1 to 4 .