CN100501992C - 用于针对加密应用实现安全多芯片模块的方法和结构 - Google Patents
用于针对加密应用实现安全多芯片模块的方法和结构 Download PDFInfo
- Publication number
- CN100501992C CN100501992C CNB2006100651987A CN200610065198A CN100501992C CN 100501992 C CN100501992 C CN 100501992C CN B2006100651987 A CNB2006100651987 A CN B2006100651987A CN 200610065198 A CN200610065198 A CN 200610065198A CN 100501992 C CN100501992 C CN 100501992C
- Authority
- CN
- China
- Prior art keywords
- chip carrier
- module according
- conductive grid
- circuit
- grid structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
- G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
- G06K19/07372—Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit
- G06K19/07381—Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit with deactivation or otherwise incapacitation of at least a part of the circuit upon detected tampering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/57—Protection from inspection, reverse engineering or tampering
- H01L23/576—Protection from inspection, reverse engineering or tampering using active circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0275—Security details, e.g. tampering prevention or detection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09263—Meander
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10151—Sensor
Abstract
一种防篡改的集成电路(IC)模块,包括陶瓷基芯片载体,一个或多个连接到该芯片载体的集成电路芯片,以及连接到该芯片载体的覆盖该一个或多个集成电路芯片的帽盖结构。在该芯片载体和该帽盖结构中形成导电栅格结构,该导电结构具有部署在x方向、y方向和z方向上的多条迂回线路。该导电栅格结构配置为检测对该IC模块进行入侵的尝试。
Description
技术领域
本发明一般地涉及集成电路器件和封装方法,并且更特别地涉及针对加密应用实现安全多芯片模块(MCM)的方法和结构。
背景技术
FIPS(联邦信息处理标准)140-1是美国政府标准,用于实现加密模块,即对数据进行加密和解密或执行其他加密操作(诸如创建或验证数字签名)的硬件或软件。FIPS 140-1标准由NIST(美国国家标准与技术协会)创建,并为正确地设计和实现执行加密的产品规定了要求。
特别地,FIPS 140-1规定了用于保护计算机和电信系统(包括语音系统)中未分类的信息的安全系统中的加密模块必须满足的要求。该标准提供了四个安全性渐增的安全级别(第1级、第2级、第3级和第4级),这些级别旨在覆盖较宽范围的可以采用加密模块的可能的应用和环境。每个安全级别提供了比前一级别更高的安全性。这四个渐增的安全级别考虑了适合于不同程度的数据敏感性和不同的应用环境的具有成本效率的解决方案。
例如,安全级别1提供了最低的安全级别。其规定了对加密模块的基本安全要求,但在该模块中不要求对生产级(production-grade)设备的要求之外的任何物理安全机制。第1级系统的例子包括集成电路(IC)卡和附加(add-on)安全产品。第1级使得软件加密功能可以在通用个人计算机(PC)上执行。
安全级别2通过添加对防篡改(tamper-evident)涂层或封印或者对防盗锁(pick-resistant lock)的要求提高了安全级别1加密模块的物理安全性。可以将如今可获得的防篡改涂层或封印置于加密模块上,使得要实现对该模块中的明文密钥和其他关键安全参数的物理访问,就必须破坏该涂层或封印。可以将防盗锁置于封盖或封口上,以防止未授权的物理访问。此外,第2级提供基于角色的认证,其中模块必须验证操作者是经授权来担当特定角色并执行一组相应任务的。第2级还考虑了在多用户分时系统中结合可信操作系统而使用的软件加密。
安全级别3甚至还要求增强的物理安全措施,其中很多措施可以在现有的商用安全产品中获得。与安全级别2(其采用锁来防止对加密模块的篡改,或者采用涂层或封印来检测何时发生篡改)相比,第3级试图防止入侵者获得对存储在该模块中的关键安全参数的访问权限。例如,嵌入了多个芯片的模块必须包含在强大的外壳中,其中如果将封盖移走或将封口打开,则关键安全参数回零(即通过改变其内容来进行电擦除)。作为替代,可以将模块封装在坚硬的、不透明的陶瓷制造(potting)材料中以阻止对这些内容的访问。
除了其他方面,第3级还提供了基于身份的认证,其比第2级中所用的基于角色的认证更强大。模块必须认证操作者的身份并验证该已标识的操作者是经授权来担当特定角色并执行一组相应任务的。
最后,安全级别4提供了最高的安全级别。尽管大多数现有产品都不符合这一安全级别,但市面上出售的某些产品符合第4级要求中的很多要求。第4级物理安全性提供了包围加密模块的保护封套。鉴于较低级别的模块的篡改检测电路可能被旁路,第4级保护的目的是检测从任意方向对该器件的入侵(penetration)。例如,如果进行突破加密模块的外壳的尝试,则应当检测到这种尝试并且此后所有的关键安全参数将回零。第4级器件对于入侵者有可能篡改器件的、物理上未受保护的环境中的操作特别有用。
第4级还防止模块由于超出该模块的电压和温度的正常操作范围的环境条件或环境波动而损及其安全性。有意地偏移到正常操作范围之外有可能被用来阻止模块在受到攻击器件进行防御。因此,模块必须包括设计为检测波动和并使关键安全参数回零的特定环境保护特征,或者必须经受严格的环境故障测试,这种测试合理地确保了该模块不会受到会损及该模块的安全性的超出正常操作范围的波动的影响。
遗憾的是,符合第4级安全要求的现有多芯片模块(MCM)实现上比较困难并且设计上比较烦琐,其包括例如罐封易碎的网孔卡结构。此外,这种设计为期望的电磁(EM)屏蔽提供了有限的容量。又一个困难来自于将现有加密模块从有机衬底材料改变为陶瓷基材料,原因是陶瓷材料表现出某些互连问题,诸如最近的邻居由于焊接球的脱落而缺少球栅格阵列。此外,完全脱落的结构将具有较低的互连高度,这接着会在整个器件的互连高度之间导致较大百分比的变化。最后的互连的脱落高度还会导致短路或开路。
因此,希望实现用于加密应用的能够克服这些缺点的安全多芯片模块(MCM)。
发明内容
通过一种防篡改的集成电路(IC)模块来克服或减轻现有技术的上述缺点和缺陷。在一个示例性的实施例中,该IC模块包括陶瓷基芯片载体,一个或多个连接到该芯片载体的集成电路芯片,以及连接到该芯片载体的覆盖该一个或多个集成电路芯片的帽盖结构。在该芯片载体和该帽盖结构中形成导电栅格结构,该导电结构具有部署在x方向、y方向和z方向上的多条迂回线路。该导电栅格结构配置为检测对该IC模块进行入侵的尝试。
在另一个实施例中,一种用于集成电路(IC)模块的安全帽盖结构包括金属化的陶瓷顶部和与该顶部集成的底座。该底座配置为连接到该IC模块的芯片载体,使得当帽盖结构连接到芯片载体时,该底座包围连接到芯片载体的一个或多个IC芯片。
在又一个实施例中,一种防篡改的集成电路(IC)模块包括陶瓷基芯片载体,一个或多个连接到该芯片载体的集成电路芯片,以及连接到该芯片载体的陶瓷基帽盖结构。该帽盖结构包括顶部和集成于其上的底座,该底座包围连接到芯片载体的一个或多个IC芯片。在该芯片载体和该帽盖结构中形成导电栅格结构,该导电栅格结构具有部署在x方向、y方向和z方向上的多条迂回线路,其中该导电栅格结构配置为检测对该IC模块进行入侵的尝试。
在又一个实施例中,公开了一种用于实现防篡改的集成电路(IC)模块的方法,该IC模块包括陶瓷基芯片载体,一个或多个连接到该芯片载体的集成电路芯片,以及连接到该芯片载体的陶瓷基帽盖结构。该方法包括在该芯片载体和该帽盖结构中形成导电栅格结构,该导电栅格结构具有部署在x方向、y方向和z方向上的多条迂回线路。该导电栅格结构配置为通过检测该导电栅格结构的电阻的变化和电容的变化或电感的变化中的至少一种变化来检测对该IC模块进行入侵的尝试。
附图说明
参考示例性附图,其中在多个图形中相同的元件以相同的方式编号:
图1是根据本发明实施例而配置的MCM安全模块的示意性截面视图;
图2示出包括在图1的安全模块的陶瓷芯片载体和/或帽盖结构中的迂回线路的示例性x-y布局;
图3示出了图1的安全模块的示例性垂直迂回线路;
图4(a)示出了以大约50微米(μm)的示例性宽度和大约200μm的示例性间距形成的迂回线路的截面;
图4(b)示出了以大约50微米(μm)的示例性宽度和大约150μm的示例性间距形成的迂回线路的截面;
图5示出了四个相邻的布线层上的迂回线路之间的关系,第一偏移对在x方向上延伸并且第二偏移对在y方向上延伸;
图6是示例性桥接结构的示意图,可以对该桥接结构进行配置,以便检测迂回线路的任意组合之间的开路情况或短路情况;
图7是根据本发明的另外的实施例的相对于图6的增强的检测电路的示意图;
图8是根据本发明的另外的实施例的金属化陶瓷帽盖结构的示意图;并且
图9是沿图8的线9-9所取的金属化帽盖结构的俯视截面视图。
具体实施方式
在此公开了一种用于针对基于例如FIPS 140-1标准的安全级别4的加密应用实现安全多芯片模块(MCM)的方法和结构。简而言之,除用于防止和阻隔对IC芯片的访问的帽层之外,陶瓷基芯片安全模块组件还具有连接一个或多个集成电路芯片的芯片载体。同时为陶瓷芯片载体和帽层提供保护性导电栅格,在x方向、y方向和z方向上在该导电栅格中形成迂回安全线路。除提供入侵检测(通过监控方法,诸如电介质阻抗偏移和电阻偏移检测)之外,这些安全线路还配置为提供电磁屏蔽。
首先参考图1,其中示出根据本发明的实施例而配置的MCM(或SCM)安全模块100的示意性截面视图。多个集成电路芯片102(例如处理器、存储器、嵌入存储器)具有附着于其上的多个焊接球104,以便机械连接和电连接到芯片载体106。芯片载体106的特征还在于板-模块互连(I/O)107,该板-模块互连107例如可以是球栅格阵列(BGA)类型、柱栅格阵列(CGA)类型或接点栅格阵列(LGA)类型。可以用密封材料(例如环氧化物)来对IC芯片102和/或焊接球104进行封装或孔型填装(underfill),以减小由于芯片和芯片载体材料之间的热膨胀失配而在焊接球104上产生的压力。还应当意识到,芯片载体106可以具有附着于其上的其他组件,诸如电容器、电阻器和类似的分立器件(未示出)。
还提供帽盖部分108以安全地包围连接到芯片载体106的IC芯片102。在所示的实施例中,芯片载体106和帽盖部分108都可以是例如多层陶瓷或层状/组织结构。将每个部分制造为可以在其间的接口上对内部布线进行访问。这使得在帽盖部分108诸如通过使用导电粘合互连109(例如焊接球)连接到芯片载体106时,外围的电网络可以包围所得到的包含芯片的内部空腔。如图所示,该网络的特征在于既是篡改检测结构(例如导电栅格)又是电磁(EM)屏蔽结构。
更具体地说,篡改检测结构包括嵌入在芯片载体106和帽盖部分108中的多条安全迂回线路110。迂回线路110配置为同时在x-y方向和垂直(z)方向上延伸,使得当该结构受到来自任意方向的入侵时,可检测到这些线路的电阻和/或阻抗的变化。同样在图1中示出的是包围迂回线路110和IC 102并同时延伸到芯片载体106和帽盖部分108中的电磁干扰(EMI)屏蔽112。EMI屏蔽112以与安全迂回线路110相似的方式而构造,但却形成了完全闭合的路径以限制来自IC102的辐射能量。
图2和图3更具体地示出了迂回线路110的配置和篡改检测特性。在图2中,针对芯片载体106或帽盖部分108的示例层示出了这些迂回线路的x-y布局,而图3示出了示例性的垂直迂回线路,其中来自一个层的折弯114通过充满导电材料的通道108而连接到另一个层中的折弯116。
一个层上的各迂回线路110之间的间隔排列为在给定层上实现可靠的吞吐量,但同时还要防止机械入侵进行探测尝试。例如,图4(a)示出了以大约50微米(μm)的示例性宽度w和大约200μm的示例性间距p形成的平行迂回线路110的一部分。通过使得这些迂回线路在相邻层上进行偏移(即形成交叉的排列),在z方向上形成50μm的有效间距。在图4(b)中,以大约150μm的间距形成50μm宽的线路,并且因此相邻层上的交叉线路形成甚至更紧密的有效间距以检测入侵物体。此外,当线宽超过了标称线粗时,该有效间距变得甚至更紧密。图5示出了四个相邻的布线层上的迂回线路之间的关系,第一偏移对在x方向上延伸并且第二偏移对在y方向上延伸。
现在参考图6,其中示出了示例性桥接结构120,可以对该桥接结构120进行配置,以便检测迂回线路110的任意组合之间的开路情况或短路情况。由于迂回线路110很有可能具有量级为数十欧的电阻,因此对每个迂回线路使用相应的一系列分立电阻器122。这将电路阻抗级别保持在足够高的值上,以便防止使供电电池124过早放电而产生过大的电流。电阻器122可以通过放置分立部件来实现,或者作为替代,将电阻器122集成为陶瓷层本身的布线构图的一部分。将跨桥接结构120的相对侧的连接点制成桥接检测电路126,桥接检测电路126还可以形成于连接到芯片载体106的单独芯片上或实现为一个现有芯片(例如闪存、静态存储器、处理器)上的宏指令。
然而,在图6的DC(直流)桥接结构120中采用电阻器122的一个潜在缺点是电路对跨一个或多个迂回线路110配备旁路跳线连接的敏感性妨碍了对旁路线路中的破坏的检测。由于短路迂回线路的电阻变化的数量级大约为1Ω或更小,因此这种变化会被相应的一系列电阻器122的值完全消解掉。换言之,桥接检测电路126可能不具有足够的敏感性以检测具有相对较高的电阻的桥接电路的一个支路(leg)中的相对较小的DC电阻变化。因此,作为替代的篡改检测方案可以对检测电路使用AC(例如正弦波)或其他时变信号,以便能够检测到如相位之类的附加参数的变化。同样,仍希望以消耗相对较少的电量的方式来实现这种方案。
相应地,图7是根据本发明的另外的实施例的相对于图6的增强的检测方案700的示意图。如图所示,信号发生器702配置为向对幅度和相位都敏感的检测电路704提供诸如AC或脉冲输出之类的时变信号。作为采用电阻器的替代,定时器电路706间歇地将电池电源124连接到信号发生器702以及连接到检测电路704以便省电。通过以较低的占空因数为信号发生器702供电以节省电池电量,检测方案700可以包含对幅度和相位都敏感的检测电路704,还通过与驱动电路(即信号发生器702)相同的占空因数来对该检测电路704进行供电。对幅度和相位都敏感的检测电路704可以检测诸如使用探针、尝试的跳线和断线、溶液以及其他类型的入侵方法进行的入侵所导致的迂回线路110的电阻、电感和电容的参数变化。
因此,可获得的高级别的电路集成、数字信号处理和混合的信号技术可以得到优化的检测方法。出于这种考虑的可能技术可以包括例如TDR(时域反射)和TDT(时域传输)。这些方法可以通过将当前的响应信号与已初始化的标准(例如,其对每个衬底可以是唯一的)相比较来利用脉冲形状和到达时间的差异。此外,假定可在期望的功率预算内实现在不同的频率上检查相位的时域方法和频域方法的组合,则可以采用这些组合。同时采用保护结构的阻止篡改尝试的多种方法可以显著地增强安全性。
最后,图8和图9示出了根据本发明的另外的实施例的金属化的陶瓷帽盖结构800。作为采用到芯片载体的焊接表面连接的替代,帽盖结构的特征在于整体支架(或底座),该支架具有连接于其上的焊接圆角的内周和外周,不需要安装到载体的焊接球。除解决了近邻焊接短路的问题之外,本结构还防止了帽盖-载体互连与相邻部件之间的焊接溅射。
在图8的截面视图中特别地示出,帽盖结构800包括与底座804集成的顶部802,底座804包围并保护附着到载体808的各芯片806(例如处理器、存储器、嵌入存储器)。帽盖结构800可以由诸如铝之类的材料构成并且还可以包括诸如玻璃相添加剂之类的其他陶瓷组分以与陶瓷芯片载体808的热膨胀系数(CTE)相匹配。帽盖结构800还包含内部金属化,其可以包括诸如(例如)钼、钨、钛、镍、铜和金之类的材料。帽盖结构800上还可以包括表面金属化。
为了为安装在陶瓷载体808上的所有部件提供防篡改的第4级安全性,帽盖结构800必须能够抵挡通过诸如机械探测、钻孔和定向激光之类的任意的多种方法进行的入侵尝试。帽盖结构800的顶部802和芯片载体808都包括配置到细化的栅格构图中的内部布线。因此,如果这些布线“网”(net)被突破并且电路监控器件检测到随后的电阻或阻抗的变化,则该模块将自动地断电以防止对关键数据的访问。另一方面,对于通过周边底座804进行的入侵,围绕底座804的外部(和内部)而部署的多个焊接圆角810实现了至少两个功能。首先,圆角810在帽盖结构800、芯片载体808以及构图在其中的一系列分立的或连续的金属化线路之间提供永久的焊锡连接。其次,圆角810还通过放置在特定位置来提供安全功能。
更具体地说,图9示出了沿图8的线9-9所取的帽盖结构800的俯视截面视图。同样,帽盖结构800与芯片载体808之间的电连通性通过焊接圆角810来实现,可以围绕周边底座804的任一侧而形成焊接圆角810。金属化陶瓷帽盖结构800与芯片载体808之间的完全接触还通过在底座804与芯片载体808之间采用聚合物粘合层来实现。有意地将粘合层的厚度保持得较薄且不导电。
通过选择性地对底座804的垂直表面进行金属化来进一步限定焊接圆角810,以便限制焊料的浸润和扩散。优选地将相邻焊接圆角之间的间隔保持为最小,以便防止探针穿过两个相邻的焊接圆角之间。此外,应当将每个单独的焊接圆角810的宽度保持为最小,以便当电路的电阻或阻抗变化时,可以容易地检测到探针对焊接圆角的穿刺。在所示的实施例中,焊接圆角810沿底座804的内周和外周的排列使得内周上的每个圆角位于外周上的一对圆角之间,反之亦然。换言之,沿底座804的一侧的圆角相对于在相对侧上的圆角交错地设置。因此,如果要在外周上的圆角之间插入探针或某些其他的器械,并使其通过底座材料,则该器械还会与内周上的圆角发生接触。
尽管已经参考优选实施例对本发明进行了描述,但本领域的普通技术人员应当理解,在不偏离本发明范围的情况下,可以进行各种改变并且可以用等价形式替代其元件。此外,在不偏离本发明的本质范围的情况下,可以作出许多修改,以把特定的情形或材料适用于本发明的思想。因此,本发明并非旨在限于作为所考虑的用于执行本发明的最好模式而公开的特定实施例,本发明将包括在所附权利要求范围内的所有实施例。
Claims (33)
1.一种防篡改的集成电路IC模块,包括:
陶瓷基芯片载体;
一个或多个集成电路芯片,其附着于所述芯片载体;
帽盖结构,其连接到所述芯片载体,并覆盖所述一个或多个集成电路芯片;以及
在所述芯片载体和所述帽盖结构中形成的导电栅格结构,所述导电结构具有部署在x方向、y方向和z方向上的多条迂回线路;
其中所述导电栅格结构配置为通过检测所述导电栅格结构的电阻的变化和电容的变化中的至少一种变化来检测对所述IC模块进行入侵的尝试。
2.根据权利要求1所述的IC模块,其中形成于所述芯片载体的一个布线层上的迂回线路以相对于形成于所述芯片载体的相邻布线层上的迂回线路偏移的排列而部署。
3.根据权利要求2所述的IC模块,其中以选定线宽和其间的间距来形成所述x方向和所述y方向上的所述多条迂回线路,以使所述偏移排列在所述z方向上产生的有效间距等于或小于所述选定线宽。
4.根据权利要求1所述的IC模块,其中所述z方向上的所述迂回线路还包括形成于所述芯片载体的一个层上的折弯,所述折弯通过充满导电材料的通道而连接到形成于所述芯片载体的另一个层上的折弯。
5.根据权利要求1所述的IC模块,还包括桥接结构,其配置为检测所述导电栅格结构中的开路情况和短路情况中的至少一种情况。
6.根据权利要求5所述的IC模块,其中所述导电栅格结构中的所述多条迂回线路连接到相关联的电阻器件,以便限制连接到所述导电栅格结构的电源的放电量。
7.根据权利要求5所述的IC模块,其中所述桥接结构配置为检测所述导电栅格结构的电阻的变化和电容的变化中的至少一种变化。
8.根据权利要求5所述的IC模块,还包括:
信号发生器,其配置为向所述桥接结构提供时变输入;以及
检测电路,其连接到所述桥接结构,所述检测电路配置为具有相位和幅度敏感性。
9.根据权利要求8所述的IC模块,其中所述检测电路检测所述导电栅格结构的电容的变化和电感的变化中的至少一种变化。
10.根据权利要求9所述的IC模块,其中所述检测电路实现时域反射TDR和时域传输TDT中的至少一个。
11.根据权利要求8所述的IC模块,还包括定时器电路,其配置为根据期望的占空因数间歇地为所述信号发生器和所述检测电路提供电能。
12.根据权利要求1所述的IC模块,还包括包围所述一个或多个集成电路芯片的电磁干扰EMI屏蔽,所述EMI屏蔽形成于所述芯片载体和所述帽盖结构中。
13.根据权利要求12所述的IC模块,其中所述EMI屏蔽形成闭合路径,以便限制从所述一个或多个集成电路芯片辐射出来的能量。
14.根据权利要求1所述的IC模块,其中所述帽盖结构同时机械连接和电连接到所述芯片载体。
15.一种防篡改的集成电路IC模块,包括:
陶瓷基芯片载体;
一个或多个集成电路芯片,其连接到所述芯片载体;
陶瓷基帽盖结构,其连接到所述芯片载体,所述帽盖结构包括顶部和集成于其上的底座,所述底座包围连接到所述芯片载体的所述一个或多个IC芯片;以及
在所述芯片载体和所述帽盖结构中形成的导电栅格结构,所述导电栅格结构具有部署在x方向、y方向和z方向上的多条迂回线路;
其中所述导电栅格结构配置为通过检测所述导电栅格结构的电阻的变化和电容的变化中的至少一种变化来检测对所述IC模块进行入侵的尝试。
16.根据权利要求15所述的IC模块,其中形成于所述芯片载体的一个布线层上的迂回线路以相对于形成于所述芯片载体的相邻布线层上的迂回线路偏移的排列而部署。
17.根据权利要求16所述的IC模块,其中以选定线宽和其间的间距来形成所述x方向和所述y方向上的所述多条迂回线路,以使所述偏移排列在所述z方向上产生的有效间距等于或小于所述选定线宽。
18.根据权利要求15所述的IC模块,其中所述z方向上的所述迂回线路还包括形成于所述芯片载体的一个层上的折弯,所述折弯通过充满导电材料的通道而连接到形成于所述芯片载体的另一个层上的折弯。
19.根据权利要求15所述的IC模块,还包括桥接结构,其配置为检测所述导电栅格结构中的开路情况和短路情况中的至少一种情况。
20.根据权利要求19所述的IC模块,其中所述导电栅格结构中的所述多条迂回线路连接到相关联的电阻器件,以便限制连接到所述导电栅格结构的电源的放电量。
21.根据权利要求19所述的IC模块,其中所述桥接结构配置为检测所述导电栅格结构的电阻的变化和电容的变化中的至少一种变化。
22.根据权利要求19所述的IC模块,还包括:
信号发生器,其配置为向所述桥接结构提供时变输入;以及
检测电路,其连接到所述桥接结构,所述检测电路配置为具有相位和幅度敏感性。
23.根据权利要求22所述的IC模块,其中所述检测电路检测所述导电栅格结构的电容的变化和电感的变化中的至少一种变化。
24.根据权利要求23所述的IC模块,其中所述检测电路实现时域反射TDR和时域传输TDT中的至少一个。
25.根据权利要求22所述的IC模块,还包括定时器电路,其配置为根据期望的占空因数间歇地为所述信号发生器和所述检测电路提供电能。
26.根据权利要求15所述的IC模块,还包括包围所述一个或多个集成电路芯片的电磁干扰EMI屏蔽,所述EMI屏蔽形成于所述芯片载体和所述帽盖结构中。
27.根据权利要求26所述的IC模块,其中所述EMI屏蔽形成闭合路径,以便限制从所述一个或多个集成电路芯片辐射出来的能量。
28.根据权利要求15所述的IC模块,其中所述帽盖结构同时机械连接和电连接到所述芯片载体。
29.根据权利要求15所述的IC模块,还包括沿所述底座的外周和内周部署的多个焊接圆角,所述焊接圆角配置为在所述帽盖结构的内部布线和所述芯片载体的内部布线之间提供电连接。
30.根据权利要求25所述的IC模块,其中所述外周上的所述多个焊接圆角和所述内周上的所述多个焊接圆角彼此交错地设置。
31.一种用于实现防篡改的集成电路IC模块的方法,所述IC模块包括陶瓷基芯片载体,一个或多个连接到所述芯片载体的集成电路芯片,以及连接到所述芯片载体的陶瓷基帽盖结构,所述方法包括:
在所述芯片载体和所述帽盖结构中形成导电栅格结构,所述导电栅格结构具有部署在x方向、y方向和z方向上的多条迂回线路;
其中所述导电栅格结构配置为通过检测所述导电栅格结构的电阻的变化和电容的变化中的至少一种变化来检测对所述IC模块进行入侵的尝试。
32.根据权利要求31所述的方法,还包括通过所述帽盖结构的底座与所述芯片载体之间的聚合物粘合层将所述帽盖结构粘合到所述芯片载体,其中所述底座包围附着到所述芯片载体的一个或多个IC芯片。
33.根据权利要求32所述的方法,还包括:
沿所述底座的外周和内周形成多个焊接圆角,所述焊接圆角配置为在所述帽盖结构的内部布线和所述芯片载体的内部布线之间提供电连接;
其中所述外周上的所述多个焊接圆角和所述内周上的所述多个焊接圆角彼此交错地设置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/907,761 US7281667B2 (en) | 2005-04-14 | 2005-04-14 | Method and structure for implementing secure multichip modules for encryption applications |
US10/907,761 | 2005-04-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1855474A CN1855474A (zh) | 2006-11-01 |
CN100501992C true CN100501992C (zh) | 2009-06-17 |
Family
ID=37107554
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2006100651987A Active CN100501992C (zh) | 2005-04-14 | 2006-03-27 | 用于针对加密应用实现安全多芯片模块的方法和结构 |
Country Status (2)
Country | Link |
---|---|
US (3) | US7281667B2 (zh) |
CN (1) | CN100501992C (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102474977A (zh) * | 2009-07-07 | 2012-05-23 | 国际商业机器公司 | 保护密钥和代码的多层安全结构及其方法 |
Families Citing this family (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003102510A2 (en) * | 2002-06-04 | 2003-12-11 | Nds Limited | Prevention of tampering in electronic devices |
US7281667B2 (en) * | 2005-04-14 | 2007-10-16 | International Business Machines Corporation | Method and structure for implementing secure multichip modules for encryption applications |
WO2007091210A2 (en) * | 2006-02-09 | 2007-08-16 | Nxp B.V. | Circuit arrangement, data processing device comprising such circuit arrangement as well as method for identifying an attack on such circuit arrangement |
JP4349389B2 (ja) * | 2006-07-28 | 2009-10-21 | ソニー株式会社 | データ記憶装置、および、通信装置 |
US8117460B2 (en) * | 2007-02-14 | 2012-02-14 | Intel Corporation | Time-domain reflectometry used to provide biometric authentication |
US7710286B1 (en) | 2007-03-30 | 2010-05-04 | Maxim Integrated Products, Inc. | Intrusion detection using a conductive material |
US7923830B2 (en) * | 2007-04-13 | 2011-04-12 | Maxim Integrated Products, Inc. | Package-on-package secure module having anti-tamper mesh in the substrate of the upper package |
US7868441B2 (en) * | 2007-04-13 | 2011-01-11 | Maxim Integrated Products, Inc. | Package on-package secure module having BGA mesh cap |
US7615416B1 (en) | 2007-08-31 | 2009-11-10 | Maxim Integrated Products, Inc. | Secure package with anti-tamper peripheral guard ring |
US7898090B1 (en) | 2007-09-28 | 2011-03-01 | Ixys Ch Gmbh | General purpose ball grid array security cap |
US8552566B1 (en) | 2008-05-30 | 2013-10-08 | Maxim Integrated Products, Inc. | Integrated circuit package having surface-mount blocking elements |
US8332659B2 (en) * | 2008-07-29 | 2012-12-11 | International Business Machines Corporation | Signal quality monitoring to defeat microchip exploitation |
US8214657B2 (en) * | 2008-07-29 | 2012-07-03 | International Business Machines Corporation | Resistance sensing for defeating microchip exploitation |
US9003559B2 (en) * | 2008-07-29 | 2015-04-07 | International Business Machines Corporation | Continuity check monitoring for microchip exploitation detection |
US8172140B2 (en) * | 2008-07-29 | 2012-05-08 | International Business Machines Corporation | Doped implant monitoring for microchip tamper detection |
US7952478B2 (en) * | 2008-07-29 | 2011-05-31 | International Business Machines Corporation | Capacitance-based microchip exploitation detection |
US8012868B1 (en) * | 2008-12-15 | 2011-09-06 | Amkor Technology Inc | Semiconductor device having EMI shielding and method therefor |
WO2011128778A2 (en) * | 2010-04-17 | 2011-10-20 | Paypod, Ltd | Security techniques card payment terminal |
US20120279762A1 (en) * | 2011-05-03 | 2012-11-08 | Industry-Academic Cooperation Foundation, Yonsei University | Composition for forming stretchable conductive pattern, method of producing the stretchable conductive pattern using the composition, and electronic device including stretchable conductive electrode |
DE102011083419A1 (de) * | 2011-09-26 | 2013-03-28 | Siemens Aktiengesellschaft | Elektronische Baugruppe, Leiterplatte und Verfahren |
US8816717B2 (en) * | 2012-10-17 | 2014-08-26 | International Business Machines Corporation | Reactive material for integrated circuit tamper detection and response |
WO2014086987A2 (en) * | 2012-12-07 | 2014-06-12 | Cryptera A/S | A security module for protecting circuit components from unauthorized access |
DE102013205729A1 (de) | 2013-03-28 | 2014-10-02 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Vorrichtung und Verfahren mit einem Träger mit Schaltungsstrukturen |
GB201311834D0 (en) * | 2013-07-02 | 2013-08-14 | Qinetiq Ltd | Electronic hardware assembly |
CN103985674B (zh) * | 2014-06-03 | 2017-02-15 | 山东华芯半导体有限公司 | 一种安全芯片防攻击结构及防攻击的方法 |
US10540907B2 (en) | 2014-07-31 | 2020-01-21 | Intelligent Technologies International, Inc. | Biometric identification headpiece system for test taking |
US10410535B2 (en) | 2014-08-22 | 2019-09-10 | Intelligent Technologies International, Inc. | Secure testing device |
CN106662746B (zh) * | 2014-08-22 | 2020-10-23 | 国际智能技术公司 | 安全考试设备、系统和方法 |
CN104318187B (zh) * | 2014-10-17 | 2017-11-07 | 深圳市新国都技术股份有限公司 | 基于电容检测的智能终端交互信息的保护方法和系统 |
US20160174388A1 (en) | 2014-12-15 | 2016-06-16 | International Business Machines Corporation | Printed circuit board security using embedded photodetector circuit |
SG11201705664RA (en) * | 2015-01-09 | 2017-08-30 | Stanford Res Inst Int | Unclonable rfid chip and method |
CN105891651B (zh) * | 2015-01-16 | 2019-12-10 | 恩智浦美国有限公司 | 低功率开路检测系统 |
US10007811B2 (en) | 2015-02-25 | 2018-06-26 | Private Machines Inc. | Anti-tamper system |
FR3041454B1 (fr) * | 2015-09-22 | 2018-03-16 | Thales | Dispositif de protection d'un circuit electronique avec detection d'un changement de reactance electrique |
US9911012B2 (en) | 2015-09-25 | 2018-03-06 | International Business Machines Corporation | Overlapping, discrete tamper-respondent sensors |
US10080290B2 (en) * | 2015-11-17 | 2018-09-18 | Intel Corporation | Stretchable embedded electronic package |
US9887847B2 (en) * | 2016-02-03 | 2018-02-06 | International Business Machines Corporation | Secure crypto module including conductor on glass security layer |
TWI769995B (zh) | 2016-06-24 | 2022-07-11 | 日商半導體能源研究所股份有限公司 | 顯示裝置、電子裝置 |
IT201600072154A1 (it) * | 2016-07-11 | 2018-01-11 | Ibm | Dispositivi elettronici con circuiti di sicurezza individuali |
US10251260B1 (en) * | 2016-08-29 | 2019-04-02 | Square, Inc. | Circuit board to hold connector pieces for tamper detection circuit |
US10192076B1 (en) | 2016-08-29 | 2019-01-29 | Square, Inc. | Security housing with recesses for tamper localization |
US10321589B2 (en) * | 2016-09-19 | 2019-06-11 | International Business Machines Corporation | Tamper-respondent assembly with sensor connection adapter |
US10299372B2 (en) | 2016-09-26 | 2019-05-21 | International Business Machines Corporation | Vented tamper-respondent assemblies |
US10595400B1 (en) | 2016-09-30 | 2020-03-17 | Square, Inc. | Tamper detection system |
US10497650B2 (en) | 2017-04-13 | 2019-12-03 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
US10504096B1 (en) | 2017-04-28 | 2019-12-10 | Square, Inc. | Tamper detection using ITO touch screen traces |
US10306753B1 (en) | 2018-02-22 | 2019-05-28 | International Business Machines Corporation | Enclosure-to-board interface with tamper-detect circuit(s) |
EP3550466B1 (en) * | 2018-04-06 | 2023-08-02 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Puf-film and method for producing the same |
EP3550623B1 (en) | 2018-04-06 | 2020-07-29 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Puf-film and method for producing the same |
EP3550475A1 (en) | 2018-04-06 | 2019-10-09 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Puf-film and method for producing the same |
US10770410B2 (en) * | 2018-08-03 | 2020-09-08 | Arm Limited | Circuit alteration detection in integrated circuits |
US11893146B2 (en) * | 2020-03-04 | 2024-02-06 | Arm Limited | Tamper detection techniques |
US11910576B2 (en) | 2020-09-25 | 2024-02-20 | Nvidia Corporation | Heat recovery for datacenter cooling systems |
CN112234974B (zh) * | 2020-11-24 | 2023-06-13 | 西安恩狄集成电路有限公司 | 一种防破解电路 |
DE102020133099A1 (de) * | 2020-12-11 | 2022-06-15 | Zf Cv Systems Global Gmbh | Leiterplatte für elektronische Schaltungen |
US20220352099A1 (en) * | 2021-05-03 | 2022-11-03 | Nvidia Corporation | Integrated circuit physical security device |
US11882645B2 (en) * | 2021-10-22 | 2024-01-23 | International Business Machines Corporation | Multi chip hardware security module |
US20230134349A1 (en) * | 2021-10-29 | 2023-05-04 | International Business Machines Corporation | Hardware protection module |
Family Cites Families (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4023156A (en) * | 1975-01-30 | 1977-05-10 | American District Telegraph Company | Alarm system for detecting disturbance of a solid medium |
DE2646160C2 (de) * | 1975-12-08 | 1983-12-22 | Cerberus AG, 8708 Männedorf, Zürich | Verfahren und Vorrichtung zur Überwachung schalleitender Medien |
EP0035323A1 (en) | 1980-03-01 | 1981-09-09 | Sangamo Weston Limited | Electricity meters |
CA1169939A (en) * | 1981-04-16 | 1984-06-26 | Robert K. Harman | Intrusion detection system |
US4538527A (en) * | 1981-10-09 | 1985-09-03 | Pilkington P.E. Limited | Security system |
IL78728A (en) * | 1986-05-08 | 1990-07-12 | Magal Security Systems Ltd | Security fence |
US5117457A (en) * | 1986-11-05 | 1992-05-26 | International Business Machines Corp. | Tamper resistant packaging for information protection in electronic circuitry |
FR2615987B1 (fr) * | 1987-05-27 | 1994-04-01 | Axytel | Dispositif de controle de l'integrite d'une paroi quelconque, metallique ou non, destine a declencher automatiquement une intervention en cas d'agression commise a l'encontre de cette paroi |
US5185717A (en) * | 1988-08-05 | 1993-02-09 | Ryoichi Mori | Tamper resistant module having logical elements arranged in multiple layers on the outer surface of a substrate to protect stored information |
US4933898A (en) * | 1989-01-12 | 1990-06-12 | General Instrument Corporation | Secure integrated circuit chip with conductive shield |
JP2960560B2 (ja) * | 1991-02-28 | 1999-10-06 | 株式会社日立製作所 | 超小型電子機器 |
GB9115972D0 (en) * | 1991-07-24 | 1991-09-11 | Gore W L & Ass Uk | Improvements in security enclosures |
US5506566A (en) * | 1993-05-06 | 1996-04-09 | Northern Telecom Limited | Tamper detectable electronic security package |
US5369299A (en) * | 1993-07-22 | 1994-11-29 | National Semiconductor Corporation | Tamper resistant integrated circuit structure |
US5466634A (en) * | 1994-12-20 | 1995-11-14 | International Business Machines Corporation | Electronic modules with interconnected surface metallization layers and fabrication methods therefore |
GB9601899D0 (en) * | 1996-01-31 | 1996-04-03 | Neopost Ltd | Mailing system |
US5705981A (en) * | 1996-03-15 | 1998-01-06 | Breed Automotive Technology, Inc. | Secure enclosure with continuous monitoring |
US5675319A (en) * | 1996-04-26 | 1997-10-07 | David Sarnoff Research Center, Inc. | Tamper detection device |
US5995628A (en) * | 1997-04-07 | 1999-11-30 | Motorola, Inc. | Failsafe security system and method |
US5953623A (en) * | 1997-04-10 | 1999-09-14 | International Business Machines Corporation | Ball limiting metal mask and tin enrichment of high melting point solder for low temperature interconnection |
GB9711181D0 (en) * | 1997-05-31 | 1997-07-23 | Ncr Int Inc | Electrical lead and financial terminal including the lead |
US5959845A (en) * | 1997-09-18 | 1999-09-28 | International Business Machines Corporation | Universal chip carrier connector |
US6578147B1 (en) * | 1999-01-15 | 2003-06-10 | Cisco Technology, Inc. | Parallel intrusion detection sensors with load balancing for high speed networks |
JP2000227457A (ja) | 1999-02-05 | 2000-08-15 | Rohm Co Ltd | 半導体装置 |
EP1041482A1 (de) * | 1999-03-26 | 2000-10-04 | Siemens Aktiengesellschaft | Manipulationssichere integrierte Schaltung |
US6396400B1 (en) * | 1999-07-26 | 2002-05-28 | Epstein, Iii Edwin A. | Security system and enclosure to protect data contained therein |
GB0001975D0 (en) * | 2000-01-29 | 2000-03-22 | Neopost Ltd | Packaging provided with means to check integrity thereof |
US6414884B1 (en) * | 2000-02-04 | 2002-07-02 | Lucent Technologies Inc. | Method and apparatus for securing electronic circuits |
JP3604002B2 (ja) * | 2000-06-02 | 2004-12-22 | シャープ株式会社 | 半導体装置 |
US6541701B1 (en) * | 2000-06-30 | 2003-04-01 | Cisco Technology, Inc. | Containment fence apparatus and potting method |
US6680514B1 (en) | 2000-12-20 | 2004-01-20 | International Business Machines Corporation | Contact capping local interconnect |
US6791191B2 (en) * | 2001-01-24 | 2004-09-14 | Hrl Laboratories, Llc | Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations |
JP2002314031A (ja) | 2001-04-13 | 2002-10-25 | Fujitsu Ltd | マルチチップモジュール |
US7183657B2 (en) * | 2004-09-23 | 2007-02-27 | Texas Instruments Incorporated | Semiconductor device having resin anti-bleed feature |
US7281667B2 (en) * | 2005-04-14 | 2007-10-16 | International Business Machines Corporation | Method and structure for implementing secure multichip modules for encryption applications |
-
2005
- 2005-04-14 US US10/907,761 patent/US7281667B2/en not_active Expired - Fee Related
-
2006
- 2006-03-27 CN CNB2006100651987A patent/CN100501992C/zh active Active
-
2007
- 2007-06-26 US US11/768,312 patent/US7472836B2/en not_active Expired - Fee Related
-
2009
- 2009-01-05 US US12/348,364 patent/US7806341B2/en not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102474977A (zh) * | 2009-07-07 | 2012-05-23 | 国际商业机器公司 | 保护密钥和代码的多层安全结构及其方法 |
US8938627B2 (en) | 2009-07-07 | 2015-01-20 | International Business Machines Corporation | Multilayer securing structure and method thereof for the protection of cryptographic keys and code |
CN102474977B (zh) * | 2009-07-07 | 2015-05-27 | 国际商业机器公司 | 保护密钥和代码的多层安全结构及其方法 |
Also Published As
Publication number | Publication date |
---|---|
CN1855474A (zh) | 2006-11-01 |
US7806341B2 (en) | 2010-10-05 |
US7472836B2 (en) | 2009-01-06 |
US20060231633A1 (en) | 2006-10-19 |
US7281667B2 (en) | 2007-10-16 |
US20080000988A1 (en) | 2008-01-03 |
US20090145973A1 (en) | 2009-06-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100501992C (zh) | 用于针对加密应用实现安全多芯片模块的方法和结构 | |
US7180008B2 (en) | Tamper barrier for electronic device | |
US7791898B2 (en) | Security apparatus | |
US7768005B2 (en) | Physically highly secure multi-chip assembly | |
CN105938818A (zh) | 用于具有传热元件的电子封装体的方法和系统 | |
US9003559B2 (en) | Continuity check monitoring for microchip exploitation detection | |
US10181430B2 (en) | Tamper resistant electronic hardware assembly with a non-functional die used as a protective layer | |
EP3295379B1 (en) | Integrated circuit chip protection against physical and/or electrical alterations | |
WO2003019467A1 (en) | A pin pad | |
US20080001307A1 (en) | Method, system, and apparatus for a secure bus on a printed circuit board | |
KR20080033418A (ko) | 데이터 보호를 위한 보안 방법 | |
CN115989495A (zh) | 针对恶意攻击具有保护功能的集成电路器件 | |
JP2022099881A (ja) | 半導体装置 | |
RU125772U1 (ru) | 2,5d микросхема с системой защиты от исследования | |
IE20010797A1 (en) | A PIN pad |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |