CN100498619C - Double locomotive data interchange module based on bus low pressure differential signal transmission - Google Patents
Double locomotive data interchange module based on bus low pressure differential signal transmission Download PDFInfo
- Publication number
- CN100498619C CN100498619C CNB2007101325852A CN200710132585A CN100498619C CN 100498619 C CN100498619 C CN 100498619C CN B2007101325852 A CNB2007101325852 A CN B2007101325852A CN 200710132585 A CN200710132585 A CN 200710132585A CN 100498619 C CN100498619 C CN 100498619C
- Authority
- CN
- China
- Prior art keywords
- control circuit
- gate array
- programmable gate
- blvds
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Logic Circuits (AREA)
Abstract
The invention relates to a dual-computer data exchange module based on bus low voltage difference signal transmission, which is mainly used to complete data exchange function between a master and a slave under a redundant system configuration of a communication management unit to ensure the real-time and reliable data transmission. The module comprises a FPGA control circuit (1), a CPLD control circuit (2), a high-speed dual-port RAM memory control circuit (3), a BLVDS interface resistance matching circuit (4) and a power supply circuit (5); wherein, the FPGA control circuit and the CPLD control circuit are respectively connected with the RAM memory control circuit and a backplane bus terminal through data, address and a control signal line; the FPGA control circuit is connected with the BLVDS interface resistance matching circuit through a FPGA component difference signal pin; the BLVDS interface resistance matching circuit outputs the signal through a BLVDS output terminal (6).
Description
Technical field
The present invention is the part of communications management unit device in ECS of power plant (electric control system) or the comprehensive automation system of transformer substation, be mainly used in the function of finishing exchanges data between following main frame of communications management unit redundant system configuration and slave, guarantee real time of data transmission and reliability, belong to the technical field that power plant electrical control system or comprehensive automation system of transformer substation are made.
Background technology
For guaranteeing the reliability and the security of communication system, generally require communications management unit to be configured to double-machine redundancy system in ECS of power plant (electric control system) or the comprehensive automation system of transformer substation, one is a main frame, and another is a slave.When main frame broke down, slave Upgraded Now and is main frame, bears communication task, and main frame is reduced to slave.In order to realize high speed, the reliable seamless transmission of master/slave machine data exchange, consider to use the bus low pressure differential signal transmission mode to realize the hardware interface design that two-shipper switches.
Low Voltage Differential Signal LVDS (Low Voltage Differential Signal) is the physical layer interface standard that is used for high speed data transfer by the ANSI/TIA/EIA-644-1995 definition.It has the characteristic of hypervelocity (1.4Gb/s), low-power consumption and low electromagnetic, is the priority scheme of realizing the high-speed communication of kilomegabit level on the copper medium; Can be used for server, can pile and build hub, wireless base station, ATM switch and high resolving power demonstration or the like, also can be used for design of communication system.
Bus low pressure differential signal BLVDS (Bus-LVDS) is the expansion of LVDS technology in the multi-point field, has bus arbitration function, bigger drive current (10mA) and better impedance matching design.The main application of Bus-LVDS solution is to carry out intrasystem data transmission.If the agreement between the employing system is carried out intrasystem data transmission, the cost of software/hardware aspect is too expensive, so simplicity of design and lower-cost BLVDS link just become the abnormal type of very attractive and select.The BLVDS solution also can be guaranteed can carry out data transmission between circuit board, module, frame, rack or cabinet and the cabinet except can supporting the data transmission in the circuit board, and its data transmission media comprises copper cable or printed circuit board (pcb) circuit.
This module use bus B LVDS hardware interface mode realizes the data transmission between master/slave machine, guarantees high speed, reliability and the stability of data transmission on hardware, can satisfy the demand of practical application.
Summary of the invention
Technical matters: fundamental purpose of the present invention provides a kind of double locomotive data interchange module based on the bus low pressure differential signal transmission, adopt bus low pressure differential signal BLVDS to realize the exchanges data between the master/slave machine in the configuration of communication processor redundant system, the extensive on-site programmable gate array FPGA device that has a BLVDS interface by employing carries out core bus and extends out, in addition the high-speed programmable logic device (CPLD) is realized relevant steering logic, be equipped with high-capacity and high-speed two-port RAM storer and carry out exchanges data, thereby realized high speed between the master/slave machine of communication processor, reliable data transmission.
Technical scheme: above-mentioned purpose of the present invention is achieved in that this module comprises on-site programmable gate array FPGA control circuit, complex programmable logic device (CPLD) control circuit, high speed two-port RAM memorizer control circuit, BLVDS interface resistors match circuit and power-supply circuit; Wherein, on-site programmable gate array FPGA control circuit, complex programmable logic device (CPLD) control circuit are connected with high speed two-port RAM memorizer control circuit and core bus terminal by data, address, control signal wire respectively, the on-site programmable gate array FPGA control circuit is connected with BLVDS interface resistors match circuit by the differential signal pin of FPGA device, and BLVDS interface resistors match circuit is by BLVDS lead-out terminal output signal.
Above-mentioned on-site programmable gate array FPGA control circuit mainly is made up of on-site programmable gate array FPGA device, serial FLASH memory, JTAG (Joint Test Action Group, a kind of international standard test protocol) interface circuit and corresponding resistance thereof, capacitor element; The control of serial FLASH memory, data signal line link to each other with the on-site programmable gate array FPGA device, and the BLVDS signal pins of on-site programmable gate array FPGA device exports BLVDS interface resistors match circuit to; The on-site programmable gate array FPGA device also links to each other with data, address, the control signal wire of core bus terminal; High speed two-port RAM storer in the high speed two-port RAM memorizer control circuit wherein data, address, the control signal wire of a port side links to each other with the on-site programmable gate array FPGA device, and the jtag interface signal wire is connected with the JTAG debugging pin of on-site programmable gate array FPGA device.
Above-mentioned complex programmable logic device (CPLD) control circuit mainly is made up of complex programmable logic device (CPLD) and jtag interface circuit; Complex programmable logic device (CPLD) links to each other with data, address, the control signal wire of core bus terminal, also link to each other with data, address, the control signal wire of the other end oral-lateral of high speed two-port RAM storer simultaneously, the JTAG signal is connected with the JTAG debugging pin of complex programmable logic device (CPLD).
Above-mentioned high speed two-port RAM memorizer control circuit mainly is made up of high speed two-port RAM storer and resistance, capacitor element accordingly thereof; The data of a two-port RAM storer port side wherein, address, control signal wire link to each other with the on-site programmable gate array FPGA device, and the data of other end oral-lateral, address, control signal wire link to each other with complex programmable logic device (CPLD).
Above-mentioned BLVDS interface resistors match circuit mainly is made up of series matching resistor and build-out resistor in parallel, one end of resistance in series links to each other with the output of the BLVDS signal of on-site programmable gate array FPGA device, the other end links to each other with the BLVDS lead-out terminal of module, and parallel resistance is parallel on the differential signal line on the lead-out terminal.
Above-mentioned power-supplying circuit is realized by three low pressure difference linear voltage regulators, low pressure difference linear voltage regulator be input as the voltage that System Backplane provides, the one voltage stabilizer is output as the supply voltage of IO supply voltage, high speed two-port RAM memory power and the serial FLASH memory of high-speed programmable logic device (CPLD); Another voltage stabilizer is output as the IO supply voltage of on-site programmable gate array FPGA device; A voltage stabilizer is the kernel supply voltage of FPGA again.
Principle of work of the present invention is: when the communications management unit device is configured to double-machine redundancy system when work, thereby realize the exchanges data of two-shipper by the control access right that double locomotive data interchange module is set.Its concrete control method is:
Data exchange module in the host microprocessors CPU visit main frame, by corresponding control logic is set, make the high speed two-port RAM memory read/write in the main frame effective, promptly host microprocessors CPU can visit the high speed two-port RAM storer of double locomotive data interchange module in the main frame.
The microprocessor CPU of slave can directly pass through the high speed two-port RAM storer of the double locomotive data interchange module on the BLVDS bus access main frame by the steering logic of the double locomotive data interchange module in the slave is set.
By above setting, master/slave machine passes through the data transmission between the master/slave machine of the visit realization communication processor of the high speed two-port RAM storer in the main frame.
Beneficial effect: entire circuit of the present invention has following characteristics: adopt the hardware based on bus low pressure differential signal BLVDS transmission mode to connect design, guarantee high speed, the reliability of master/slave system data exchange; Adopt the on-site programmable gate array FPGA device to realize the data link of bus low pressure differential signal BLVDS, compare and adopt special-purpose BLVDS control chip can significantly reduce number of chips, reduce cost, improve the security of system reliability, have greater flexibility and backwards compatibility simultaneously.
Description of drawings
Fig. 1 is the on-site programmable gate array FPGA device control circuit schematic diagram of module of the present invention.
Fig. 2 is the complex programmable logic device (CPLD) control circuit schematic diagram of module of the present invention.
Fig. 3 is the high speed two-port RAM memorizer control circuit schematic diagram of module of the present invention.
Fig. 4 is the BLVDS interface resistors match circuit theory diagrams of module of the present invention.
Fig. 5 is the power-supply circuit schematic diagram of module of the present invention.
Fig. 6 is the schematic block circuit diagram of module of the present invention.
Fig. 7 is the exchanges data principle schematic of module of the present invention in master/slave machine configuration.
Embodiment
Below in conjunction with accompanying drawing, specific implementation of the present invention is described in further detail.
Referring to Fig. 6, the double locomotive data interchange module circuit that the present invention is based on bus low pressure differential signal BLVDS transmission mainly comprises: on-site programmable gate array FPGA control circuit 1, complex programmable logic device (CPLD) control circuit 2, high speed two-port RAM memorizer control circuit 3, BLVDS interface resistors match circuit 4 and power-supply circuit 5; Wherein, on-site programmable gate array FPGA control circuit 1, complex programmable logic device (CPLD) control circuit 2 are connected with high speed two-port RAM memorizer control circuit 3 and core bus terminal 7 by data, address, control signal wire respectively, on-site programmable gate array FPGA control circuit 1 is connected with BLVDS interface resistors match circuit 4 by the differential signal pin of FPGA device, and BLVDS interface resistors match circuit 4 is by BLVDS lead-out terminal 6 output signals.
Referring to Fig. 1, main element adopts the fpga chip U7 of the LFEC3E model of LATTICE company in the on-site programmable gate array FPGA device control circuit of the present invention, this kind of FPGA has rich in natural resources, multiple electric level interface can be provided, two kinds of level standards of BLVDS and TTL have been used in this module, U7 is by address bus SA[19..0], data bus SD[7..0] and control signal corresponding line SMEMWR, SMEMRD links to each other with core bus, simultaneously by address bus R_R_A[14..0], data bus R_R_D[7..0] and the address of control signal corresponding line and high speed two-port RAM storer U14 right side port, data, control signal wire links to each other, also by address difference sub-signal bus R_ADDRPN[19..0], data differential signals bus R_DATAPN[7..0] link to each other with the resistors match network.On-site programmable gate array FPGA device control circuit is realized the core bus of TTL fiduciary level and the interface between BLVDS fiduciary level transfer bus on the one hand, has also realized the access rights control function of microprocessor to high speed two-port RAM storer simultaneously.The U6 of the serial FLASH memory in the circuit is the SST25VF020 chip, total 2Mbit storage unit.It links to each other with the on-site programmable gate array FPGA device, realizes the procedure stores function, and when powering on, loading procedure is given on-site programmable gate array FPGA device U7, and U7 is normally moved.JP4 in the circuit is that JTAG loads terminal, links to each other with the JTAG debugging interface of on-site programmable gate array FPGA, and the program that is used for compiling in the computing machine is loaded in the serial FLASH memory.
Referring to Fig. 2, adopt the X95108 programmable logic device (PLD) U13 of Xilinx company to realize in the complex programmable logic device (CPLD) control circuit of the present invention.It introduces the address bus SA[19..0 of core bus], data bus SD[7..0] and control signal corresponding line SMEMWR, SMEMRD, also link to each other simultaneously with on-site programmable gate array FPGA device U7.Core bus is the Transistor-Transistor Logic level signal system, complex programmable logic device (CPLD) is realized the level conversion function, simultaneously U13 is also by data bus XDATA[7..0], address bus ADDR[14..0] and the control signal corresponding line link to each other with address, data, the control signal wire of another port, high speed two-port RAM storer U14 left side, realized the access control of control that the CPU access control of communication processor is weighed and core bus to high speed two-port RAM storer.
Referring to Fig. 3, U14 adopts high speed, the high capacity two-port RAM memory I DT70V06 of IDT company in the high speed two-port RAM memorizer control circuit of the present invention, it has the ram space of 16k * 8, access time is 25ns, have two independently data, address and control signal ports, have the hardware port arbitration circuit in the sheet, read and write in an orderly manner by two ports to guarantee any unit in the storer, contention takes place in read-write to data to avoid dual-CPU system.The address of one port, data, control signal wire link to each other with complex programmable logic device (CPLD) U13 among the present invention, address, another port, data, control signal wire link to each other with on-site programmable gate array FPGA device U7, realize the high speed exchange of two-shipper data.
Referring to Fig. 4, in the BLVDS interface resistors match circuit of the present invention the BLVDS output signal has been carried out resistors match, respectively differential signal has been sealed in 80 ohm serial resistor, between the differential signal with 75 Ohmages and connect, erasure signal disturbs, the integrality of enhancing signal.
Referring to Fig. 5, power-supply circuit of the present invention has adopted 3 low pressure difference linear voltage regulators to realize, the input voltage that is input as System Backplane of low pressure difference linear voltage regulator, one U8 adopts the SPX1117M3-3.3 low pressure difference linear voltage regulator, is output as the supply voltage 3.3V of IO supply voltage, high speed two-port RAM memory power and the serial FLASH memory of high-speed programmable logic device (CPLD); Another voltage stabilizer U9 adopts the SPX1117M3-2.5 low pressure difference linear voltage regulator, is output as the IO supply voltage 2.5V of on-site programmable gate array FPGA device; A voltage stabilizer U10 adopts MCP1700-120 again, is mainly the kernel supply voltage 1.2V of FPGA.
Referring to Fig. 7, the double locomotive data interchange module circuit that the present invention is based on the bus low pressure differential signal transmission is mainly realized by following control method.In the application system of reality, disposed the dual-computer redundancy communication processor, the right side is host A and the inner double locomotive data interchange module that has thereof, the left side is slave B and inner double locomotive data interchange module thereof.The microprocessor CPU of right side host A can conduct interviews to the double locomotive data interchange module in its cabinet by core bus A7, the microprocessor CPU of host A is controlled the A2 of high-speed programmable logic device (CPLD) via core bus A7, it is set to high speed two-port RAM storer A3 access control power, the microprocessor CPU of host A can be visited the port of two-port RAM storer A3 like this; And the microprocessor CPU of slave B can conduct interviews to the double locomotive data interchange module of its cabinet inside by core bus B7, the microprocessor CPU of slave B is controlled on-site programmable gate array FPGA device B1 via core bus B7, forbid that it weighs high speed two-port RAM storer B3 access control, dispose the signal output of the BLVDS of on-site programmable gate array FPGA device B1 simultaneously, like this microprocessor CPU of slave B via core bus B7 to on-site programmable gate array FPGA device B1, pass through BLVDS interface resistors match circuit again to BLVDS Interface Terminal B6, again through the BLVDS Interface Terminal A6 of the stube cable between the master/slave machine to host A, via BLVDS interface resistors match circuit A4, arrive on-site programmable gate array FPGA device A1 again, control the another one port that to visit high speed two-port RAM storer A3 through the access control power of on-site programmable gate array FPGA device A1 again.Realized that by signal link described above high speed, real time data between the master/slave machine exchange like this.
Should illustrate that at last enforcement of the present invention only is used to technical scheme is described and is unrestricted.More than the present invention is had been described in detail, those of ordinary skill also is appreciated that and it still can make amendment or be equal to replacement the technical scheme that disclosed of invention.And all do not break away from the modification and the replacement of the spirit and scope of technical solution of the present invention, and it all should be encompassed in the middle of the claim scope of the present invention.
Claims (6)
1. the double locomotive data interchange module based on the bus low pressure differential signal transmission is characterized in that this module comprises: on-site programmable gate array FPGA control circuit (1), complex programmable logic device (CPLD) control circuit (2), high speed two-port RAM memorizer control circuit (3), BLVDS interface resistors match circuit (4) and power-supply circuit (5); Wherein, on-site programmable gate array FPGA control circuit (1), complex programmable logic device (CPLD) control circuit (2) are connected with high speed two-port RAM memorizer control circuit (3) and core bus terminal (7) by data, address, control signal wire respectively, on-site programmable gate array FPGA control circuit (1) is connected with BLVDS interface resistors match circuit (4) by the differential signal pin of FPGA device, and BLVDS interface resistors match circuit (4) is by BLVDS lead-out terminal (6) output signal.
2. a kind of double locomotive data interchange module based on the bus low pressure differential signal transmission according to claim 1 is characterized in that: on-site programmable gate array FPGA control circuit (1) mainly is made up of on-site programmable gate array FPGA device, serial FLASH memory, jtag interface circuit and corresponding resistance thereof, capacitor element; The control of serial FLASH memory, data signal line link to each other with the on-site programmable gate array FPGA device, and the BLVDS signal pins of on-site programmable gate array FPGA device exports BLVDS interface resistors match circuit (4) to; The on-site programmable gate array FPGA device also links to each other with data, address, the control signal wire of core bus terminal (7); High speed two-port RAM storer in the high speed two-port RAM memorizer control circuit (3) wherein data, address, the control signal wire of first port side links to each other with the on-site programmable gate array FPGA device, and the jtag interface signal is connected with the JTAG debugging pin of on-site programmable gate array FPGA device.
3. a kind of double locomotive data interchange module according to claim 1 based on the bus low pressure differential signal transmission, it is characterized in that: complex programmable logic device (CPLD) control circuit (2) mainly is made up of complex programmable logic device (CPLD) and jtag interface circuit; Complex programmable logic device (CPLD) links to each other with data, address, the control signal wire of core bus terminal (7), also link to each other with data, address, the control signal wire of second port side in addition of high speed two-port RAM storer simultaneously, the JTAG signal is connected with the JTAG debugging pin of complex programmable logic device (CPLD).
4. a kind of double locomotive data interchange module based on the bus low pressure differential signal transmission according to claim 1 is characterized in that: high speed two-port RAM memorizer control circuit (3) mainly is made up of high speed two-port RAM storer and resistance, capacitor element accordingly thereof; The data of a two-port RAM storer port side wherein, address, control signal wire link to each other with the on-site programmable gate array FPGA device, and the data of other end oral-lateral, address, control signal wire link to each other with complex programmable logic device (CPLD).
5. a kind of double locomotive data interchange module according to claim 1 based on the bus low pressure differential signal transmission, it is characterized in that: BLVDS interface resistors match circuit (4) mainly is made up of series matching resistor and build-out resistor in parallel, one end of series matching resistor links to each other with the output of the BLVDS signal of on-site programmable gate array FPGA device, the other end links to each other with the BLVDS lead-out terminal of module, and build-out resistor in parallel is parallel on the differential signal line on the lead-out terminal.
6. a kind of double locomotive data interchange module according to claim 1 based on the bus low pressure differential signal transmission, it is characterized in that: power-supply circuit (5) is realized by three low pressure difference linear voltage regulators, low pressure difference linear voltage regulator be input as the voltage that System Backplane provides, the one voltage stabilizer is output as the supply voltage of IO supply voltage, high speed two-port RAM memory power and the serial FLASH memory of high-speed programmable logic device (CPLD); Another voltage stabilizer is output as the IO supply voltage of on-site programmable gate array FPGA device; A voltage stabilizer is the kernel supply voltage of FPGA again.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101325852A CN100498619C (en) | 2007-09-21 | 2007-09-21 | Double locomotive data interchange module based on bus low pressure differential signal transmission |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101325852A CN100498619C (en) | 2007-09-21 | 2007-09-21 | Double locomotive data interchange module based on bus low pressure differential signal transmission |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101158868A CN101158868A (en) | 2008-04-09 |
| CN100498619C true CN100498619C (en) | 2009-06-10 |
Family
ID=39306988
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007101325852A Expired - Fee Related CN100498619C (en) | 2007-09-21 | 2007-09-21 | Double locomotive data interchange module based on bus low pressure differential signal transmission |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100498619C (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103186A (en) * | 2009-12-18 | 2011-06-22 | 上海贝尔股份有限公司 | Debug method of FPGA and equipment thereof |
| CN104678757A (en) * | 2013-12-02 | 2015-06-03 | 景德镇昌航航空高新技术有限责任公司 | Helicopter engine dual-redundancy fuel oil regulation controller |
| CN105827554B (en) * | 2016-03-10 | 2019-02-15 | 重庆大学 | A kind of optimization method and device of FlexRay bus node build-out resistor |
| CN108228502B (en) * | 2016-12-14 | 2021-03-26 | 中国航空工业集团公司西安航空计算技术研究所 | Back plate meeting electrical characteristics of ARINC659 bus |
| CN107368444A (en) * | 2017-08-02 | 2017-11-21 | 杭州迪普科技股份有限公司 | Electronic equipment |
| US11032905B2 (en) * | 2018-01-19 | 2021-06-08 | Ge Aviation Systems Llc | Unmanned vehicle control systems |
| CN109739697B (en) * | 2018-12-13 | 2022-10-14 | 北京计算机技术及应用研究所 | High-speed data exchange-based strong real-time dual-computer synchronization fault-tolerant system |
| CN110096010A (en) * | 2019-05-14 | 2019-08-06 | 广州致远电子有限公司 | Core board and equipment |
| CN110519141B (en) * | 2019-08-22 | 2024-08-02 | 深圳龙电华鑫控股集团股份有限公司 | Master-slave communication circuit and communication device |
| CN113595843A (en) * | 2021-07-28 | 2021-11-02 | 浙江中控技术股份有限公司 | Control system based on BLVDS signal relay device |
| CN114089918A (en) * | 2021-11-24 | 2022-02-25 | 浙江中控技术股份有限公司 | Bidirectional access device |
| CN114443517B (en) * | 2021-12-30 | 2023-05-26 | 苏州浪潮智能科技有限公司 | Interactive programmable logic device interconnection server system |
| CN115766622A (en) * | 2022-09-28 | 2023-03-07 | 苏州浪潮智能科技有限公司 | Switch power-on control circuit, method and system |
-
2007
- 2007-09-21 CN CNB2007101325852A patent/CN100498619C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101158868A (en) | 2008-04-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100498619C (en) | Double locomotive data interchange module based on bus low pressure differential signal transmission | |
| CN204009877U (en) | A kind of integrated data collection and control device | |
| CN101000591A (en) | Double-machine redundancy system based on embedded CPU | |
| CN205139890U (en) | Two memory system that live of two accuses based on X86 framework | |
| CN101944002B (en) | Gain adjustable multifunctional data acquisition card | |
| CN101989763A (en) | Power supply backup system and device and communication equipment | |
| CN106897243A (en) | Modified server and storage device | |
| CN102880235B (en) | Single-board computer based on loongson 2F central processing unit (CPU) as well as reset management and using method of single-board computer | |
| CN206807466U (en) | A kind of high availability redundant ciphering terminal based on PCIE non-transparent bridges | |
| CN105259853A (en) | A redundant on-site bus I/O control device | |
| CN110096291A (en) | Power management chip upgrades circuit, method and the network equipment | |
| CN201084008Y (en) | Double machine data interchange module based on bus low-voltage differential signal transmission | |
| CN203858630U (en) | Pcie interface switching device | |
| CN202171888U (en) | One-chip microcomputer and CPLD collaborative design experimental system | |
| CN201570908U (en) | Monitoring and protecting device of DS (data-sharing) centralized-digitized transformer station | |
| CN204480237U (en) | A kind of connector, universal serial bus device and intelligent terminal | |
| CN207008492U (en) | A kind of modular server and bottom plate | |
| CN115098016B (en) | Redundant computer high-precision AD acquisition equipment based on LRM | |
| CN206479922U (en) | Highly dense server hard disk back plane | |
| CN104967574A (en) | Soft switch device | |
| CN205608716U (en) | Multiunit optical module communication interface switching circuit | |
| CN103530256A (en) | CPCIe and PCI protocol data processing device and method | |
| CN104915313B (en) | A kind of FMC boards that level conversion is realized using FPGA | |
| CN202413793U (en) | Machine case of traction control unit of electric locomotive and electric locomotive | |
| CN207611382U (en) | Dual-machine communication redundant apparatus based on cpci bus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090610 Termination date: 20170921 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |