CN205139890U - Two memory system that live of two accuses based on X86 framework - Google Patents
Two memory system that live of two accuses based on X86 framework Download PDFInfo
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- CN205139890U CN205139890U CN201520958886.0U CN201520958886U CN205139890U CN 205139890 U CN205139890 U CN 205139890U CN 201520958886 U CN201520958886 U CN 201520958886U CN 205139890 U CN205139890 U CN 205139890U
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Abstract
The utility model discloses a two memory system that live of two accuses based on X86 framework, memory system's store controller is two, adopts active - active mode, and two controllers all are in the state of activation, according to the load pressure between the controller, carries out load balancing automatically, and ability parallel processing comes from the IO request of server. The utility model discloses a load balancing according to the load pressure between the controller, is carried out automatically to two controller designs of living, in case trouble or off -line that certain controller appears, its work will in time be taken over to another controller, and does not influence the work of oneself. Adopt two controller designs of living, this mode still has a great deal of advantages such as balanced portfolio, make full use of resource and lift system performance when guaranteeing system's high reliability through each other for redundant backup.
Description
Technical field
The utility model relates to notebook technical field of memory, is specifically related to a kind of dual control dual-active storage system based on X86-based.
Background technology
Storage system is the foundation stone of whole IT system, is that IT technology is rely and existed and play the basic platform of usefulness.The hardware component such as disk chassis, two memory controllers, array backboard, some power supplys, fans that general storage system is placed by a large amount of disk of one or more confession forms.
Wherein main parts are exactly memory controller and disk chassis.Controller, by its built-in control software design, realizes the management of whole storage array.General storage array is to the interface of main frame just on memory controller, and general every controller has a host interface at least, and some controller provides more host interface; These host interface can directly or be connected with main frame by optical fiber switch, and various management interface (serial ports, Ethernet interface etc.) is also integrated on the controller in addition.And generally why adopt two controllers, mainly consider from the angle of high availability, raising performance and load balancing.A lot of storage array by the switching between these two controllers, can prevent the Single Point of Faliure of controller, connection cable, the network equipment (as fibre channel media and hub), main frame HBA.Some storage array then can realize multichannel data access and interchannel load balancing by main frame or array software.
Utility model content
The technical problems to be solved in the utility model is: the utility model provides a kind of dual control dual-active storage system based on X86-based.
The technical scheme that the utility model adopts is:
A kind of dual control dual-active storage system based on X86-based, the memory controller of described storage system is two, adopt Active – Active mode of operation, two controllers are all in state of activation, according to load pressure between controller, automatically carry out load balancing, can parallel processing ask from the I/O of server, once the fault of certain controller appearance or off-line, another controller will take over its work in time, and not affect the work of oneself.Adopt dual-active Controller gain variations, this mode of operation, by while redundancy backup guarantees system high reliability each other, also has equalizing traffic, makes full use of the plurality of advantages such as resource and elevator system performance.
The control end of described storage system comprises 2 pieces and stores control panel, and controller adopts X86 platform, and adopt the connect chip with NT function between controller, be connected through backboard by the NT passage of PCIex8, NT passage realizes buffer memory image feature;
Each controller is divided into front-end and back-end two parts, and front-end interface comprises 10,000,000,000 network interfaces, supervising the network interface and other expansion interfaces etc.; Rear end adopts the PCIex8 of processor to be converted to 8 road SAS buses through SASController, and 4 tunnels are used for realizing the redundancy to disk read-write path, rear end, and other 4 tunnels realize the expansion to disk number through SASExpander;
Store end to be made up of 6 pieces of storage support plates, every block support plate carries 4 pieces of 2.5 cun of 256G is with the solid-state electronic dish destroying functions.
The storage control end of described storage system adopts X86-based flush bonding processor Intel Duo i7, supports twin-channel DDR3 internal memory;
The chipset of described storage control end adopts QM77, and provide DMI bus to interconnect with CPU, transfer rate reaches 5.0GT/S, is used for uploading the data needing computing and the result receiving computing;
Described storage control end provides the operation result of video processor in FDI bus receiving processor, exports after converting standard video format to;
Described storage control end provides two PCIex4 passages, is used for spread F C interface;
Described storage control end provides a road SMBUS interface, BMC managing chip obtains the real time temperature information of CPU and bridge sheet in QM77 platform also by SMBUS bus, obtain Vital Voltage information by W83795, the information of acquisition is given administrative unit by network management interface by BMC;
PCIe × 8 bus that described storage control end utilizes flush bonding processor to provide is converted to SAS bus through SASController, expands to 12 road SAS buses, be connected to memory module through backboard by SASExpander.
The storage end of described storage system comprises 6 pieces and stores support plate, and every block support plate carries 4 pieces of 2.5 cun of 256G can destroy electric board, adopts the BMC of storage control module to realize logic and destroys and physical destroying function.
The power acquisition redundant power of described storage system, wherein during a road power failure, another road power supply can continue the steady operation of guarantee system;
Wherein, mainboard by two DC Power supplies of outside, after redundancy/current-sharing and voltage transitions, for mainboard provides fundamental voltage;
Motherboard power supply intake section mainly comprises redundancy/current-sharing and voltage transitions two large divisions;
Redundancy/current-sharing part, realizes the N+1 redundancy of parallel current-sharing by LTC4350 chip and MOSFET; It is balanced that flow equalizing function can make the supply current of two power supplys realize, and when one of them power failure, another power supply can be taken over rapidly and carry out independently-powered, improves the reliability of system.
The primary clustering such as controller, power supply, fan, battery, host interface plate of described storage system is modular assembly, supports the hot plug of independent assembly and online replacing.This mode of operation, by while redundancy backup guarantees system high reliability each other, also has equalizing traffic, makes full use of the plurality of advantages such as resource and elevator system performance.
Described storage system adopts buffer memory mirror image mechanism, can brush retention disk after a power failure under data cached.
The beneficial effects of the utility model are:
The utility model adopts dual-active Controller gain variations, according to load pressure between controller, automatically carries out load balancing, once the fault of certain controller appearance or off-line, another controller will take over its work in time, and not affect the work of oneself.Adopt dual-active Controller gain variations, this mode of operation, by while redundancy backup guarantees system high reliability each other, also has equalizing traffic, makes full use of the plurality of advantages such as resource and elevator system performance.
Accompanying drawing explanation
Fig. 1 is dual control storage hardware paralell composition;
Fig. 2 is the control end block diagram of storage system;
Fig. 3 is the storage end block diagram of storage system;
Fig. 4 is redundant power block diagram.
Embodiment
With reference to the accompanying drawings, by embodiment, the utility model is further illustrated:
Embodiment 1:
A kind of dual control dual-active storage system based on X86-based, the memory controller of described storage system is two, adopt Active – Active mode of operation, two controllers are all in state of activation, according to load pressure between controller, automatically carry out load balancing, can parallel processing ask from the I/O of server, once the fault of certain controller appearance or off-line, another controller will take over its work in time, and not affect the work of oneself.Adopt dual-active Controller gain variations, this mode of operation, by while redundancy backup guarantees system high reliability each other, also has equalizing traffic, makes full use of the plurality of advantages such as resource and elevator system performance.
Embodiment 2:
As shown in Figure 1, on the basis of embodiment 1, the control end of storage system described in the present embodiment comprises 2 pieces and stores control panel, controller adopts X86 platform, the connect chip with NT function is adopted between controller, be connected through backboard by the NT passage of PCIex8, NT passage realizes buffer memory image feature;
Each controller is divided into front-end and back-end two parts, and front-end interface comprises 10,000,000,000 network interfaces, supervising the network interface and other expansion interfaces etc.; Rear end adopts the PCIex8 of processor to be converted to 8 road SAS buses through SASController, and 4 tunnels are used for realizing the redundancy to disk read-write path, rear end, and other 4 tunnels realize the expansion to disk number through SASExpander;
Store end to be made up of 6 pieces of storage support plates, every block support plate carries 4 pieces of 2.5 cun of 256G is with the solid-state electronic dish destroying functions.
Embodiment 3:
As shown in Figure 2, on the basis of embodiment 1 or 2, the storage control end of storage system described in the present embodiment adopts X86-based flush bonding processor Intel Duo i7, supports twin-channel DDR3 internal memory;
The chipset of described storage control end adopts QM77, and provide DMI bus to interconnect with CPU, transfer rate reaches 5.0GT/S, is used for uploading the data needing computing and the result receiving computing;
Described storage control end provides the operation result of video processor in FDI bus receiving processor, exports after converting standard video format to;
Described storage control end provides two PCIex4 passages, is used for spread F C interface;
Described storage control end provides a road SMBUS interface, BMC managing chip obtains the real time temperature information of CPU and bridge sheet in QM77 platform also by SMBUS bus, obtain Vital Voltage information by W83795, the information of acquisition is given administrative unit by network management interface by BMC;
PCIe × 8 bus that described storage control end utilizes flush bonding processor to provide is converted to SAS bus through SASController, expands to 12 road SAS buses, be connected to memory module through backboard by SASExpander.
Embodiment 4:
As shown in Figure 3, on the basis of embodiment 1 or 2, the storage end of storage system described in the present embodiment comprises 6 pieces and stores support plate, and every block support plate carries 4 pieces of 2.5 cun of 256G can destroy electric board, adopts the BMC of storage control module to realize logic and destroys and physical destroying function.
Embodiment 5:
As shown in Figure 4, on the basis of embodiment 1 or 2, the power acquisition redundant power of storage system described in the present embodiment, wherein during a road power failure, another road power supply can continue the steady operation of guarantee system.
Wherein, mainboard by two DC Power supplies of outside, after redundancy/current-sharing and voltage transitions, for mainboard provides fundamental voltage;
Motherboard power supply intake section mainly comprises redundancy/current-sharing and voltage transitions two large divisions;
Redundancy/current-sharing part, realizes the N+1 redundancy of parallel current-sharing by LTC4350 chip and MOSFET; When DC power supply 1 and DC power supply 2 are all normal, two power supplys are load supplying jointly, and it is balanced that flow equalizing function can make the supply current of two power supplys realize, when one of them power failure, another power supply can be taken over rapidly and carry out independently-powered, improves the reliability of system.
Embodiment 6:
On the basis of embodiment 1 or 2, the primary clustering such as controller, power supply, fan, battery, host interface plate of storage system described in the present embodiment is modular assembly, supports the hot plug of independent assembly and online replacing.This mode of operation, by while redundancy backup guarantees system high reliability each other, also has equalizing traffic, makes full use of the plurality of advantages such as resource and elevator system performance.
Embodiment 7:
On the basis of embodiment 1 or 2, storage system described in the present embodiment adopts buffer memory mirror image mechanism, can brush retention disk after a power failure under data cached.
Above embodiment is only for illustration of the utility model; and be not limitation of the utility model; the those of ordinary skill of relevant technical field; when not departing from spirit and scope of the present utility model; can also make a variety of changes and modification; therefore all equivalent technical schemes also belong to category of the present utility model, and scope of patent protection of the present utility model should be defined by the claims.
Claims (7)
1. the dual control dual-active storage system based on X86-based, it is characterized in that: the memory controller of described storage system is two, adopt Active – Active mode of operation, two controllers are all in state of activation, according to load pressure between controller, automatically carry out load balancing, energy parallel processing is asked from the I/O of server.
2. a kind of dual control dual-active storage system based on X86-based according to claim 1, it is characterized in that: the control end of described storage system comprises 2 pieces and stores control panel, controller adopts X86 platform, the connect chip with NT function is adopted between controller, be connected through backboard by the NT passage of PCIex8, NT passage realizes buffer memory image feature;
Each controller is divided into front-end and back-end two parts, and front-end interface comprises 10,000,000,000 network interfaces, supervising the network interface and other expansion interfaces; Rear end adopts the PCIex8 of processor to be converted to 8 road SAS buses through SASController, and 4 tunnels are used for realizing the redundancy to disk read-write path, rear end, and other 4 tunnels realize the expansion to disk number through SASExpander;
Store end to be made up of 6 pieces of storage support plates, every block support plate carries 4 pieces of 2.5 cun of 256G is with the solid-state electronic dish destroying functions.
3. a kind of dual control dual-active storage system based on X86-based according to claim 1 and 2, is characterized in that: the storage control end of described storage system adopts X86-based flush bonding processor Intel Duo i7, supports twin-channel DDR3 internal memory;
The chipset of described storage control end adopts QM77, provides DMI bus to interconnect with CPU, is used for uploading the data needing computing and the result receiving computing;
Described storage control end provides the operation result of video processor in FDI bus receiving processor, exports after converting standard video format to;
Described storage control end provides two PCIex4 passages, is used for spread F C interface;
Described storage control end provides a road SMBUS interface, BMC managing chip obtains the real time temperature information of CPU and bridge sheet in QM77 platform also by SMBUS bus, obtain Vital Voltage information by W83795, the information of acquisition is given administrative unit by network management interface by BMC;
PCIe × 8 bus that described storage control end utilizes flush bonding processor to provide is converted to SAS bus through SASController, expands to 12 road SAS buses, be connected to memory module through backboard by SASExpander.
4. a kind of dual control dual-active storage system based on X86-based according to claim 1 and 2, it is characterized in that: the storage end of described storage system comprises 6 pieces and stores support plate, every block support plate carries 4 pieces of 2.5 cun of 256G can destroy electric board, adopts the BMC of storage control module to realize logic and destroys and physical destroying function.
5. a kind of dual control dual-active storage system based on X86-based according to claim 1 and 2, it is characterized in that: the power acquisition redundant power of described storage system, wherein during a road power failure, another road power supply can continue the steady operation of guarantee system;
Wherein, mainboard by two DC Power supplies of outside, after redundancy/current-sharing and voltage transitions, for mainboard provides fundamental voltage;
Motherboard power supply intake section mainly comprises redundancy/current-sharing and voltage transitions two large divisions;
Redundancy/current-sharing part, realizes the N+1 redundancy of parallel current-sharing by LTC4350 chip and MOSFET.
6. a kind of dual control dual-active storage system based on X86-based according to claim 1 and 2, it is characterized in that: the controller of described storage system, power supply, fan, battery, host interface plate are modular assembly, support the hot plug of independent assembly and online replacing.
7. a kind of dual control dual-active storage system based on X86-based according to claim 1 and 2, is characterized in that: described storage system adopts buffer memory mirror image mechanism, can brush retention disk after a power failure under data cached.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520958886.0U CN205139890U (en) | 2015-11-27 | 2015-11-27 | Two memory system that live of two accuses based on X86 framework |
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| CN201520958886.0U CN205139890U (en) | 2015-11-27 | 2015-11-27 | Two memory system that live of two accuses based on X86 framework |
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| CN205139890U true CN205139890U (en) | 2016-04-06 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106505694A (en) * | 2016-12-30 | 2017-03-15 | 卢文浩 | A kind of management system of intelligent battery group and control method |
| CN107122137A (en) * | 2017-04-26 | 2017-09-01 | 济南浪潮高新科技投资发展有限公司 | A kind of dual control storage system based on RapidIO |
| CN109901954A (en) * | 2019-02-25 | 2019-06-18 | 浙江大华技术股份有限公司 | Store equipment and method for managing resource |
| CN111338991A (en) * | 2020-02-20 | 2020-06-26 | 中国科学院自动化研究所 | Multi-mode storage system based on eMMC array |
| CN111666040A (en) * | 2019-03-08 | 2020-09-15 | 美光科技公司 | Apparatus, method and system relating to thermal equalization |
| CN117492664A (en) * | 2023-12-29 | 2024-02-02 | 柏科数据技术（深圳）股份有限公司 | Source data double-control double-activity storage control method, system, terminal and medium |
-
2015
- 2015-11-27 CN CN201520958886.0U patent/CN205139890U/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106505694A (en) * | 2016-12-30 | 2017-03-15 | 卢文浩 | A kind of management system of intelligent battery group and control method |
| CN106505694B (en) * | 2016-12-30 | 2018-12-25 | 卢文浩 | A kind of management system and control method of intelligent battery group |
| CN107122137A (en) * | 2017-04-26 | 2017-09-01 | 济南浪潮高新科技投资发展有限公司 | A kind of dual control storage system based on RapidIO |
| CN109901954A (en) * | 2019-02-25 | 2019-06-18 | 浙江大华技术股份有限公司 | Store equipment and method for managing resource |
| CN109901954B (en) * | 2019-02-25 | 2022-08-16 | 浙江大华技术股份有限公司 | Storage device and resource management method |
| CN111666040A (en) * | 2019-03-08 | 2020-09-15 | 美光科技公司 | Apparatus, method and system relating to thermal equalization |
| CN111338991A (en) * | 2020-02-20 | 2020-06-26 | 中国科学院自动化研究所 | Multi-mode storage system based on eMMC array |
| CN111338991B (en) * | 2020-02-20 | 2022-03-11 | 中国科学院自动化研究所 | Multi-mode storage system based on eMMC array |
| CN117492664A (en) * | 2023-12-29 | 2024-02-02 | 柏科数据技术（深圳）股份有限公司 | Source data double-control double-activity storage control method, system, terminal and medium |
| CN117492664B (en) * | 2023-12-29 | 2024-04-16 | 柏科数据技术（深圳）股份有限公司 | Source data double-control double-activity storage control method, system, terminal and medium |
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Granted publication date: 20160406 Termination date: 20171127 |
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