CN100490326C - Relatively prime mode parallel counter based on congruence theory - Google Patents
Relatively prime mode parallel counter based on congruence theory Download PDFInfo
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- CN100490326C CN100490326C CNB2005100099821A CN200510009982A CN100490326C CN 100490326 C CN100490326 C CN 100490326C CN B2005100099821 A CNB2005100099821 A CN B2005100099821A CN 200510009982 A CN200510009982 A CN 200510009982A CN 100490326 C CN100490326 C CN 100490326C
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- counter
- synchronous ring
- trigger
- synchronous
- counters
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Abstract
A relative prime modulo parallel counter based on the congruent theory relates to a counter of synchronous shift register type composed of a first, a second synchronous ring counters, and a decode unit, among which, the numbers of triggers in any two synchronous ring counters from the first to r are prime mutually, the clock pulse input ends of all synchronous ring counters are connected and linked to the clock pulse signals, the positive output or negative output end of each trigger in all said counters are connected to an input end of the decode unit. It uses the counter as its basic component and numbers of triggers in each are prime mutually, so a large count can be got with only a few ring counters.
Description
Technical field:
The present invention relates to a kind of synchronous shift register type counter.
Background technology:
Along with high-speed development of science and technology, modern society has proposed more and more higher requirement to the high speed and precision measurement in Electronic Testing field.The high-speed counting technology is an emphasis research topic in the electronic measurements field as the technical foundation of precision timing, frequency measurement.Counter is the parts of state variation in the reflection digital system, and pace of change is the relatively more crucial parameter of counter, and can it have directly determined counter be applicable in certain digital system.The sorting technique of counter has a variety of, whether synchronous from the variation of each carry-out bit, can be divided into coincidence counter and asynchronous counter, coincidence counter generally is made up of trigger and gate, and its maximal rate is by the delay and the logical relation decision of the trigger of forming coincidence counter and gate.In the process of design coincidence counter, usually to consider regularly this parameter of allowance, regularly allowance is to be used for weighing time slot or the extra time that each clock cycle keeps, if each trigger and gate all are assigned a big timing allowance in the design of coincidence counter, then this coincidence counter can be operated in stable state, raising along with clock frequency, regularly allowance reduces, the destabilizing factor of circuit increases, when clock frequency during near failure frequency, regularly allowance will arrive zero, and the coincidence counter circuit working enters labile state.The figure place of coincidence counter many more (mould is big more) in addition, needed gate is just many more, causes its failure frequency low more.Synchronously ring counter is based on the ring counter of shift register structure, and it is the highest a kind of of count frequency in the counter, and its reason is in its state turnover, does not need unnecessary gate that the order that keeps normal increasing or decreasing is provided.But,, in application of practical project, seldom obtain using again because this counter is more to the use of hardware resource because the order of this counter output state is not easy to describe.The coincidence counter ubiquity of existing structure is along with number of flip-flops in the counter increases, and the maximum count frequency must reduce this problem.
Summary of the invention:
The purpose of this invention is to provide a kind of relatively prime mould parallel counter based on congruence theory, it has overcome along with number of flip-flops in the counter increases, and the maximum count frequency reduces the ubiquitous problem of this conventional counter.It is by the first synchronous ring counter P
1, the second synchronous ring counter P
2The synchronous ring counter P of r
rForm the first synchronous ring counter P with decoding unit 2
1The synchronous ring counter P of～the r
rIn trigger number prime number each other all in any two synchronous ring counters, the clock pulse input terminal of trigger all links together and meets clock pulse signal clk in all synchronous ring counters, the positive output end of each trigger in all synchronous ring counters or anti-output all are connected on the input of decoding unit 2, during the counter initial condition, the positive output end of the first trigger of each synchronous ring counter all is " 1 ", and other all is " 0 ".During counter works of the present invention, all trigger elder generation zero clearings, each clock pulse then, digital " 1 " moves one between the trigger of synchronous ring counter inside, the data that all triggers are input to decoder 2 also take place once to change, and decoder 2 is translated into corresponding numerical value increase and decrease to the variation of input data and just finished counting work.The present invention constructs the coincidence counter group of relatively prime (mutually can not be a divided evenly) factor according to the Chinese remainder theorem in the Ancient Chinese algebra congruence theory, and r ring counter synchronously promptly arranged, and the mould of these synchronous ring counters is respectively n
1, n
2..., n
r(n
1, n
2..., n
rBe r relatively prime positive integer), the clock end of these synchronous ring counters is connected in parallel, the exportable status number n of this coincidence counter group is n so
1n
2N
r, it is n
1, n
2..., n
rLeast common multiple, suppose r whole zero clearings of counter zero hour, through arriving x state after x clock, the state of this r coincidence counter is respectively a at this moment
1, a
2... a
r, then there is following relational expression to set up,
X three (a
1N
1x
1+ a
2N
2x
2+ ... + a
rN
rx
r) (mod n
1n
2N
r) (1)
Wherein, N
j=n/n
j, 1≤j≤r, N
jBe the mould n of least common multiple n divided by j coincidence counter
j, N
jIn Ancient Chinese algebra, be called the number that spreads out; x
jBe called multiplying factor.By N
jx
j≡ 1 (mod n
j), 1≤j≤r can obtain x
jValue.The structure of relatively prime mould parallel counter group provided by the invention makes ring counter be convenient to be applied to make it the high speed performance of showing that it is exclusive in the engineering application.The invention has the beneficial effects as follows: the structure that adopts relatively prime mould parallel counter group, produce the big modulus high-speed counter of being convenient to use on the engineering, because it has used the basic module of synchronous ring counter as it, therefore overcome conventional counter along with modulus increases, the maximum count frequency reduces the ubiquitous problem of this conventional counter, because the number of trigger is relatively prime in each belt counter, therefore avoided the not unique situation of present condition, thereby just obtain very big counting with belt counter number seldom, for the high-speed and continuous counting provides a kind of practicable technological means.In the modulation domain measurement technology, wide figure place, high-speed synchronous counter are to measure no blanking time the Primary Component of (ZDT), when its maximum count frequency has directly determined to survey, the precision of frequency measurement.Each step of high-speed synchronous counter maximum count frequency is improved all the renewal that can bring performance index to modulation domain measurement and analytical technology, and has alleviated temporally interpolated pressure in the precise time-time-interval measuring technique effectively.Therefore the research to the high-speed synchronous counter has important practical significance.
Description of drawings;
Fig. 1 is the structural representation of embodiment of the present invention one, and Fig. 2 is the structural representation of execution mode two.
Embodiment:
Embodiment one: specify present embodiment below in conjunction with Fig. 1.It is by the first synchronous ring counter P
1, the second synchronous ring counter P
2The synchronous ring counter P of r
rForm the first synchronous ring counter P with decoding unit 2
1The synchronous ring counter P of～the r
rIn trigger number prime number each other all in any two synchronous ring counters, the clock pulse input terminal of trigger all links together and meets clock pulse signal clk in all synchronous ring counters, and the positive output end of each trigger in all synchronous ring counters or anti-output all are connected on the input of decoding unit 2.All triggers in the present embodiment are all selected " D " trigger for use, the input of the first trigger of each synchronous ring counter all links together with the output of terminal trigger, and the output of the front end trigger of each synchronous ring counter all is connected with the input of rear end trigger.During counter initial condition of the present invention, the positive output end of the first trigger of each synchronous ring counter all is " 1 ", and other all is " 0 ".Decoding unit 2 both can utilize formula (1) to program and realize counting, also can realize counting with hardware logic electric circuit.
Embodiment two: specify present embodiment below in conjunction with Fig. 2.It is by the first synchronous ring counter P
1, the second synchronous ring counter P
2The synchronous ring counter P of r
rForm the first synchronous ring counter P with decoding unit 2
1The synchronous ring counter P of～the r
rIn trigger number prime number each other all in any two synchronous ring counters, the clock pulse input terminal of trigger all links together and meets clock pulse signal clk in all synchronous ring counters, and the anti-output of each trigger in all synchronous ring counters all is connected on the input of decoding unit 2.All triggers in the present embodiment are all selected " D " trigger for use.
Claims (2)
1,, it is characterized in that it is by the first synchronous ring counter (P based on the relatively prime mould parallel counter of congruence theory
1), the second synchronous ring counter (P
2) ... synchronous ring counter (the P of r
r) and decoding unit (2) composition, the first synchronous ring counter (P
1Synchronous ring counter (the P of)～r
r) in trigger number prime number each other all in any two synchronous ring counters, the clock pulse input terminal of trigger all links together and connects clock pulse signal (clk) in all synchronous ring counters, the positive output end of each trigger in all synchronous ring counters or anti-output all are connected on the input of decoding unit (2), during the counter initial condition, the positive output end of the first trigger of each synchronous ring counter all is " 1 ", and other all is " 0 ".
2, the relatively prime mould parallel counter based on congruence theory according to claim 1 is characterized in that all triggers all select " D " trigger for use.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100099821A CN100490326C (en) | 2005-05-16 | 2005-05-16 | Relatively prime mode parallel counter based on congruence theory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100099821A CN100490326C (en) | 2005-05-16 | 2005-05-16 | Relatively prime mode parallel counter based on congruence theory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1688109A CN1688109A (en) | 2005-10-26 |
| CN100490326C true CN100490326C (en) | 2009-05-20 |
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ID=35306149
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100099821A Expired - Fee Related CN100490326C (en) | 2005-05-16 | 2005-05-16 | Relatively prime mode parallel counter based on congruence theory |
Country Status (1)
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|---|---|
| CN (1) | CN100490326C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110224762B (en) * | 2018-03-02 | 2021-11-30 | 科大国盾量子技术股份有限公司 | Pulse synchronization method and system |
-
2005
- 2005-05-16 CN CNB2005100099821A patent/CN100490326C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1688109A (en) | 2005-10-26 |
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Granted publication date: 20090520 Termination date: 20100516 |