CN100463160C - 双镶嵌布线和方法 - Google Patents

双镶嵌布线和方法 Download PDF

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Publication number
CN100463160C
CN100463160C CNB2005100562974A CN200510056297A CN100463160C CN 100463160 C CN100463160 C CN 100463160C CN B2005100562974 A CNB2005100562974 A CN B2005100562974A CN 200510056297 A CN200510056297 A CN 200510056297A CN 100463160 C CN100463160 C CN 100463160C
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CN
China
Prior art keywords
dual damascene
dielectric layer
conductive path
dual
path bar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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CNB2005100562974A
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English (en)
Chinese (zh)
Other versions
CN1722424A (zh
Inventor
托马斯·L.·麦克德维特
安东尼·K.·斯坦博
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Shanghai Youci Information Technology Co ltd
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International Business Machines Corp
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Publication date
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Publication of CN1722424A publication Critical patent/CN1722424A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H10W20/432—Layouts of interconnections comprising crossing interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497—Inductive arrangements or effects of, or between, wiring layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
CNB2005100562974A 2004-07-14 2005-04-05 双镶嵌布线和方法 Expired - Lifetime CN100463160C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/710,478 US7223684B2 (en) 2004-07-14 2004-07-14 Dual damascene wiring and method
US10/710,478 2004-07-14

Publications (2)

Publication Number Publication Date
CN1722424A CN1722424A (zh) 2006-01-18
CN100463160C true CN100463160C (zh) 2009-02-18

Family

ID=35598615

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005100562974A Expired - Lifetime CN100463160C (zh) 2004-07-14 2005-04-05 双镶嵌布线和方法

Country Status (4)

Country Link
US (2) US7223684B2 (https=)
JP (1) JP5229710B2 (https=)
CN (1) CN100463160C (https=)
TW (1) TWI341568B (https=)

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US7545045B2 (en) * 2005-03-24 2009-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy via for reducing proximity effect and method of using the same
US7615476B2 (en) * 2005-06-30 2009-11-10 Intel Corporation Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages
US7524595B2 (en) * 2005-09-08 2009-04-28 United Microelectronics Corp. Process for forming anti-reflection coating and method for improving accuracy of overlay measurement and alignment
KR100737155B1 (ko) * 2006-08-28 2007-07-06 동부일렉트로닉스 주식회사 반도체 소자의 고주파 인덕터 제조 방법
CN101154046B (zh) * 2006-09-30 2010-12-22 中芯国际集成电路制造(上海)有限公司 双镶嵌结构的制造方法
US7488682B2 (en) * 2006-10-03 2009-02-10 International Business Machines Corporation High-density 3-dimensional resistors
US7608538B2 (en) 2007-01-05 2009-10-27 International Business Machines Corporation Formation of vertical devices by electroplating
US8952547B2 (en) 2007-07-09 2015-02-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with contact structure with first/second contacts formed in first/second dielectric layers and method of forming same
US8299622B2 (en) 2008-08-05 2012-10-30 International Business Machines Corporation IC having viabar interconnection and related method
US8138036B2 (en) * 2008-08-08 2012-03-20 International Business Machines Corporation Through silicon via and method of fabricating same
JP2010141097A (ja) * 2008-12-11 2010-06-24 Panasonic Corp 半導体装置及びその製造方法
JP2010153543A (ja) * 2008-12-25 2010-07-08 Fujitsu Ltd 半導体装置およびその製造方法
US8659156B2 (en) 2011-10-18 2014-02-25 International Business Machines Corporation Interconnect structure with an electromigration and stress migration enhancement liner
US9076848B2 (en) 2013-03-12 2015-07-07 International Business Machines Corporation Semiconductor device channels
US9111935B2 (en) * 2013-03-12 2015-08-18 International Business Machines Corporation Multiple-patterned semiconductor device channels
US9099471B2 (en) 2013-03-12 2015-08-04 International Business Machines Corporation Semiconductor device channels
US9831214B2 (en) * 2014-06-18 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
US10177032B2 (en) * 2014-06-18 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaging devices, and methods of packaging semiconductor devices
US10461149B1 (en) * 2018-06-28 2019-10-29 Micron Technology, Inc. Elevationally-elongated conductive structure of integrated circuitry, method of forming an array of capacitors, method of forming DRAM circuitry, and method of forming an elevationally-elongated conductive structure of integrated circuitry
US10475796B1 (en) 2018-06-28 2019-11-12 Micron Technology, Inc. Method of forming an array of capacitors, a method of forming DRAM circuitry, and a method of forming an elevationally-elongated conductive structure of integrated circuitry
US11101171B2 (en) 2019-08-16 2021-08-24 Micron Technology, Inc. Apparatus comprising structures including contact vias and conductive lines, related methods, and memory devices
US12598983B2 (en) * 2021-11-11 2026-04-07 International Business Machines Corporation Interconnects formed using integrated damascene and subtractive etch processing

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CN1402326A (zh) * 2001-08-22 2003-03-12 矽统科技股份有限公司 利用镶嵌制程形成金属电容器的方法及其产品
US6670274B1 (en) * 2002-10-01 2003-12-30 Taiwan Semiconductor Manufacturing Company Method of forming a copper damascene structure comprising a recessed copper-oxide-free initial copper structure
US6740392B1 (en) * 2003-04-15 2004-05-25 Micron Technology, Inc. Surface barriers for copper and silver interconnects produced by a damascene process

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US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
JPH1065101A (ja) * 1996-08-22 1998-03-06 Sony Corp 半導体装置
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JP4502173B2 (ja) * 2003-02-03 2010-07-14 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
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US6670274B1 (en) * 2002-10-01 2003-12-30 Taiwan Semiconductor Manufacturing Company Method of forming a copper damascene structure comprising a recessed copper-oxide-free initial copper structure
US6740392B1 (en) * 2003-04-15 2004-05-25 Micron Technology, Inc. Surface barriers for copper and silver interconnects produced by a damascene process

Also Published As

Publication number Publication date
TW200629470A (en) 2006-08-16
US20060012052A1 (en) 2006-01-19
JP2006054433A (ja) 2006-02-23
JP5229710B2 (ja) 2013-07-03
CN1722424A (zh) 2006-01-18
US20070128848A1 (en) 2007-06-07
TWI341568B (en) 2011-05-01
US7709905B2 (en) 2010-05-04
US7223684B2 (en) 2007-05-29

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Effective date of registration: 20210414

Address after: 116 Lu'an Road, Nanhui new town, Pudong New Area, Shanghai

Patentee after: Shanghai Youci Information Technology Co.,Ltd.

Address before: New York, USA

Patentee before: International Business Machines Corp.

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Granted publication date: 20090218

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