TWI341568B - Dual damascene wiring and method - Google Patents

Dual damascene wiring and method

Info

Publication number
TWI341568B
TWI341568B TW094123018A TW94123018A TWI341568B TW I341568 B TWI341568 B TW I341568B TW 094123018 A TW094123018 A TW 094123018A TW 94123018 A TW94123018 A TW 94123018A TW I341568 B TWI341568 B TW I341568B
Authority
TW
Taiwan
Prior art keywords
dual damascene
damascene wiring
wiring
dual
damascene
Prior art date
Application number
TW094123018A
Other languages
English (en)
Chinese (zh)
Other versions
TW200629470A (en
Inventor
Thomas L Mcdevitt
Anthony K Stamper
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200629470A publication Critical patent/TW200629470A/zh
Application granted granted Critical
Publication of TWI341568B publication Critical patent/TWI341568B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H10W20/432—Layouts of interconnections comprising crossing interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497—Inductive arrangements or effects of, or between, wiring layers
TW094123018A 2004-07-14 2005-07-07 Dual damascene wiring and method TWI341568B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/710,478 US7223684B2 (en) 2004-07-14 2004-07-14 Dual damascene wiring and method

Publications (2)

Publication Number Publication Date
TW200629470A TW200629470A (en) 2006-08-16
TWI341568B true TWI341568B (en) 2011-05-01

Family

ID=35598615

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094123018A TWI341568B (en) 2004-07-14 2005-07-07 Dual damascene wiring and method

Country Status (4)

Country Link
US (2) US7223684B2 (https=)
JP (1) JP5229710B2 (https=)
CN (1) CN100463160C (https=)
TW (1) TWI341568B (https=)

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US7545045B2 (en) * 2005-03-24 2009-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy via for reducing proximity effect and method of using the same
US7615476B2 (en) * 2005-06-30 2009-11-10 Intel Corporation Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages
US7524595B2 (en) * 2005-09-08 2009-04-28 United Microelectronics Corp. Process for forming anti-reflection coating and method for improving accuracy of overlay measurement and alignment
KR100737155B1 (ko) * 2006-08-28 2007-07-06 동부일렉트로닉스 주식회사 반도체 소자의 고주파 인덕터 제조 방법
CN101154046B (zh) * 2006-09-30 2010-12-22 中芯国际集成电路制造(上海)有限公司 双镶嵌结构的制造方法
US7488682B2 (en) * 2006-10-03 2009-02-10 International Business Machines Corporation High-density 3-dimensional resistors
US7608538B2 (en) 2007-01-05 2009-10-27 International Business Machines Corporation Formation of vertical devices by electroplating
US8952547B2 (en) 2007-07-09 2015-02-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with contact structure with first/second contacts formed in first/second dielectric layers and method of forming same
US8299622B2 (en) 2008-08-05 2012-10-30 International Business Machines Corporation IC having viabar interconnection and related method
US8138036B2 (en) * 2008-08-08 2012-03-20 International Business Machines Corporation Through silicon via and method of fabricating same
JP2010141097A (ja) * 2008-12-11 2010-06-24 Panasonic Corp 半導体装置及びその製造方法
JP2010153543A (ja) * 2008-12-25 2010-07-08 Fujitsu Ltd 半導体装置およびその製造方法
US8659156B2 (en) 2011-10-18 2014-02-25 International Business Machines Corporation Interconnect structure with an electromigration and stress migration enhancement liner
US9076848B2 (en) 2013-03-12 2015-07-07 International Business Machines Corporation Semiconductor device channels
US9111935B2 (en) * 2013-03-12 2015-08-18 International Business Machines Corporation Multiple-patterned semiconductor device channels
US9099471B2 (en) 2013-03-12 2015-08-04 International Business Machines Corporation Semiconductor device channels
US9831214B2 (en) * 2014-06-18 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
US10177032B2 (en) * 2014-06-18 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaging devices, and methods of packaging semiconductor devices
US10461149B1 (en) * 2018-06-28 2019-10-29 Micron Technology, Inc. Elevationally-elongated conductive structure of integrated circuitry, method of forming an array of capacitors, method of forming DRAM circuitry, and method of forming an elevationally-elongated conductive structure of integrated circuitry
US10475796B1 (en) 2018-06-28 2019-11-12 Micron Technology, Inc. Method of forming an array of capacitors, a method of forming DRAM circuitry, and a method of forming an elevationally-elongated conductive structure of integrated circuitry
US11101171B2 (en) 2019-08-16 2021-08-24 Micron Technology, Inc. Apparatus comprising structures including contact vias and conductive lines, related methods, and memory devices
US12598983B2 (en) * 2021-11-11 2026-04-07 International Business Machines Corporation Interconnects formed using integrated damascene and subtractive etch processing

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US5055423A (en) * 1987-12-28 1991-10-08 Texas Instruments Incorporated Planarized selective tungsten metallization system
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
JPH1065101A (ja) * 1996-08-22 1998-03-06 Sony Corp 半導体装置
JP3164025B2 (ja) * 1997-08-04 2001-05-08 日本電気株式会社 半導体集積回路装置及びその製造方法
US6133144A (en) * 1999-08-06 2000-10-17 Taiwan Semiconductor Manufacturing Company Self aligned dual damascene process and structure with low parasitic capacitance
US6429119B1 (en) * 1999-09-27 2002-08-06 Taiwan Semiconductor Manufacturing Company Dual damascene process to reduce etch barrier thickness
US6611060B1 (en) 1999-10-04 2003-08-26 Kabushiki Kaisha Toshiba Semiconductor device having a damascene type wiring layer
US6566258B1 (en) 2000-05-10 2003-05-20 Applied Materials, Inc. Bi-layer etch stop for inter-level via
JP2002198424A (ja) * 2000-12-27 2002-07-12 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6566242B1 (en) * 2001-03-23 2003-05-20 International Business Machines Corporation Dual damascene copper interconnect to a damascene tungsten wiring level
JP4050876B2 (ja) * 2001-03-28 2008-02-20 富士通株式会社 半導体集積回路装置とその製造方法
CN1248303C (zh) * 2001-08-22 2006-03-29 联华电子股份有限公司 利用镶嵌制程形成金属电容器的方法及其产品
US20030139034A1 (en) 2002-01-22 2003-07-24 Yu-Shen Yuang Dual damascene structure and method of making same
US6579795B1 (en) 2002-04-02 2003-06-17 Intel Corporation Method of making a semiconductor device that has copper damascene interconnects with enhanced electromigration reliability
JP2004031439A (ja) * 2002-06-21 2004-01-29 Renesas Technology Corp 半導体集積回路装置およびその製造方法
US6784478B2 (en) * 2002-09-30 2004-08-31 Agere Systems Inc. Junction capacitor structure and fabrication method therefor in a dual damascene process
US6670274B1 (en) * 2002-10-01 2003-12-30 Taiwan Semiconductor Manufacturing Company Method of forming a copper damascene structure comprising a recessed copper-oxide-free initial copper structure
JP4502173B2 (ja) * 2003-02-03 2010-07-14 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US6740392B1 (en) * 2003-04-15 2004-05-25 Micron Technology, Inc. Surface barriers for copper and silver interconnects produced by a damascene process
US6987059B1 (en) * 2003-08-14 2006-01-17 Lsi Logic Corporation Method and structure for creating ultra low resistance damascene copper wiring

Also Published As

Publication number Publication date
TW200629470A (en) 2006-08-16
CN100463160C (zh) 2009-02-18
US20060012052A1 (en) 2006-01-19
JP2006054433A (ja) 2006-02-23
JP5229710B2 (ja) 2013-07-03
CN1722424A (zh) 2006-01-18
US20070128848A1 (en) 2007-06-07
US7709905B2 (en) 2010-05-04
US7223684B2 (en) 2007-05-29

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MM4A Annulment or lapse of patent due to non-payment of fees